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Available online , doi: 10.11999/JEIT250144
Abstract:
Objective Internet of Vehicles (IoV) faces emerging threats from quantum computing. NTRU lattice offers an effective approach to achieve anti-quantum security in data sharing. This study develops a decentralized anti-quantum IoV data sharing scheme. New scheme ensures the IND-CCA2 and UF-CMA security under the hardness of NTRU lattice computing problem; it uses short keys and small storage space to maintain low calculation complexity. Blockchain is employed to support the vehicle authentication, access control, key distribution and automated execution of smart contracts. New scheme provides a reliable anti-quantum solution for IoV data sharing and technical support for future development of intelligent transportation. Methods Based on unique identifiers and attribute set, the smart contract uses the Gaussian sampling algorithm to generate partial private keys and attribute private keys for users. Public–private key pairs are obtained during the key generation phase. IoV model integrates the blockchain, smart contracts, IPFS, RSUs, and OBUs. Smart contracts store and verify the data-sharing records, while IPFS stores encrypted IoV data to enhance the reliability and reduce the storage cost. RSUs collect the data uploaded by OBUs and forward it to the blockchain which broadcasts real-time traffic information to vehicles. Smart contracts dynamically evaluate the user permissions according to predefined access policies and trigger corresponding operations. Concurrent access experiments were conducted in large-scale and dynamic IoV scenario. Simulations under varying concurrent OBU access requests demonstrated that distributed blockchain architecture and smart contract permission verification enables the system to maintain stable performance under high concurrency. Results and Discussions The proposed scheme computes the data sharing signcryption strategy in accordance with current IoV security requirements. Table 2 compares its security characteristics and communication overhead. Table 3 reports four instances of private key, ciphertext and signature sizes, showing that the proposed scheme requires less overhead. Table 4 demonstrates that, as the number of concurrent users increases from 100 to 1000 , the proposed scheme achieves lower total latency and more linear Throughput-Per-Second (TPS) growth compared with scheme [9]. Figure 3 illustrates that although the time consumption of all schemes increases with higher parameter values, the proposed scheme consistently exhibits the lowest time cost. Conclusions In the proposed scheme, the user private keys are bound to attribute sets and the data access is controlled by predefined access policies. This design ensures that only users with specific attributes can perform unsigncryption, thereby enabling fine-grained access control. The trapdoor generation and Gaussian sampling algorithms within the NTRU lattice reduce key size while ensuring anti-quantum security for IoV data transmission and storage. The integration of IPFS, blockchain, and smart contracts enables efficient index management and permission control, which strengthens the reliability of IoV system. The scheme supports concurrent access by large numbers of IoV users and has the potential to mitigate traffic accidents.
Available online , doi: 10.11999/JEIT250552
Abstract:
Objective Traditional Belief Propagation–Ordered Statistics Decoding (BP-OSD) algorithms for quantum error-correcting codes often rely on a single normalization factor (\begin{document}$ \alpha $\end{document} \begin{document}$ \alpha $\end{document} \begin{document}$ \alpha $\end{document} \begin{document}$ \alpha $\end{document} \begin{document}$ {\alpha }_{0} $\end{document} Methods The proposed enhanced BP-OSD algorithm (Algorithm 1) introduces a two-stage decoding process. In the first stage, decoding is attempted using standard BP with a single predetermined normalization factor (\begin{document}$ {\alpha }_{0} $\end{document} \begin{document}$ L $\end{document} \begin{document}$ \left\{{\alpha }_{1},{\alpha }_{2}, \cdots,{\alpha }_{L}\right\} $\end{document} Results and Discussions The effectiveness of the proposed algorithm is evaluated through Monte Carlo simulations on both Surface codes \begin{document}$ \left[\kern-0.15em\left[ {2{d}^{2}-2d+\mathrm{1,1},d} \right]\kern-0.15em\right] $\end{document} \begin{document}$ \left[\kern-0.15em\left[ {\mathrm{882,24}} \right]\kern-0.15em\right] $\end{document} Fig. 4(a) ). The error threshold is improved from approximately \begin{document}$ 15.5\% $\end{document} \begin{document}$ 18.3\% $\end{document} Fig. 4(b) demonstrates that, particularly at low physical error rates, the proposed algorithm maintains a decoding speed comparable to the original BP algorithm. This efficiency results from the two-stage design, in which the more computationally intensive parameter-listed search is activated only when required. For QLDPC codes (Fig. 5(a) , the proposed algorithm outperforms both the original BP and BP-OSD algorithms in terms of logical error rate, even when a smaller OSD candidate list per α value is employed. As shown in Table 3 , increasing the parameter list size L (e.g., \begin{document}$ L=\mathrm{4,8},16 $\end{document} Table 2 ) decreases rapidly as the physical error rate declines, confirming the efficiency of the two-stage framework. Conclusions An enhanced BP-OSD algorithm for quantum error-correcting codes is presented, featuring a parameter-listing strategy for the normalization factor (\begin{document}$ \alpha $\end{document} \begin{document}$ \alpha $\end{document} \begin{document}$ \alpha $\end{document} \begin{document}$ {\alpha }_{0} $\end{document}
Available online , doi: 10.11999/JEIT250535
Abstract:
Objective Microwave meteorological radar has broad application potential in rainfall detection due to its non-contact measurement, high spatiotemporal resolution, and multi-parameter retrieval capability. However, in the context of climate change, increasingly complex rainfall events require monitoring systems to deliver high-precision, multi-dimensional, real-time data to support disaster warning and climate research. Conventional single-mode radars, constrained by fixed functionalities, cannot fully meet these requirements, which has led to the development of multi-mode radar technology. The dual-mode radar examined in this study employs Frequency Modulated Continuous Wave (FMCW) and Continuous Wave (CW) modes. These modes adopt different algorithmic principles for raindrop velocity measurement: FMCW enables spatially stratified detection and strong anti-interference performance, whereas CW provides more accurate measurements of raindrop fall speed, yielding integral rainfall information in the vertical column. Despite these advantages, retrieval accuracy remains limited by the reliance of traditional algorithms on fixed empirical parameters, which restrict adaptability to regional climate variations and dynamic microphysical precipitation processes, and hinder real-time response to variations in rain Drop Size Distribution (DSD). Ground rain gauges, by contrast, provide near-true reference data through direct measurement of rainfall intensity. To address the above challenges, this paper proposes a dynamic inversion algorithm that integrates dual-mode (FMCW–CW) radar with rain gauge data, enhancing adaptability and retrieval accuracy for rainfall monitoring. Methods Two models are developed for the two radar modes. For the FMCW mode, which can retrieve DSD parameters, a fusion algorithm based on Attention integrated with a double-layer Long Short-Term Memory (LSTM) network (LSTM–Attention–LSTM) is proposed. The first LSTM extracts features from DSD data and rain gauge–measured rainfall intensity through its hidden state output, with a dropout layer applied to randomly discard neurons and reduce overfitting. The Attention mechanism calculates feature similarity using dot products and converts it into attention weights. The second LSTM then processes the time series and integrates the hidden-layer features, which are passed through a fully connected layer to generate the retrieval results. For the CW mode, which cannot directly retrieve DSD parameters and is constrained to the reflectivity factor–Rainfall rate (Z–R) relationship (Z=aRb), an algorithm based on the Extended Kalman Filter (EKF) is proposed to optimize this relationship. The method dynamically models the Z–R parameters, computes the residual between predicted rainfall intensity and rain gauge observations, and updates the prior estimates accordingly. Physical constraints are applied to parameters a and b during state updates to ensure consistency with physical laws, thereby enabling accurate fitting of the Z–R relationship. Results and Discussions Experimental results show that both models enhance the accuracy of rainfall intensity retrieval. For the FMCW mode, the LSTM–Attention–LSTM model applied to the test dataset outperforms traditional physical models, single-layer LSTM, and double-layer LSTM. It effectively captures the temporal variation of rainfall intensity, with the absolute error relative to observed values remaining below 0.25 mm/h (Fig. 5 ). Compared with the traditional physical model, the LSTM–Attention–LSTM reduces RMSE and MAE by 46% and 38%, achieving values of 0.1623 mm/h and 0.147 mm/h, respectively, and increases R2 by 14.5% to 0.95 (Table 2 ). For the CW mode, the Z–R relationship optimized by the EKF model provides the best fit for the Z and R distribution in the validation dataset (Fig. 6 ). Rainfall intensity retrieved with this algorithm on the test set exhibits the smallest deviation from actual observations compared with convective cloud empirical formulas, Beijing plain area empirical formulas, and the dynamic Z–R method. The corresponding RMSE, MAE, and R2 reach 0.1076 mm/h, 0.094 mm/h, and 0.972, respectively (Fig. 7 ; Table 4 ). Conclusions This study proposes two multi-source data fusion schemes that integrate dual-mode radar with rain gauges for short-term rainfall monitoring. Experimental results confirm that both methods significantly improve the accuracy of rainfall intensity retrieval and demonstrate strong dynamic adaptability and robustness.
Available online , doi: 10.11999/JEIT250525
Abstract:
Objective The real-time channel emulator is a critical tool in wireless device research and development, enabling accurate and repeatable experiments in controlled laboratory environments. This capability reduces testing costs by avoiding extensive field trials and accelerates development cycles by allowing rapid iteration and validation of wireless devices under realistic conditions. With the rapid advancement of aerial platforms—including drones, High-Altitude Pseudo-Satellites (HAPS), and Unmanned Aerial Vehicles (UAVs)—for integrated sensing and communication, high-resolution imaging, and environmental reconstruction in complex wireless environments, the challenges of channel modeling have increased considerably. In particular, there is growing demand for real-time simulation of wide-range multipath delay spread channels. Existing simulation methods, although effective in traditional scenarios, face substantial limitations in hardware storage resources when handling such channels. This study addresses these limitations by proposing an efficient storage method for real-time emulation of wide-range multipath channels. The method reduces memory overhead while preserving high fidelity in channel reproduction, thereby offering a practical and optimized solution for next-generation wireless communication research. Methods In conventional real-time channel emulation, a combined simulation approach is adopted, employing cascaded common delay and multipath delay spread components. The common delay component is implemented using a single high-capacity memory module, whereas the multipath delay spread component is implemented using a Dense Tapped Delay Line (D-TDL). This design reduces storage resource requirements by multiplexing the common delay component, but the achievable multipath delay spread range remains limited. Moreover, the multipath delay is constrained by the common delay component, reducing flexibility and compromising the ability to emulate complex scenarios. The Sparse Tapped Delay Line (S-TDL) scheme is used in some algorithms to extend the multipath delay emulation range by cascading block memory modules. However, this method introduces inter-tap delay dependencies and cannot adapt to the requirements of wide-range multipath delay spread channels. Alternatively, Time-Division Multiplexing (TDM) is applied in other algorithms to improve the utilization efficiency of block memory modules and decouple multipath delay control. Despite this, TDM is constrained by the read/write bandwidth of memory, making it unsuitable for real-time channel emulation of large-bandwidth signals. To overcome the multi-tap delay coupling issue in the S-TDL algorithm, an Optimized Sparse Tapped Delay Line (OS-TDL) algorithm is proposed. By analyzing delay-dependent relationships among multipath taps, theoretical derivation establishes an analytical relationship between the number of multipaths and the delay spread range achievable under decoupling constraints. Redundant taps are introduced to eliminate inter-tap delay dependencies, enabling flexible configuration of arbitrary multipath delay combinations. The algorithm formulates a joint optimization model that balances hardware memory allocation and multipath delay spread fidelity, supports wide-range multipath scenarios without being limited by memory read/write bandwidth, and allows real-time emulation of large-bandwidth signals. The central innovation lies in dynamically constraining tap activation and sparsity patterns to reduce redundant memory while preserving wide-range multipath delay spread channel characteristics. Compared with conventional approaches, the proposed algorithm significantly enhances storage resource utilization efficiency in wide-range multipath channel emulation. On this basis, a concrete algorithmic procedure is developed, in which an input multipath delay sequence is computationally processed to derive delay configuration parameters and activation sequences for multiple cascaded memory units. Comprehensive validation procedures for the algorithm are presented in later sections. Results and Discussions Conventional S-TDL algorithms are constrained by inter-tap delay coupling, which limits their ability to achieve high-fidelity emulation of wide-range multipath delay variations. To overcome this limitation, a comparative simulation of three algorithms—the memory resource exclusive algorithm, the TDM memory resource algorithm, and the OS-TDL algorithm proposed herein—is systematically conducted. A controlled variable approach is employed to evaluate storage resource utilization efficiency across three key dimensions: signal sampling rate, number of emulated multipath components, and multipath delay spread range. Theoretical analysis and simulation results show that the proposed OS-TDL algorithm significantly reduces memory requirements compared with conventional methods, while maintaining emulation fidelity. Its effectiveness is further verified through experimental implementation on AMD’s Virtex UltraScale+ series high-performance Field-Programmable Gate Array (FPGA), using the XCVU13P verification platform. Comparative FPGA resource measurements under identical system specifications confirm the superiority of the proposed algorithm, demonstrating its ability to improve memory efficiency while accurately reproducing wide-range multipath delay spread channels. Conclusions This study addresses the challenge of storage resource utilization efficiency in real-time channel emulation for wide-range multipath delay spread by analyzing the inter-tap delay dependency inherent in conventional S-TDL algorithms. An OS-TDL algorithm is proposed to emulate wide-range multipath delay spread channels. Both simulation and hardware verification results demonstrate that the proposed algorithm substantially improves storage efficiency while accurately reproducing multipath wide-range delay spread characteristics. These findings confirm that the algorithm meets the design requirements of real-time channel emulators for increasingly complex verification scenarios.
Available online , doi: 10.11999/JEIT250084
Abstract:
Objective The emergence of clustered target communication networks complicates electromagnetic environment detection in non-cooperative scenarios, creating challenges for electromagnetic situation awareness and electronic countermeasures. Existing research seldom addresses topology prediction under conditions with no prior knowledge, where the absence of explicit structural information and the dynamic nature of the networks hinder accurate inference. This study investigates topology prediction for non-cooperative clustered wireless communication networks using graph-structured data-driven approaches. Specifically, it evaluates the performance of multiple topology inference methods, including the Multivariate Hawkes Process (MHP), Peter–Clark Momentary Conditional Independence (PCMCI), Graph Encoder–Decoder (GED), and Graph Convolutional Networks (GCN). The effects of network properties such as node count and edge probability on inference accuracy are analyzed. Additionally, a hybrid framework that integrates statistical models with graph-based learning is explored to improve inference accuracy and computational efficiency. Methods The proposed methodology combines causal inference with Graph Neural Network (GNN)–based learning. Adjacency matrices are first generated through causal discovery, using time-domain matrices derived from simulated wireless communication events. These matrices are constructed by thresholding power spectra to yield binary communication states. The GNN module subsequently refines the causal discovery output by suppressing false positives and optimizing global topology through encoder–decoder operations with multi-head attention mechanisms. To assess robustness, synthetic datasets are generated with NS-3 simulations under varying conditions: edge probabilities (0.15–0.60), node densities (8–13 nodes), sampling durations (0.05–0.30 ms), and node feature completeness (partial, 50%; full, 100%). Connectivity patterns are modeled by incorporating distance-adjusted edge probabilities. Performance evaluation uses F1-score, accuracy, recall, and inference time, with systematic comparison across baseline models (MHP, PCMCI, GCN, GED) and hybrid variants (PCMCI+GED, MHP+GED). Results and Discussions The PCMCI+GED hybrid framework consistently achieves superior topology prediction across diverse network configurations. At an edge probability of 0.45, PCMCI+GED with full node features attains an F1-score of 0.808, exceeding the performance of standalone PCMCI and GED by 31.1% and 4.9%, respectively (Fig. 7 ). This improvement arises from the synergy between causal priors and graph neural networks: PCMCI establishes preliminary causal relationships, while GED refines inference through global attention mechanisms that reduce false positives. Comparative analysis reveals that richer node features enhance topology inference in causal inference methods (Fig. 7 ). For example, MHP+GED with full features exceeds its 50% feature counterpart by 2.10%, and PCMCI+GED with full features improves by 3.04%. Yet, the most substantial gains come from combining causal inference with GED. Relative to standalone MHP with full features, MHP+GED improves by 30.65% with 50% features and 33.40% with full features. Similarly, PCMCI+GED improves by 34.43% and 38.51% under the same conditions. In contrast, relying solely on GNNs proves insufficient for modeling causal relationships. GED alone performs similarly to GCN, with Mean Absolute Error (MAE) and Root Mean Squared Error (RMSE) values of 0.0149 and 0.0206 , respectively (Fig. 8 ). Without causal priors, GED offers no significant advantage over GCN; however, when priors are incorporated, GED outperforms GCN in inference accuracy (Fig. 9 ). Sampling duration analysis shows that 0.1 ms is optimal, balancing redundancy and information loss (Fig. 10 , Table 2 ). Shorter intervals (0.05 ms) inflate computational costs through high-dimensional operations, whereas longer intervals (0.30 ms) obscure temporal dependencies, reducing the F1-score of PCMCI+GED with full features to 40.57% of its value at 0.1 ms. Efficiency evaluations highlight trade-offs between accuracy and runtime. With 50% node features, PCMCI+GED reduces inference time by 88.63% while retaining 96.96% of its F1-score. Under the same conditions, MHP+GED reduces inference time by 85.48% with only a 2.07% drop in performance (Fig. 11 ). PCMCI’s exponential complexity makes it computationally prohibitive in high-dimensional settings, whereas MHP’s quadratic scaling with node count and linear scaling with event frequency yield more modest efficiency gains. In low-dimensional settings, however, MHP’s event-driven computation leads to longer runtimes than PCMCI. Heatmap analysis further confirms the precision of the hybrid models. Adjacency matrices generated by PCMCI+GED and MHP+GED with full features closely align with the ground truth, demonstrating high predictive accuracy (Fig. 9 ). In sparse networks, standalone PCMCI introduces noise by linking non-interacting nodes, while GCN generates fragmented predictions due to the absence of causal priors. The hybrid framework alleviates these limitations by combining PCMCI’s local causal inference with GED’s global optimization. Overall, the hybrid framework addresses key shortcomings of individual methods: the high computational cost of PCMCI and MHP, and the limited interpretability of GNNs. By integrating causal discovery with graph-based deep learning, the model achieves state-of-the-art predictive accuracy while maintaining scalability. Its performance highlights the potential for real-time applications in resource-constrained environments, emphasizing the importance of balancing causal priors and data-driven learning for advancing non-cooperative wireless communication network analysis. Conclusions This study demonstrates the effectiveness of combining PCMCI-based causal inference with GED-enhanced GNN for topology prediction in non-cooperative clustered wireless communication networks. The hybrid model achieves state-of-the-art accuracy, particularly in dense networks, while partial node feature inputs substantially reduce computational overhead. Although the exponential complexity of PCMCI constrains scalability in high-dimensional settings, integration with GED alleviates this limitation through feature reduction and global optimization. The findings highlight the need to balance accuracy and efficiency in practical applications, where GCN offers a viable option for real-time inference. Future research will explore attention mechanisms and self-supervised learning to further enhance robustness. These advancements hold promise for improving electromagnetic situation awareness and electronic countermeasure strategies in dynamic adversarial environments.
Available online , doi: 10.11999/JEIT250231
Abstract:
Objective With the rapid development of Sixth-Generation (6G) communication technology, Integrated Sensing And Communication (ISAC) systems are regarded as key enablers of emerging applications such as the Internet of Things, smart cities, and autonomous driving. High-precision communication and sensing are required under limited spectrum resources. However, most existing studies concentrate on the far-field region, where incomplete derivation of the sensing mutual information metric, neglect of scatterer interference, and insufficient consideration of communication–sensing trade-offs limit the flexibility of beamforming design and reduce practical effectiveness. As application scenarios expand, the demand for efficient integration of communication and sensing becomes more pronounced, particularly in near-field environments where scatterer interference strongly affects system performance In this work, beamforming design for near-field ISAC systems under scatterer interference is investigated. A general expression for sensing mutual information is derived, a multi-objective optimization problem is formulated, and auxiliary variables, the Schur complement, and the Dinkelbach algorithm are employed to obtain Pareto optimal solutions. The proposed method provides a flexible and effective approach for balancing communication and sensing performance, thereby enhancing overall system performance and resource utilization in diverse application scenarios. The findings serve as a valuable reference for the optimal trade-off design of communication and sensing in near-field ISAC systems. Methods The proposed beamforming design method first derives a general expression for sensing mutual information in near-field scenarios, explicitly accounting for and quantifying the effect of scatterer interference on sensing targets. A multi-objective optimization problem is then formulated, with the Signal-to-Interference-plus-Noise Ratio (SINR) of communication users and sensing mutual information as objectives. Within this multi-objective framework, communication and sensing performance can be flexibly balanced to satisfy the requirements of different application scenarios. To enable tractable optimization, the sensing mutual information expression is transformed into a Semi-Definite Programming (SDP) problem using auxiliary variables and the Schur complement. Multi-user SINR expressions are reformulated with the Dinkelbach algorithm to convert them into convex functions, facilitating efficient optimization. The multi-objective problem is subsequently reduced to a single-objective one by constructing a system utility function, and the Pareto optimal solution is obtained to achieve the optimal balance between communication and sensing performance. This method provides a flexible and effective design strategy for near-field ISAC systems, substantially enhancing overall system performance and resource utilization. Results and Discussions This study presents a beamforming design method that balances communication and sensing performance through innovative optimization strategies. The method derives the general expression of sensing mutual information under scatterer interference, formulates a multi-objective optimization problem with the SINR of communication users and sensing mutual information as objectives, and transforms the problem into a convex form using auxiliary variables, the Schur complement, and the Dinkelbach algorithm. The Pareto optimal solution is then obtained via a system utility function, enabling the optimal balance between communication and sensing performance. Simulation results demonstrate that adjusting the weight parameter ρ flexibly balances user communication and target sensing performance (Fig. 2 ). As ρ increases from 0 to 1, sensing mutual information rises while user rate decreases, showing that a controllable trade-off can be achieved by tuning weights. In multi-user scenarios, near-field ISAC systems exhibit superior performance compared with far-field systems (Fig. 3 ). Under near-field conditions, the proposed method achieves more flexible and adjustable trade-offs than the classic Zero-Forcing (ZF) algorithm and single-objective optimization algorithms (Fig. 4 , Fig. 5 ), confirming its effectiveness and superiority in practical applications. Furthermore, the study reveals the interference pattern of scatterers on sensing targets with respect to distance (Fig. 6 , Fig. 7 ). The results indicate that the greater the distance difference between a scatterer and a sensing target, the weaker the interference on the target, with sensing mutual information gradually increasing and eventually converging. This finding provides a valuable reference for the design of near-field ISAC systems. Conclusions This paper proposes a beamforming design method for balancing communication and sensing performance by jointly optimizing sensing mutual information and communication rate. The method derives the general form of sensing mutual information, reformulates it as a SDP problem, and applies the Dinkelbach algorithm to process multi-user SINR expressions, thereby establishing a multi-objective optimization framework that can flexibly adapt to diverse application requirements. The results demonstrate three key findings: (1) The method enables flexible adjustment of communication and sensing performance, achieving an optimal trade-off through weight tuning, and allowing dynamic adaptation of system performance to specific application needs. (2) It reveals the interference pattern of scatterers on sensing targets with respect to distance, providing critical insights for near-field ISAC system design and supporting optimized system layout and parameter selection in complex environments. (3) In multi-user scenarios, the proposed approach outperforms traditional single-objective optimization methods in both communication rate and sensing mutual information, highlighting its competitiveness and practical value.
Available online , doi: 10.11999/JEIT250675
Abstract:
Objective Collaborative inference with Large Language Models (LLMs) is employed to enable mobile devices to offload multi-modal data, including images, text, video, and environmental information such as temperature and humidity, to edge servers. This offloading improves the performance of inference tasks such as human-computer question answering, logical reasoning, and decision support. Jamming attacks, however, increase transmission latency and packet loss, which reduces task completion rates and slows inference. A reinforcement learning-based collaborative inference scheme is proposed to enhance inference speed, accuracy, and task completion under jamming conditions. LLMs with different sparsity levels and quantization precisions are deployed on edge servers to meet heterogeneous inference requirements across tasks. Methods A reinforcement learning-based collaborative inference scheme is proposed to enhance inference accuracy, speed, and task completion under jamming attacks. The scheme jointly selects the edge servers, sparsity rates and quantization levels of LLMs, as well as the transmit power and channels for data offloading, based on task type, data volume, channel gains, and received jamming power. A policy risk function is formulated to quantify the probability of inference task failure given offloading latency and packet loss rate, thereby reducing the likelihood of unsafe policy exploration. Each edge server deploys LLMs with varying sparsity rates and quantization precisions, derived from layer-wise unstructured pruning and model parameter quantization, to process token vectors of multi-modal data including images, text, video, and environmental information such as temperature and humidity. This configuration is designed to meet diverse requirements for inference accuracy and speed across different tasks. The LLM inference system is implemented with mobile devices offloading images and text to edge servers for human-computer question answering and driving decision support. The edge servers employ a vision encoder and tokenizer to transform the received sensing data into token vectors, which serve as inputs to the LLMs. Pruning and parameter quantization are applied to the foundation model LLaVA-1.5-7B, generating nine LLM variants with different sparsity rates and quantization precisions to accommodate heterogeneous inference demands. Results and Discussions Experiments are conducted with three vehicles offloading images (i.e., captured traffic scenes) and texts (i.e., user prompts) using a maximum transmit power of 100 mW on 5.170～5.330 MHz frequency channels. The system is evaluated against a smart jammer that applies Q-learning to block one of the 20 MHz channels within this band. The results show consistent performance gains over benchmark schemes. Faster responses and more accurate driving advice are achieved, enabled by reduced offloading latency and lower packet loss in image transmission, which allow the construction of more complete traffic scenes. Over 20 repeated runs, inference speed is improved by 20.3%, task completion rate by 14.1%, and accuracy by 12.2%. These improvements are attributed to the safe exploration strategy, which prevents performance degradation and satisfies diverse inference requirements across tasks. Conclusions This paper proposed a reinforcement learning-based collaborative inference scheme that jointly selects the edge servers, sparsity rates and quantization levels of LLMs, as well as the transmit power and offloading channels, to counter jamming attacks. The inference system deploys nine LLM variants with different sparsity rates and quantization precisions for human-computer question answering and driving decision support, thereby meeting heterogeneous requirements for accuracy and speed. Experimental results demonstrate that the proposed scheme provides faster responses and more reliable driving advice. Specifically, it improves inference speed by 20.3%, task completion rate by 14.1%, and accuracy by 12.2%, achieved through reduced offloading latency and packet loss compared with benchmark approaches.
Available online , doi: 10.11999/JEIT250260
Abstract:
Significance The exponential growth of data volume, advances in computational power, and progress in algorithmic theory have accelerated the development of Artificial Intelligence (AI). Although AI offers unprecedented opportunities across industries, it continues to face limitations such as dependence on large datasets, poor interpretability of learning and decision-making mechanisms, limited robustness, and susceptibility to hallucinations. To overcome these challenges, integrating human cognitive decision-making capabilities and human-like cognitive models into AI systems is essential. This integration gives rise to a new form of intelligence—Human-Machine Fusion Intelligence—which combines physiological and physical characteristics. The core concept is to harness the complementary strengths of humans and machines in information processing and decision-making: humans provide intuitive judgment and contextual understanding, whereas machines are capable of high-speed computation and large-scale data analysis. By establishing a synergistic, collaborative “partnership,” Human-Machine Fusion Intelligent Decision-Making seeks to optimize decision quality through coordinated organic and probabilistic integration. This paradigm holds significant potential to improve decision reliability in mission-critical contexts, such as military operations, medical procedures, and autonomous driving, thus offering both theoretical research value and practical application relevance. Conclusions This review adopts a systematic research approach to examine Human-Machine Fusion Intelligence in decision-making across four core dimensions. First, it presents a theoretical analysis of the fundamental concepts underpinning Human-Machine Fusion Intelligence and highlights its unique advantages in complex decision-making contexts. Second, it proposes a general framework for Human-Machine Fusion Intelligent Decision-Making systems, emphasizing two key components: situational awareness and collaborative decision-making. Based on this framework, decision-making approaches are categorized into three types according to task characteristics and the nature of human-machine interaction: human-led, machine-led, and human-machine collaborative decision-making. Third, the review synthesizes recent practical advancements in representative application domains. Finally, it examines emerging trends in the development of Human-Machine Fusion Intelligent Decision-Making. Progress Unlike prior reviews that focus primarily on specific application domains, this article presents a comprehensive overview of Human-Machine Fusion Intelligence across four key dimensions: conceptual foundations, system framework, practical applications, and current challenges and future prospects. The core contributions of this review are summarized in the following four areas: First, it elucidates the advantages of Human-Machine Fusion Intelligent Decision-Making systems: (1) Improved decision-making accuracy—By combining machines’ strengths in data processing and logical reasoning with human capabilities in handling unstructured problems and ethically complex decisions, the system enables dynamic adjustment through a human-in-the-loop mechanism. (2) Enhanced interpretability of decision outcomes—The decision-making process bridges the cognitive gap between humans and machines, providing a transparent, traceable decision path and clarifying accountability boundaries. (3) Greater system robustness—By integrating machines’ risk monitoring and adaptive capabilities with human experiential judgment in complex or uncertain environments, the system establishes a closed-loop collaboration that balances technological rationality with human cognition. Second, the article highlights that Human-Machine Fusion systems cannot operate independently in safety-critical contexts due to imperfect trust mechanisms and ethical constraints. In response, it proposes a hierarchical architecture comprising two key layers: (1) Situational awareness layer, including three core processes: multimodal data perception, cross-modal information fusion, and situational analysis. (2) Collaborative decision-making layer, which distinguishes three decision-making paradigms based on task characteristics and human-machine interaction mode: (a) Human-led decision-making, suited for tasks with high uncertainty and open-ended conditions, where an enhanced intelligence model with a human-in-the-loop is adopted. (b) Machine-led decision-making, appropriate for tasks with lower uncertainty, emphasizing hybrid intelligence through cognitive model integration in automated workflows. (c) Human-machine collaborative decision-making, applicable when human and machine strengths are complementary, allowing for equal, synergistic cooperation to optimize decision efficiency. Third, the article synthesizes recent technological progress, summarizing representative applications of Human-Machine Fusion Intelligent Decision-Making in mission-critical domains such as the military, healthcare, and autonomous driving. Finally, it identifies six key directions for future development: optimization of multimodal perception, fusion of semantic and feature spaces, construction of deep collaborative feedback loops, dynamic task allocation mechanisms, enhancement of system reliability, and development of ethical guidelines. These directions aim to advance efficient collaboration and sustainable evolution of human-machine intelligence. Prospects Human-Machine Fusion Intelligent Decision-Making offers substantial research value and strong application potential for advancing emerging industries and enabling new intelligent paradigms. Although several exploratory efforts have been made, the field remains in its infancy, lacking a unified and mature theoretical or technological foundation. Key scientific and engineering challenges persist, including the optimization of multimodal perception and data fusion, bridging the semantic gap between human cognition and machine-represented feature spaces, and achieving deep integration of human and machine intelligence. Continued interdisciplinary collaboration will be essential to drive theoretical progress and technological innovation, further unlocking the potential of Human-Machine Fusion Intelligent Decision-Making.
Available online , doi: 10.11999/JEIT250663
Abstract:
Objective The rapid expansion of Artificial Intelligence (AI) computing services has heightened the demand for flexible access and efficient utilization of computing resources. Traditional Domain Name System (DNS) and IP-based scheduling mechanisms are constrained in addressing the stringent requirements of low latency and high concurrency, highlighting the need for integrated computing-network resource management. To address these challenges, this study proposes a lightweight deployment framework that enhances network adaptability and resource scheduling efficiency for AI services. Methods The AI-oriented Service IDentifier (AISID) is designed to encode service attributes into four dimensions: Object, Function, Method, and Performance. Service requests are decoupled from physical resource locations, enabling dynamic resource matching. AISID is embedded within IPv6 packets (Fig. 5 ), consisting of a 64-bit prefix for identification and a 64-bit service-specific suffix (Fig. 4 ). A lightweight incremental deployment scheme is implemented through hierarchical routing, in which stable wide-area routing is managed by ingress gateways, and fine-grained local scheduling is handled by egress gateways (Fig. 6 ). Ingress and egress gateways are incrementally deployed under the coordination of an intelligent control system to optimize resource allocation. AISID-based paths are encapsulated at ingress gateways using Segment Routing over IPv6 (SRv6), whereas egress gateways select optimal service nodes according to real-time load data using a weighted least-connections strategy (Fig. 8 ). AISID lifecycle management includes registration, query, migration, and decommissioning phases (Table 2 ), with global synchronization maintained by the control system. Resource scheduling is dynamically adjusted according to real-time network topology and node utilization metrics (Fig. 7 ). Results and Discussions Experimental results show marked improvements over traditional DNS/IP architectures. The AISID mechanism reduces service request initiation latency by 61.3% compared to DNS resolution (Fig. 9 ), as it eliminates the need for round-trip DNS queries. Under 500 concurrent requests, network bandwidth utilization variance decreases by 32.8% (Fig. 10 ), reflecting the ability of AISID-enabled scheduling to alleviate congestion hotspots. Computing resource variance improves by 12.3% (Fig. 11 ), demonstrating more balanced workload distribution across service nodes. These improvements arise from AISID’s precise semantic matching in combination with the hierarchical routing strategy, which together enhance resource allocation efficiency while maintaining compatibility with existing IPv6/DNS infrastructure (Fig. 2 ～3 ). The incremental deployment approach further reduces disruption to legacy networks, confirming the framework’s practicality and viability for real-world deployment. Conclusions This study establishes a computing-network convergence framework for AI services based on semantic-driven AISID and lightweight deployment. The key innovations include AISID’s semantic encoding, which enables dynamic resource scheduling and decoupled service access, together with incremental gateway deployment that optimizes routing without requiring major modifications to legacy networks. Experimental validation demonstrates significant improvements in latency reduction, bandwidth efficiency, and balanced resource utilization. Future research will explore AISID’s scalability across heterogeneous domains and its robustness under dynamic network conditions.
Available online , doi: 10.11999/JEIT250566
Abstract:
Objective With the widespread application of Unmanned Aerial Vehicles (UAVs) in military reconnaissance, logistics, and emergency communications, ensuring the security and reliability of UAV communication systems has become a critical challenge. Wireless channels are highly vulnerable to diverse jamming attacks. Traditional anti-jamming techniques, such as Frequency-Hopping Spread Spectrum (FHSS), are limited in dynamic spectrum environments and may be compromised by advanced machine learning algorithms. Furthermore, UAVs operate under strict constraints on onboard computational power and energy, which hinders the real-time use of complex anti-jamming algorithms. To address these challenges, this study proposes a multi-mode anti-jamming framework that integrates Intelligent Frequency Hopping (IFH), Jamming-based Backscatter Communication (JBC), and Energy Harvesting (EH) to strengthen communication resilience in complex electromagnetic environments. A Multi-mode Transfer Deep Q-Learning (MT-DQN) method is further proposed, enabling two-dimensional transfer to improve learning efficiency and adaptability under resource constraints. By leveraging transfer learning, the framework reduces computational load and accelerates decision-making, thereby allowing UAVs to counter jamming threats effectively even with limited resources. Methods The proposed framework adopts a multi-mode anti-jamming architecture that integrates IFH, JBC, and EH to establish a comprehensive defense strategy of “avoiding, utilizing, and converting” interference. The system is formulated as a Markov Decision Process (MDP) to dynamically optimize the selection of anti-jamming modes and communication channels. To address the challenges of high-dimensional state-action spaces and restricted onboard computational resources, a two-dimensional transfer reinforcement learning framework is developed. This framework comprises a cross-mode strategy-sharing network for extracting common features across different anti-jamming modes (Fig. 3 ) and a parallel network for cross-task transfer learning to adapt to variable task requirements (Fig. 4 ). The cross-mode strategy-sharing network accelerates convergence by reusing experiences, whereas the cross-task transfer learning network enables knowledge transfer under different task weightings. The reward function is designed to balance communication throughput and energy consumption. It guides the UAV to select the optimal anti-jamming strategy in real time based on spectrum sensing outcomes and task priorities. Results and Discussions The simulation results validate the effectiveness of the proposed MT-DQN. The dynamic weight allocation mechanism exhibits strong cross-task transfer capability (Fig. 6 ), as weight adjustments enable rapid convergence toward the corresponding optimal reward values. Compared with conventional Deep Reinforcement Learning (DRL) algorithms, the proposed method achieves a 64% faster convergence rate while maintaining the probability of communication interruption below 20% in dynamic jamming environments (Fig. 7 ). The framework shows robust performance in terms of throughput, convergence rate, and adaptability to variations in jamming patterns. In scenarios with comb-shaped and sweep-frequency jamming, the proposed method yields higher normalized throughput and faster convergence, exceeding baseline DQN and other transfer learning-based approaches. The results also indicate that MT-DQN improves stability and accelerates policy optimization during jamming pattern switching (Fig. 7 ), highlighting its adaptability to abrupt changes in jamming patterns through transfer learning. Conclusions This study proposes a multi-modal anti-jamming framework that integrates IFH, JBC, and EH, thereby enhancing the communication capability of UAVs. The proposed solution shifts the paradigm from traditional jamming avoidance toward active jamming exploitation, repurposing jamming signals as covert carriers to overcome the limitations of conventional frequency-hopping systems. Simulation results confirm the advantages of the proposed method in throughput performance, convergence rate, and environmental adaptability, demonstrating stable communication quality even under complex electromagnetic conditions. Although DRL approaches are inherently constrained in handling completely random jamming without intrinsic patterns, this work improves adaptability to dynamic jamming through transfer learning and cross-modal strategy sharing. These findings provide a promising approach for countering complex jamming threats in UAV networks. Future work will focus on validating the proposed algorithm in hardware implementations and enhancing the robustness of DRL methods under highly non-stationary, though not entirely unpredictable, jamming conditions such as pseudo-random or adaptive interference.
Available online , doi: 10.11999/JEIT250279
Abstract:
Objective With the rapid expansion of Internet of Things (IoT) devices, application scenarios such as smart cities and industrial intelligent manufacturing demand wider coverage and higher connection density from communication systems. Traditional terrestrial base stations have limited capacity to serve IoT devices in remote or complex environments. Unmanned Aircraft Vehicles (UAVs), owing to their flexible deployment and high mobility, can function as aerial base stations that effectively complement terrestrial networks, providing reliable and energy-efficient access for remote IoT terminals. Additionally, the expected 6G connectivity of tens of billions of devices may give rise to signaling conflicts and congestion at key nodes. To address these challenges, multi-cluster access schemes based on cluster division have been proposed. In these schemes, different clusters connect simultaneously to orthogonal subchannels, enabling UAVs to assist multiple IoT device clusters in accessing terrestrial networks concurrently. However, UAV-assisted multi-cluster communication faces pressing security and performance issues, including the susceptibility of air interface channels to attacks, the limited computational and storage capacities of IoT devices, signaling conflicts arising from massive concurrent access, and the requirement for seamless handover mechanisms due to the restricted endurance of UAVs. Therefore, the development of a secure and efficient UAV-assisted multi-cluster concurrent access and handover authentication scheme is essential. Methods This study proposes a secure authentication scheme for the UAV-assisted multi-cluster IoT device communication model, comprising four main components. First, UAV access authentication is achieved through a traditional pre-shared key mechanism, enabling mutual authentication and key agreement between the UAV and the ground network. Second, concurrent access authentication for multi-cluster IoT devices is realized using multi-layer aggregated signaling and aggregated message authentication code technologies, which effectively mitigate signaling conflicts and node congestion during massive concurrent access. Meanwhile, a Physically Unclonable Function (PUF) mechanism is incorporated to strengthen device-level security, protecting IoT devices against physical attacks while maintaining low storage and computational requirements. Finally, the UAV-assisted concurrent handover authentication integrates multi-layer aggregated signaling, aggregated message authentication code, and a pre-distribution key mechanism to enable fast and secure handovers between multi-cluster IoT devices and new UAVs, thereby ensuring the continuous security of network services. Results and Discussions The security of the proposed scheme is validated through formal analysis with the Tamarin tool, complemented by informal security analysis. The results show that the scheme satisfies mutual authentication and data security, and resists replay and man-in-the-middle attacks. The signaling overhead, as well as the computational and storage requirements of IoT devices during concurrent access and handover in multi-cluster communication, are also evaluated. The findings indicate that the scheme generates minimal signaling overhead (Fig. 3 ), thereby preventing signaling conflicts and node congestion. Moreover, the computational cost on devices remains low (Fig. 4 ), and the storage demand is minimal (Fig. 5 ), demonstrating that the scheme is well suited for resource-constrained IoT devices. Conclusions This paper proposes a UAV-assisted authentication scheme for concurrent access and handover of multi-cluster IoT devices. In this scheme, UAVs can securely and efficiently access the ground network, while multi-cluster IoT devices achieve concurrent and secure access through UAVs and perform rapid authentication and key agreement during handover to a new UAV. Security and performance analyses demonstrate that the scheme ensures multiple security properties, including mutual authentication, data security, and resistance to replay, man-in-the-middle, and physical attacks, while maintaining low computational and storage overhead on IoT devices. In addition, the scheme features low signaling overhead, effectively preventing signaling conflicts and key node congestion during large-scale concurrent access. Nevertheless, some limitations remain. Future work will explore more comprehensive and practical authentication mechanisms. Specifically, lightweight dynamic key update mechanisms tailored to UAV communication scenarios will be investigated to enhance security with minimal overhead. To address design complexity and environmental adaptability issues caused by PUF hardware dependence, more robust hardware security mechanisms will be considered to improve system stability in complex environments. Moreover, to mitigate the computational and energy burden on UAVs resulting from aggregation and forwarding tasks, approaches such as edge computing offloading will be examined to enable dynamic task allocation and load balancing, ensuring efficient and sustainable operation. Finally, a prototype system will be developed, and field experiments will be conducted to validate the feasibility and performance of the proposed solution in real-world scenarios.
Available online , doi: 10.11999/JEIT250278
Abstract:
Objective In response to the extensive demands of sixth-generation (6G) communications, new waveform designs are expected to play a critical role. Conventional Orthogonal Frequency Division Multiplexing (OFDM) relies on strict orthogonality among subcarriers; however, this orthogonality is highly vulnerable to synchronization errors, which lead to severe Inter-Carrier Interference (ICI). To address this issue, filtered multicarrier modulation techniques apply high-performance filters to each subcarrier, thereby confining spectral leakage and mitigating ICI caused by non-ideal frequency synchronization. Among these techniques, Universal Filtered Multi-Carrier (UFMC) has shown particular promise, offering enhanced spectral flexibility and reduced out-of-band emissions compared with traditional OFDM. Despite these advantages, most existing studies recommend Dolph-Chebyshev (DC) filters as UFMC prototype filters. Nevertheless, DC filters suffer from limited controllability over design parameters and insufficient robustness against interference. Recent research has sought to improve system performance by applying constrained optimization techniques in filter design, typically optimizing metrics such as Signal-to-Interference Ratio (SIR) and Signal-to-Interference-plus-Noise Ratio (SINR). Nevertheless, the Symbol Error Rate (SER) has not achieved an optimal level, indicating room for further improvement. To bridge this gap, this paper proposes a novel prototype filter design method that directly targets the average SER in interference-limited UFMC systems. This approach improves the anti-interference capability of UFMC systems and contributes to the development of robust waveform solutions for 6G communications. Methods This study first derives the SINR of the UFMC system under non-zero Carrier Frequency Offset (CFO) and formulates the SER expression under interference-limited conditions. A mathematical model is then established for prototype filter optimization, with SER defined as the objective function. Because the nonlinear coupling between SINR and the filter coefficients introduces strong non-convexity, the Successive Convex Approximation (SCA) framework is employed to locally linearize the non-convex components. Furthermore, a quadratic upper-bound technique is applied to guarantee both convexity and convergence of the approximated problem. Finally, an iterative algorithm is developed to solve the optimization model and determine the optimal prototype filter. Results and Discussions The interference suppression capability of the proposed SCA filter is comprehensively evaluated, as shown in Figs. 2 and 3 . The simulation results in Fig. 2 reveal several important findings. (1) The deviation between the theoretical SINR and Monte Carlo simulation results is less than 0.1 dB (Fig. 2 ), confirming the accuracy of the derived closed-form expressions. (2) CFO is shown to have a strong association with system interference. As the residual CFO increases from 0 to 0.05, the SINR with conventional DC filters decreases by 3.6 dB, whereas the SCA filter achieves an SINR gain of approximately 1 dB compared with the DC filter. (3) Under a CFO of 0.025, the UFMC waveform demonstrates clear superiority over the ideal OFDM system. At a Signal-to-Noise Ratio (SNR) of 18 dB, the UFMC system with the SCA filter attains an SINR of 18.4 dB, outperforming OFDM by 0.3 dB. Fig. 3 further highlights the robustness of the SCA filter in dynamic interference environments. Although the SER increases with both larger CFO and higher modulation orders, the SCA filter consistently yields the lowest SER across all interference scenarios. Under severe interference conditions (CFO = 0.05, 16QAM modulation, SNR = 17 dB), the SCA filter achieves an SER of 7.4×10–3, markedly outperforming the DC filter, which exhibits an SER of 2.9×10–2. These results demonstrate that the proposed SCA filter substantially enhances the anti-interference capability of UFMC systems. Conclusions This study first derives analytical expressions for the SINR and SER of the UFMC system under CFO. On this basis, an optimization model is established to design the prototype filter with the objective of minimizing the average SER. To address the non-convexity arising from the nonlinear coupling between SINR and filter coefficients, the SCA method is employed to reformulate the problem into a series of convex subproblems. An iterative algorithm is then proposed to obtain the optimal prototype filter. Simulation results demonstrate that, compared with conventional filters, the proposed SCA-based optimization algorithm provides flexible control over key filter parameters, achieving a narrower transition band and higher stopband attenuation under the same filter length. This improvement translates into significantly enhanced anti-interference performance under various system conditions. In summary, the main contributions of this work are: (1) Proposing a novel SCA-based optimization method for UFMC prototype filter design, which overcomes the parameter control limitations of traditional DC filters; (2) Systematically analyzing the performance advantages of the SCA filter under different modulation schemes and CFO conditions, and quantitatively demonstrating its contributions to SINR and SER improvements.
Available online , doi: 10.11999/JEIT250347
Abstract:
This paper proposes a Ku-band circularly polarized Leaky-Wave Antenna (LWA) based on a Substrate Integrated Waveguide (SIW). A parasitic slot, with the same configuration as the main radiation slot but reduced in size, is employed to address the open-stopband problem and enhance impedance matching. The radiation slot excites Circularly Polarized (CP) waves, while the parasitic slot simultaneously broadens the Axial Ratio (AR) bandwidth and suppresses the open-stopband effect. A prototype antenna is designed, fabricated, and measured. The results demonstrate that the antenna achieves a 32% 3-dB AR bandwidth from 12.6 GHz to 17.4 GHz, with CP beam scanning from –49° to +14°. The simulated and measured results are in good agreement. In addition, the realized gain remains stable across the operating band. Compared with existing works, the proposed design achieves the widest scanning range. Objective Compared with traditional phased array antennas, frequency-scanning antennas have extensive applications in both military and civilian fields owing to their advantages of low profile, low cost, and lightweight design. CP waves offer superior anti-interference performance compared with linearly polarized waves. As a representative frequency-scanning antenna, the LWA has attracted sustained global research interest. This study focuses on the investigation of a Ku-band Circularly Polarized Leaky-Wave Antenna (CP-LWA), with emphasis on wide-bandwidth and wide-scanning techniques, as well as methods for achieving circular polarization. The aim is to provide potential design concepts for next-generation mobile communication and radar system antennas. Methods The fan-shaped slot is modified based on previous work, and an additional size-reduced parasitic slot of the same shape as the main slot is introduced. The parasitic slots cancel the reflected waves generated by the main radiating slot, thereby suppressing the Open-Stop-Band (OSB) effect, and they also enlarge the effective radiating aperture, which improves radiation efficiency and impedance matching. By exploiting the metallic boundary of the conductors, the parasitic slots enhance CP performance and broaden the AR bandwidth. To validate the proposed design, an antenna consisting of 12 main slots and 11 parasitic slots is designed, simulated, and measured. Results and Discussions A prototype is designed, fabricated, and measured in a microwave anechoic chamber to validate the proposed antenna. Both simulated and measured S11 values remain below –10 dB across the entire Ku-band. The measured S11 is slightly higher in the low-frequency range (12～13 GHz) and slightly lower in the high-frequency range (16～18 GHz), while maintaining an overall consistent trend with the simulations, except for a frequency shift of approximately 0.2 GHz toward lower frequencies. For the AR bandwidth, the simulated and measured 3-dB AR bandwidths are 32.7% (12.8～17.8 GHz) and 32.0% (12.6～17.4 GHz), respectively. The realized gains are on average 0.6 dB lower than the simulated values across the AR bandwidth, likely due to measurement system errors and fabrication tolerances. The simulated and measured peak gains reach 14.26 dB and 13.65 dB, respectively, with maximum gain variations of 2.91 dB and 2.85 dB. The measured AR and gain results therefore show strong agreement with the simulations. The measured sidelobe level increases on average by approximately 0.65 dB. The simulated CP scanning range extends from –47° to +17°, while the measured range narrows slightly to –49° to +14°. The frequency shift of the LWA is analyzed, and based on the simulated effect of variations in εr on the scanning patterns, the shift toward lower frequencies is attributed to the actual dielectric constant of the substrate being smaller than the nominal value of 2.2 specified by the manufacturer. Conclusions This paper proposes a Ku-band CP-LWA based on a SIW. The antenna employs etched slots consisting of fan-shaped radiation slots and size-reduced parasitic slots. The radiation slots excite circular polarization due to their inherent geometric properties, while the parasitic slots suppress the CP effect and broaden the CP bandwidth. Measurements confirm that the proposed LWA achieves a wide 3-dB AR bandwidth of 12.6～17.4 GHz (32%) with a CP beam scanning range from –49° to +14°. Meanwhile, the antenna demonstrates stable gain performance across the entire AR bandwidth.
Available online , doi: 10.11999/JEIT250436
Abstract:
Objective Holographic Multiple-Input Multiple-Output (HMIMO), based on continuous-aperture antennas and programmable metasurfaces, is regarded as a cornerstone of 6G wireless communication. Its potential to overcome the limitations of conventional massive MIMO is critically dependent on accurate channel modeling and estimation. Three major challenges remain: (1) oversimplified electromagnetic propagation models, such as far-field approximations, cause severe mismatches in near-field scenarios; (2) statistical models fail to characterize the coupling between channel coefficients, user positions, and random orientations; and (3) the high dimensionality of parameter spaces results in prohibitive computational complexity. To address these challenges, a hybrid parametric-Bayesian framework is proposed in which neural networks, factor graphs, and convex optimization are integrated. Precise channel estimation, user position sensing, and angle decoupling in near-field HMIMO systems are thereby achieved. The methodology provides a pathway toward high-capacity 6G applications, including Integrated Sensing And Communication (ISAC). Methods A hybrid channel estimation method is proposed to decouple the “channel-coordinate-angle” parameters and to enable joint estimation of channel coefficients, coordinates, and angles under random user orientations. A neural network is first employed to capture the nonlinear relationship between holographic channel characteristics and the relative coordinates of the base station and user. The trained network is then embedded into a factor graph, where global optimization is performed. The neural network is dynamically approximated through Taylor expansion, allowing bidirectional message propagation and iterative refinement of parameter estimates. To address random user orientations, Euler angle rotation theory is introduced. Finally, convex optimization is applied to estimate the rotation mapping matrix, resulting in the decoupling of coordinate and angle parameters and accurate channel estimation. Results and Discussions The simulations evaluate the performance of different algorithms under varying key parameters, including Signal-to-Noise Ratio (SNR), pilot length L, and base station antenna number M. Two performance metrics are considered: Normalized Mean Square Error (NMSE) of channel estimation and user positioning accuracy, with the Cramér–Rao Lower Bound (CRLB) serving as the theoretical benchmark. At an SNR of 10 dB, the proposed method achieves a channel NMSE below –40 dB, outperforming Least Squares (LS) estimation and approximate model-based approaches. Under high SNR conditions, the NMSE converges toward the CRLB, confirming near-optimal performance (Fig. 5a ). The proposed channel model demonstrates superior performance over “approximate methods” due to its enhanced characterization of real-world channels. Moreover, the positioning error gap between the proposed method and the “parallel bound” narrows to nearly 3 dB at high SNR, confirming the accuracy of angle estimation and the effectiveness of parameter decoupling (Fig. 5b ). Moreover, the proposed method maintains performance close to the theoretical bounds when system parameters, such as user antenna number N, base station antenna number M, and pilot length L, are varied, demonstrating strong robustness (Figs. 6 ～8 ). These results also show that the Euler angle rotation-based estimation effectively compensates for coordinate offsets induced by random user orientations. Conclusions This study proposes a framework for HMIMO channel estimation by integrating neural networks, factor graphs, and convex optimization. The main contributions are threefold. First, Euler angles and coordinate mapping are incorporated into the parameterized channel model through factorization and factor graphs, enabling channel modeling under arbitrary user antenna orientations. Second, neural networks and convex optimization are embedded as factor nodes in the graph, allowing nonlinear function approximation and global optimization. Third, bidirectional message passing between neural network and convex optimization nodes is realized through Taylor expansion, thereby achieving joint decoupling and estimation of channel parameters, coordinates, and angles. Simulation results confirm that the proposed framework achieves higher accuracy—exceeding benchmarks by more than 3 dB, and demonstrates strong robustness across a range of scenarios. Future work will extend the method to multi-user environments, incorporate polarization diversity, and address hardware impairments such as phase noise, with the aim of supporting practical deployment in 6G systems.
Available online , doi: 10.11999/JEIT250404
Abstract:
Objective ElectroCardioGram (ECG) signals are key indicators of human health. However, their complex composition and diverse features make visual recognition prone to errors. This study proposes a classification algorithm for ECG pathological signals based on data generation. A Diffusion Generative Network (DGN), also known as a diffusion model, progressively adds noise to real ECG signals until they approach a noise distribution, thereby facilitating model processing. To improve generation speed and reduce memory usage, a Knowledge Distillation-Diffusion Generative Network (KD-DGN) is proposed, which demonstrates superior memory efficiency and generation performance compared with the traditional DGN. This work compares the memory usage, generation efficiency, and classification accuracy of DGN and KD-DGN, and analyzes the characteristics of the generated data after lightweight processing. In addition, the classification effects of the original MIT-BIH dataset and an extended dataset (MIT-BIH-PLUS) are evaluated. Experimental results show that convolutional networks extract richer feature information from the extended dataset generated by DGN, leading to improved recognition performance of ECG pathological signals. Methods The generative network-based ECG signal generation algorithm is designed to enhance the performance of convolutional networks in ECG signal classification. The process begins with a Gaussian noise-based image perturbation algorithm, which obscures the original ECG data by introducing controlled randomness. This step simulates real-world variability, enabling the model to learn more robust representations. A diffusion generative algorithm is then applied to reconstruct and reproduce the data, generating synthetic ECG signals that preserve the essential characteristics of the original categories despite the added noise. This reconstruction ensures that the underlying features of ECG signals are retained, allowing the convolutional network to extract more informative features during classification. To improve efficiency, the approach incorporates knowledge distillation. A teacher-student framework is adopted in which a lightweight student model is trained from the original, more complex teacher ECG data generation model. This strategy reduces computational requirements and accelerates the data generation process, improving suitability for practical applications. Finally, two comparative experiments are designed to validate the effectiveness and accuracy of the proposed method. These experiments evaluate classification performance against existing approaches and provide quantitative evidence of its advantages in ECG signal processing. Results and Discussions The data generation algorithm yields ECG signals with a Signal-to-Noise Ratio (SNR) comparable to that of the original data, while presenting more discernible signal features. The student model constructed through knowledge distillation produces ECG samples with the same SNR as those generated by the teacher model, but with substantially reduced complexity. Specifically, the student model achieves a 50% reduction in size, 37.5% lower memory usage, and a 57% shorter runtime compared with the teacher model (Fig. 6 ). When the convolutional network is trained with data generated by the KD-DGN, its classification performance improves across all metrics compared with a convolutional network trained without KD-DGN. Precision reaches 95.7%, and the misidentification rate is reduced to approximately 3% (Fig. 9 ). Conclusions The DGN provides an effective data generation strategy for addressing the scarcity of ECG datasets. By supplying additional synthetic data, it enables convolutional networks to extract more diverse class-specific features, thereby improving recognition performance and reducing misidentification rates. Optimizing DGN with knowledge distillation further enhances efficiency, while maintaining SNR equivalence with the original DGN. This optimization reduces computational cost, conserves machine resources, and supports simultaneous task execution. Moreover, it enables the generation of new data without LOSS, allowing convolutional networks to learn from larger datasets at lower cost. Overall, the proposed approach markedly improves the classification performance of convolutional networks on ECG signals. Future work will focus on further algorithmic optimization for real-world applications.
Available online , doi: 10.11999/JEIT250191
Abstract:
Objective Signal sorting is a crucial technology in electronic reconnaissance that enables the deinterleaving of mixed pulse sequences emitted by multiple radar radiation sources, thereby supporting military decision-making. With the rapid advancement of electronic technology, multi-station cooperative signal sorting has received increasing attention. However, existing multi-station signal sorting methods depend heavily on manually selected parameters, which limits adaptability. Moreover, in complex environments with pulse loss and noise interference, conventional methods struggle to process unpaired pulses effectively, reducing the accuracy and stability of sorting. To address these challenges, this study applies the Dirichlet Process Mixture Model (DPMM) to multi-station cooperative signal sorting. The proposed approach enables adaptive sorting even when the number of radiation sources is unknown or measurement errors exist, thereby improving flexibility and adaptability. Furthermore, it can effectively classify unpaired pulses caused by pulse loss or noise, enhancing the robustness and reliability of sorting. This research provides a novel strategy for signal sorting in complex electromagnetic environments and holds promising application value in radar signal processing. Methods In multi-station cooperative signal sorting, the spatial distribution of multiple receiving stations detecting the same radar signal makes efficient and accurate signal pairing and classification a core challenge. To address this issue, a multi-station cooperative signal sorting method based on the DPMM is proposed. The process comprises three stages: pulse pairing, time-difference clustering and sorting, and mismatched pulse classification. In the pulse pairing stage, identical pulses originating from the same radiation source are identified from the sequences intercepted by each receiving station. To ensure accurate pairing, a dual-constraint strategy is adopted, combining a time-difference window with multi-parameter matching. Successfully paired pulses are then constructed into a time-difference vector set, which provides the data foundation for the subsequent clustering and sorting stage. In the time-difference clustering and sorting stage, DPMM is employed to cluster the time-difference vector set. DPMM adaptively determines the number of clusters to model the data structure, enabling the system to infer the optimal cluster count. Gibbs sampling is used to optimize model parameters, further enhancing clustering robustness. Based on the clustering results, radar pulse sets are constructed, achieving signal sorting across multiple radiation sources. In the mismatched pulse classification stage, unpaired pulses caused by noise interference or pulse loss during transmission are further processed. DPMM is applied to fit radar pulse parameter vectors, including pulse width, radio frequency, and bandwidth. The affiliation degree of each mismatched pulse relative to the radar pulse sets is then calculated. Pulses with affiliation degrees exceeding a predefined threshold are merged into the corresponding pulse set, whereas those below the threshold are classified as anomalous pulses, likely due to interference or noise, and are discarded. This method enhances the adaptability and robustness of multi-station cooperative signal sorting and provides an effective solution for complex electromagnetic environments. Results and Discussions In the experimental validation, radar pulse data are generated through simulation to evaluate the effectiveness of the proposed method. Compared with traditional multi-station cooperative signal sorting approaches, the method achieves high-precision sorting without requiring prior knowledge of the number of radiation sources or parameter measurement errors, thereby demonstrating strong adaptability and practicality. To comprehensively assess performance in complex environments, simulations are conducted to analyze sorting capability under varying measurement errors, pulse loss rates, and interference rates. The final sorting results are summarized in (Table. 3 ). The results indicate that even in the presence of noise interference and data loss, most radar pulses are accurately identified, with only a small fraction misclassified as interference signals. The final sorting accuracy reaches 98.8%, confirming the robustness and stability of the method against pulse loss, noise, and other uncertainties. To further validate its superiority, the method is compared with other algorithms under different conditions. Sorting accuracy under different Time of Arrival (TOA) measurement errors (Fig. 6 ) shows that stable performance is maintained even under severe noise interference, reflecting strong noise resistance. Further analyses of sorting accuracy under different pulse loss rates and interference rates (Figs. 7 and 8 ) demonstrate that higher efficiency and stability are achieved in handling unpaired pulses, and pulses that fail to be paired are more accurately classified. The sorting accuracy of different algorithms in various scenarios (Fig. 9 ) further confirms that the method performs more consistently in complex environments, indicating higher adaptability. Overall, the method adapts well to diverse application scenarios and provides efficient, stable, and reliable signal sorting for multi-station cooperative electronic reconnaissance tasks. Conclusions This study proposes a multi-station cooperative signal sorting method based on the DPMM to address the limitations of traditional approaches, which rely heavily on prior information and perform poorly in processing unpaired pulses. By applying DPMM for adaptive clustering of time-difference information, the proposed method avoids sorting errors caused by improper manual parameter settings and effectively classifies unpaired pulses based on radar pulse parameter characteristics. Simulation results show that this method not only improves the accuracy and stability of multi-station cooperative signal sorting but also maintains high sorting performance even when the number of radiation sources is unknown or measurement errors are present, highlighting its engineering application value. Future research may extend this approach to dynamic electromagnetic environments and adaptive real-time processing to meet the demands of more complex electronic reconnaissance tasks.
Available online , doi: 10.11999/JEIT250440
Abstract:
Objective ARIA is established as the Korean national Standard block cipher (KS X 1213) in 2003 to meet the demand for robust cryptographic solutions across government, industrial, and commercial sectors in South Korea. Designed by a consortium of Korean cryptographers, the algorithm adopts a hardware-efficient architecture that supports 128-, 192-, and 256-bit key lengths, providing a balance between computational performance and cryptographic security. This design allows ARIA to serve as a competitive alternative to the Advanced Encryption Standard (AES), with comparable encryption and decryption speeds suitable for deployment in resource-constrained environments, including embedded systems and high-performance applications. The security of ARIA is ensured by its Substitution–Permutation Network (SPN) structure, which incorporates two distinct substitution layers and a diffusion layer to resist classical cryptanalytic methods such as differential, linear, and related-key attacks. This robustness has promoted its adoption in secure communication protocols and financial systems within South Korea and internationally. With the emergence of quantum computing, challenges to classical ciphers arise. Quantum algorithms such as Grover’s algorithm reduce the effective key strength of symmetric ciphers, necessitating reassessment of their post-quantum security. In this study, ARIA’s quantum circuit implementation is optimized through tower-field decomposition and in-place circuit optimization, enabling a comprehensive evaluation of its resilience against quantum adversaries. Methods The quantum resistance of ARIA is evaluated by estimating the resources required for exhaustive key search attacks under Grover’s algorithm. Grover’s quantum search algorithm achieves quadratic speedup, effectively reducing the security strength of a 128-bit key to the classical equivalent of 64 bits. To ensure accurate assessment, the quantum circuits for ARIA’s encryption and decryption processes are optimized within Grover’s framework, thereby reducing the required quantum resources. The core technique employed is tower-field decomposition, which transforms high-order finite field operations into equivalent lower-order operations, yielding compact computational representations. Specifically, the S-box and linear layer circuits are optimized using automated search tools to identify efficient combinations of low-order field operations. The resulting quantum circuits are then applied to estimate Grover-attack resource requirements, and the results are compared against the National Institute of Standards and Technology (NIST) post-quantum security standards. Results and Discussions Optimized quantum circuits for all four ARIA S-boxes are constructed using tower-field decomposition and automated circuit search tools (Fig. 7 , Table 2 ). By integrating these with the linear layer, a complete quantum encryption circuit is implemented, and Grover-attack resource requirements are re-evaluated (Tables 5 and 6 ). Detailed implementation data are provided in the Clifford+T gate set. The experimental results show that ARIA-192 does not meet the NIST Level 3 post-quantum security standard, indicating vulnerabilities to quantum adversaries. In contrast, ARIA-128 and ARIA-256 comply with Level 1 and Level 3 requirements, respectively. Further optimization is theoretically feasible through methods such as pseudo-key techniques. Future research may focus on developing automated circuit search tools to extend this framework, enabling systematic post-quantum security evaluations of ARIA and comparable symmetric ciphers (e.g., AES, SM4) within a generalized assessment model. Conclusions This study investigates the quantum resistance of classical cryptographic algorithms in the context of quantum computing, with a particular focus on the Korean block cipher ARIA. By leveraging the distinct algebraic structures of ARIA’s four S-boxes, tower-field decomposition is applied to design optimized quantum circuits for all S-boxes. Additionally, the circuit depth of the ARIA linear layer is optimized through an in-place quantum circuit implementation, resulting in a more efficient realization of the ARIA algorithm in the quantum setting. A complete quantum encryption circuit is constructed by integrating these optimization components, and the security of the ARIA family of algorithms is evaluated against quantum adversaries using Grover’s key search attack model. The results demonstrate improved implementation efficiency under the newly designed quantum scheme. However, ARIA-192 exhibits resistance below the NIST Level 3 quantum security threshold, indicating a potential vulnerability to quantum attacks.
Available online , doi: 10.11999/JEIT250359
Abstract:
Objective The proliferation of Internet of Things (IoT) devices has intensified the need for robust, hardware-level security. Among hardware-based security primitives, Physical Unclonable Functions (PUFs) serve a critical role in lightweight authentication and dynamic key generation by leveraging inherent process variations to produce unique, unclonable responses. Achieving reliable PUF performance under environmental fluctuations—such as temperature and supply voltage variation, requires balancing sensitivity to process variations with environmental robustness. Conventional approaches, including circuit-level stabilization and architecture-level error correction, can improve reliability but often increase area, power, and test complexity. To overcome these drawbacks, recent work has explored voltage or bias perturbation for unstable response correction. However, entropy degradation during mode transitions in dual-mode PUFs remains a major concern, compromising both reliability and energy efficiency. This study proposes a bit-configurable bistable electric bridge-divider PUF that addresses these challenges by maintaining entropy independence between operational modes, reducing error correlation, and limiting repair and masking overhead. The proposed solution improves randomness, reliability, and energy efficiency, making it suitable for secure, cost-effective authentication in IoT edge devices operating under dynamic conditions. Methods Hardware overhead and testing complexity associated with conventional PUF stabilization techniques are reduced by introducing a bit-configurable bistable electric bridge-divider PUF architecture. Entropy generation is enhanced by amplifying process-induced variations through electric bridge imbalance and the exponential behavior of subthreshold current. A reconfigurable bit-cell is employed to enable seamless switching between electric bridge mode and voltage divider mode without additional layout cost; dual-mode operation is thus supported while preserving area efficiency. A voltage-skew-based self-detection and repair mechanism is integrated to dynamically identify and mitigate unstable responses, thereby improving reliability under varying environmental conditions. The PUF circuit is fully custom-designed and fabricated in the TSMC 28 nm CMOS process. Post-layout simulations confirm the robustness of the architecture, demonstrating effective self-repair capabilities and consistent performance under temperature and voltage fluctuations. Results and Discussions The proposed design is fabricated using the TSMC 28 nm CMOS process. The total layout area measures 3 283.3 μm2, and each PUF cell occupies 0.7888 μm2 (Fig. 11 ). Simulation waveforms of the self-detection, repair, and masking operations are presented in (Fig. 12 ). Inter-chip Hamming distance histograms and fitted curves for both electric bridge mode and voltage divider mode are shown in (Fig. 13a , Fig. 14a ). Autocorrelation results of the 40,960-bit output are illustrated in (Fig. 13b , Fig. 14b ). The randomness of the responses is evaluated using the NIST test suite provided by the U.S. National Institute of Standards and Technology, with the results summarized in (Table 1 ). The native Bit Error Rate (BER), measured before repair or masking, is analyzed under various temperature and supply voltage conditions (Fig. 15 ). By dynamically adjusting the voltage skew, precise control of the error correction rate is achieved, leading to a substantial reduction in BER across different environments (Fig. 16 ). A performance comparison with previously reported designs is provided in (Table 2 ). After applying the entropy source repair and masking mechanism, the BER converges to below 1.62 × 10–9, approaching the ideal “zero” BER. Conclusions A bit-configurable PUF architecture is proposed to address environmental variability and hardware constraints in IoT edge devices. A reconfigurable bit-cell is employed to support dynamic switching between electric bridge mode and voltage divider mode without incurring additional layout cost. Process-induced variations are amplified through bridge imbalance and the exponential behavior of subthreshold current, which enhances the randomness and uniqueness of the PUF responses. A voltage-skew-based self-detection and repair mechanism is integrated to identify and correct unstable responses, effectively reducing the BER under varying environmental conditions. The proposed design, fabricated using the TSMC 28 nm CMOS process, demonstrates high entropy, robustness, and low overhead in terms of area and power consumption. These characteristics make it suitable for secure and lightweight authentication and key generation in resource-constrained IoT systems.
Available online , doi: 10.11999/JEIT250361
Abstract:
Objective Modern processors rely heavily on branch prediction to improve pipeline efficiency; however, the transient execution windows created by speculative execution expose critical security vulnerabilities. While prior research has primarily examined conditional branch instructions, this study identifies a previously overlooked attack surface: loop instructions (LOOP, LOOPZ, LOOPNZ) and JRCXZ in x86 architectures, which use the RCX register to determine branch outcomes. These instructions produce significantly longer transient windows than JCC instructions, posing heightened threats to hardware-level isolation. This work demonstrates the exploitability of these instructions, quantifies their transient execution behavior, and validates practical attack scenarios. Methods This study employs a systematic methodology to investigate the speculative behavior of loop instructions and assess their exploitability. First, the microarchitectural behavior of LOOP, LOOPZ, LOOPNZ, and JRCXZ instructions is reverse-engineered using Performance Monitoring Counters (PMCs), with a focus on their dependency on RCX register values and interaction with the branch prediction unit. Speculative durations of loop and JCC instructions are compared using cycle-accurate profiling via the RDPMC instruction, which accesses fixed-function PMCs to record clock cycles. Based on these observations, exploit primitives are constructed by manipulating RCX values to induce speculative execution paths. The feasibility of these primitives is evaluated through four real-world attack scenarios on Intel CPUs: (1) Cross-user/kernel data leakage through speculative memory access following mispredicted loop exits. (2) Covert channel creation between Simultaneous MultiThreading (SMT) threads by measuring timing differences between correctly and incorrectly predicted branches during speculative execution. (3) SGX enclave compromise via speculative access to secrets gated by RCX-controlled branching. (4) Kernel Address Space Layout Randomization (KASLR) bypass using page fault timing during transient execution of loop-based probes. Each scenario is tested on real hardware under controlled conditions to assess reliability, reproducibility, and attack robustness. Results and Discussions The proposed transient execution attack targeting loop instructions (LOOP, LOOPZ, LOOPNZ) and JRCXZ offers notable advantages over traditional Spectre exploits. These RCX-dependent instructions exhibit transient execution windows that are, on average, 40% longer than those of conventional JCC branches (Table 1 ). The extended speculative duration significantly improves attack reliability: in cross-user/kernel boundary experiments, the proposed method achieves an average data leakage accuracy of 90%, compared to only 10% for JCC-based techniques under identical conditions. The attack also demonstrates high efficacy in bypassing hardware isolation mechanisms. In Intel SMT environments, a covert channel is established with 97.5% accuracy and a throughput of 256.9 kbit/s (Table 4 ), exploiting timing discrepancies between correctly and incorrectly predicted branches during speculative execution. In trusted execution environments, the attack achieves 98% accuracy in extracting secret values from Intel SGX enclaves, highlighting the susceptibility of RCX-controlled speculation to enclave compromise. Additionally, KASLR is completely defeated by exploiting speculative page fault timing during loop instruction execution. Kernel base addresses are recovered deterministically in all test cases (Fig. 4 ), demonstrating the critical security implications of this attack vector. Conclusions This study identifies a critical vulnerability in modern speculative execution mechanisms by demonstrating that loop instructions (LOOP, LOOPZ, LOOPNZ) and JRCXZ—which rely on the RCX register for branch decisions, serve as novel vectors for transient execution attacks. The key contributions are threefold: (1) These instructions generate speculative execution windows that are, on average, 40% longer than those of JCC instructions. (2) Practical exploits are demonstrated across key hardware isolation boundaries—including user/kernel space, SMT, and Intel SGX enclaves, with success rates exceeding 90% in targeted scenarios. (3) The findings expose critical limitations in current Spectre defenses, indicating that existing mitigations are insufficient to address RCX-dependent speculative paths, thereby motivating the need for specialized countermeasures.
Available online , doi: 10.11999/JEIT250212
Abstract:
Objective Memristors are considered promising devices for the construction of artificial synapses because their unique nonlinear and non-volatile properties effectively mimic the functions and mechanisms of biological synapses. These features have made memristors a research focus in brain-inspired science. Memristive neural networks, composed of memristive neurons or memristive synapses, constitute a class of biomimetic artificial neural networks that exhibit dynamic behaviors more closely aligned with those of biological neural systems and provide more plausible biological interpretations. Since the concept of the memristive neural network was proposed, extensive pioneering research has been conducted, revealing several critical issues that require further exploration. Although current memristive neural networks can generate complex dynamic behaviors such as chaos and multistability, these effects are often achieved at the cost of increased network complexity or the requirement for specialized memristive characteristics. Therefore, the systematic exploration of simple memristive neural networks that can produce diverse dynamic behaviors, the proposal of practical design strategies, and the development of efficient, precise control schemes remain of considerable research value. Methods This paper proposes a chaoticization method for an Extremely Simple Cyclic Memristive Convolutional Neural Network (ESCMCNN) that contains only unidirectional synaptic connections based on memristors. Using a three-node neural network as an example, a class of memristive cyclic neural networks with simple structures and rich dynamic behaviors is constructed. Numerical analysis tools, including bifurcation diagrams, basins of attraction, phase plane diagrams, and Lyapunov exponents, are employed to investigate the networks’ diverse bifurcation processes, multiple types of multistability, and multi-variable signal amplitude control. Electronic circuit experiments are used to validate the feasibility of the proposed networks. Finally, a novel multi-power reaching law is developed to achieve chaotic synchronization within fixed time. Results and Discussions For a three-node cyclic neural network initially in a periodic state, two network chaotification methods—full-synaptic memristivation and multi-node extension—are proposed using magnetically controlled memristors (Fig. 1 ). Phase plane diagrams illustrate the chaotic attractors generated by these networks (Fig. 2 ), confirming the feasibility of the proposed methods. Using network (B) as an example, numerical analysis tools are utilized to study its diverse dynamic evolution processes (Fig. 5 , Fig. 6 , Fig. 7 ), various forms of multistability (Fig. 8 , Fig. 9 ), and multi-variable amplitude control (Fig. 10 ). The physical realization of network (B) is further demonstrated through circuit experiments (Fig. 11 , Fig. 12 ). Additionally, the effectiveness of the fixed-time synchronization control strategy for network (B) is verified through numerical simulations (Fig. 13 , Fig. 14 ). Conclusions This paper proposes a construction method for the ESCMCNN capable of generating rich dynamic behaviors. A series of ESCMCNNs is successfully designed based on a three-node neural network in a periodic state. The dynamic evolution of the ESCMCNN as a function of memristive parameters is investigated using numerical tools, including single- and dual-parameter bifurcation diagrams and Lyapunov exponents. Under different initial conditions, the ESCMCNN exhibits various forms of multistability, including the coexistence of point attractors with periodic attractors, and point attractors with chaotic attractors. The study further demonstrates that the oscillation amplitudes of multiple variables in the ESCMCNN are strongly dependent on the memristive coupling strength. The reliability of these numerical results is confirmed through electronic circuit experiments. In addition, a novel multi-power reaching law is proposed to achieve fixed-time synchronization of the network, and its feasibility and effectiveness are validated through simulation tests.
Available online , doi: 10.11999/JEIT250471
Abstract:
Objective With the rising demand for secure computing, cache-based side-channel attacks have become a critical threat to modern processors. Conventional data cache designs do not account for information leakage caused by malicious memory access patterns, enabling adversaries to infer sensitive data from subtle variations in cache access latency. Existing countermeasures, such as cache mapping randomization and cache flushing, provide partial protection but incur considerable hardware overhead and performance degradation, particularly in resource-constrained private caches such as L1 and L2. To address this limitation, this study focuses on L1 data caches and proposes a fast flushing mechanism based on Time-To-Live (TTL) control. The method mitigates side-channel leakage while minimizing additional hardware complexity and performance cost. Methods This study proposes a fast cache flushing method that introduces a lightweight 3-bit TTL field into each cache line, together with a global time register (Time), to enable efficient cache invalidation. When a flush instruction is issued, the Time register is incremented, and all cache lines are checked against their TTL values. Only lines that remain valid and contain modified data are invalidated and written back, thereby reducing flushing overhead. To ensure robustness and correctness, several auxiliary strategies are incorporated, including mechanisms to handle TTL wraparound, preserve data consistency, and strengthen resistance against advanced side-channel attacks. The proposed mechanism is realized through custom instruction set extensions on a RISC-V processor platform. Results and Discussions The proposed cache flushing mechanism exhibits significant performance benefits in representative application scenarios. Experimental evaluation shows that it reduces average flushing latency by approximately 70% relative to conventional flushing techniques. In side-channel security tests based on the Prime+Probe attack model, an adversary probing 1024 cache lines after the victim executes a flush operation is unable to recover valid sensitive information patterns, thereby confirming the security effectiveness of the proposed architecture. Regarding hardware overhead, the design introduces only about 8% additional logic and approximately 0.01% extra storage cost for TTL fields compared with conventional cache structures. Conclusions This paper presents a fast cache flushing mechanism to defend against cache-based side-channel attacks. The proposed method achieves a balanced trade-off between security and performance. Experimental results show that it substantially reduces cache flushing latency while effectively mitigating typical side-channel threats. The design is particularly suited for deployment in resource-constrained private caches such as L1 and L2. Hardware implementation further confirms the lightweight nature and engineering feasibility of the approach, indicating strong potential for practical application.
Available online , doi: 10.11999/JEIT250627
Abstract:
Objective To address the challenges of complex multiply–accumulate operations and high energy consumption in hardware implementations of Convolutional Neural Networks (CNNs), this study proposes a Processing-In-Memory (PIM) AdderNet acceleration architecture based on Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), with innovations at the circuit level. Specifically, a novel in-situ absolute difference computation circuit is designed to support L1-norm operations, replacing traditional multipliers and simplifying the data path and computational logic. By leveraging magnetic resistance state mapping, a reconfigurable full-adder unit is developed that enables single-cycle carry-chain updates and multi-mode logic switching, thereby enhancing parallel computing efficiency and energy–performance ratio. Through array-level integration and coordinated control with heterogeneous peripheral circuits, this work establishes a scalable and energy-efficient PIM-based convolutional acceleration system, providing a practical and viable paradigm for deploying deep learning hardware in resource-constrained environments. Methods To achieve energy-efficient acceleration of AdderNet in resource-constrained environments, this study proposes a circuit-level Computing-In-Memory (CIM) architecture based on STT-MRAM. The L1 norm is embedded into the memory array to enable in-situ absolute difference computation, thereby replacing conventional multiply–accumulate operations and simplifying datapath complexity. To reduce redundant operations caused by frequent zero-value interactions in AdderNet, a sparsity-aware computation strategy is implemented, which bypasses invalid operations and lowers dynamic power consumption. A reconfigurable full-adder unit is further designed using magnetoresistive state mapping, supporting single-cycle carry-chain propagation and logic mode switching. These units are integrated into a scalable parallel array structure that performs L1-norm operations efficiently. The architecture is complemented by optimized dataflow control and heterogeneous peripheral circuits, forming a complete low-power AdderNet accelerator. Simulation and hardware-level validations confirm the accuracy, throughput, and energy efficiency of the proposed system under realistic workloads. Results and Discussions Simulation results confirm the effectiveness and efficiency of the proposed MRAM-based AdderNet hardware accelerator under realistic inference workloads. The fabricated full-adder unit supports in-memory computation with dual-mode configurability for both sum and carry operations (Fig. 2 , Fig. 3 ). The proposed 1-bit full adder produces correct logical outputs in both modes, with timing waveforms validating reliable switching behavior under a 40 nm CMOS process (Fig. 7 , Fig. 8 ). The parallel array structure, which integrates multiple MRAM-based full-adder units, enables efficient L1-norm-based convolution through element-wise absolute difference (Fig. 4 ) and maps standard convolution kernels into a format compatible with the proposed architecture (Fig. 5b ). Device-level Monte Carlo simulations reveal tightly distributed resistance states, with coefficients of variation of low-resistance and high-resistance states of approximately 1.1% (CVLRS) and 1.2% (CVHRS), respectively, and a resistance window of ～5349 Ω, ensuring accurate bit-level distinction (Fig. 6 ). The MRAM device also exhibits robust noise margins (NM ≈ 50.5), confirming its suitability for logic-in-memory operations. On the CIFAR-10 dataset, the accelerator achieves a classification accuracy of 90.66%, with only a 1.18% reduction compared with the floating-point software baseline (Fig. 9 , Fig. 10 ). The final design achieves a peak throughput of 32.31 GOPS and a peak energy efficiency of 494.56 GOPS/W at 133 MHz, exceeding several state-of-the-art designs (Table 2 ). Conclusions To address the high computational complexity and energy consumption of traditional convolutional multiply–accumulate operations, this study proposes an MRAM-based AdderNet hardware accelerator that incorporates L1-norm computation and sparsity optimization strategies. At the circuit level, an in-situ absolute difference computation method based on STT-MRAM is introduced, together with a magnetic resistance state-mapped full-adder circuit that enables fast and configurable carry and sum computations. Building on these units, a scalable parallel full-adder array is constructed to replace multiplications with lightweight additions, and the complete accelerator is implemented with integrated peripheral circuits. Simulation results validate the proposed design. On the same benchmark dataset, the accelerator achieves an accuracy of 90.66% through circuit–algorithm co-optimization, with accuracy degradation limited to 1.18% compared with the software reference model. Although the training process shows periodic local oscillations, the overall convergence trend follows an exponential decay pattern. The architecture ultimately achieves a peak throughput of 32.31 GOPS and a peak energy efficiency of 494.56 GOPS/W at 133 MHz, exceeding conventional approaches in both performance and energy efficiency.
Available online , doi: 10.11999/JEIT250509
Abstract:
Objective Deep Neural Network (DNN)-based image compression has gained increasing importance in real-time applications such as intelligent driving, where an efficient balance between compression ratio and encoding speed is essential. This study proposes a hardware implementation of entropy coding, realized on a Field-Programmable Gate Array (FPGA) platform based on Range Asymmetric Numeral Systems (RANS) arithmetic coding. The design seeks to achieve an optimal trade-off between compression efficiency and hardware resource utilization, while maximizing data throughput to meet the requirements of real-time environments. The main objectives are to enhance image encoding throughput, reduce hardware resource consumption, and sustain high data throughput with only minor losses in compression ratio. The proposed hardware architecture demonstrates strong scalability and practical deployment potential, offering significant value for DNN-based image compression in high-performance systems. Methods To enable practical FPGA deployment of RANS arithmetic coding, several hardware-oriented optimizations are applied. Division and modulus operations in the state update are replaced with precomputed reciprocals combined with fixed-point multiply-and-shift sequences. A precision-calibration stage based on remainder-boundary checks corrects substitution errors to ensure exact quotient–remainder equivalence with full-precision division. This calibration is implemented synchronously in the encoder datapath with minimal control overhead to preserve lossless decoding. Parameter storage and lookup overheads are reduced through fine-grained quantization and a compact, flattened Cumulative Distribution Function (CDF) layout, CDF values are linearly scaled and quantized to fixed-width integers, while contiguous storage of valid entries together with stored effective lengths eliminated padding. Tailored bit-width assignments for different parameter types balance precision against resource usage. These measures reduce the CDF table size from 31.125 KB to 6.369 KB while simplifying lookup logic and shortening critical memory-access paths. Throughput is further increased by using an interleaved multi-channel architecture in which the input stream is partitioned into independent substreams processed concurrently by separate RANS encoder instances. Each instances maintain its own local state, parameter memory, and renormalization buffer. Local handling of renormalization and escape conditions preserves channel continuity, enabling the decoder to perform symmetric decoding without global synchronization. Finally, the entire design is organized as a pipeline-friendly datapath. Reciprocal multiplications are mapped to DSP blocks, while lookups and calibration checks occupy adjacent pipeline stages. Renormalized bytes are emitted to an output FIFO to avoid stalls. This eliminates multi-cycle divide units, reduces latency and memory footprint, and provide a scalable path to high-frequency, high-throughput operation. Results and Discussions The proposed model is deployed on a Xilinx Kintex-7 XC7K325T FPGA platform, synthesized using Vivado v2018.2 and functionally verified on ModelSim SE-64 10.4. Data throughput, resource utilization, and compression efficiency are emphasized in the evaluation. Simulation results indicate that the implemented encoder achieves an identical compression ratio to the PyTorch-based open-source CompressAI library. Any degradation in compression efficiency caused by high parallelism is negligible for high-resolution images (≥768 × 512) (Fig. 5 ). The FPGA implementation further shows that timing closure is met at a 140 MHz clock frequency. In single-channel mode, the design consumes only 540 LUTs, 336 FFs, and 9.5 BRAMs. Under high-parallelism configurations, resource utilization scales linearly with the number of channels. In eight-channel parallel mode, the encoder attains a symbol throughput of 191.97 M Symbols/s and a data throughput of 4.607 Gbps, representing an improvement of approximately 766% over single-channel operation (Table 3 ). To quantitatively evaluate the trade-off between resource usage and encoding efficiency, the metric Area Efficiency (AE) is introduced. When compared with FPGA implementations of other entropy coding schemes, the proposed architecture demonstrates clear advantages in both resource efficiency and throughput, achieving an AE of 85.97 K Symbol/(s × Slice), which exceeds most existing high-throughput models. Relative to comparable entropy coding schemes, the proposed design provides a significant increase in throughput (Table 4 ). Moreover, the scalability and adaptability of the architecture are validated across different degrees of parallelism, enabling flexible adjustment of channel count while maintaining superior performance in diverse application scenarios. Conclusions This work proposes a high-throughput RANS arithmetic coding hardware architecture for DNN-based image compression and demonstrates its implementation on an FPGA platform. By integrating hardware-friendly division substitution, fine-grained parameter quantization, and continuous-output interleaved parallelism, the design overcomes key bottlenecks related to computational latency and resource overhead. Experimental results confirm that the proposed model achieves a peak throughput of 191.97 M symbols/s with negligible compression loss, while also demonstrating outstanding AE and linear scalability. The architecture provides significant advantages over existing entropy coding implementations in both resource-constrained and high-performance scenarios, offering strong practical potential for real-time neural network image compression systems. Overall, this research delivers a pragmatic and extensible solution for the hardware realization of DNN-based image compression, with the capability to accelerate large-scale deployment in high-efficiency environments such as intelligent driving.
Available online , doi: 10.11999/JEIT250413
Abstract:
Significance This paper systematically organizes and analyzes the historical progress, fundamental characteristics, application scenarios, and challenges of Stochastic Computing (SC), making four main contributions. (1) Integration of theoretical frameworks and refinement of knowledge systems. By reviewing the evolution of SC from its theoretical origins in the 1940s to its resurgence in the 21st-century Internet of Things era, the paper establishes a coherent theoretical trajectory. The analysis of unipolar and bipolar encoding mechanisms, stochastic bitstream generation architectures, and computational error models provides researchers with a unified technical framework. (2) Demonstration of application potential. Through examinations of three representative scenarios, namely digital filters, image processing, and neural networks, the paper highlights SC’s advantages in hardware efficiency and fault tolerance. For instance, XNOR-gate and multiplexer-based digital filter designs reduce hardware resource consumption by several orders of magnitude, whereas neural network acceleration schemes that employ low-discrepancy sequence-based stochastic sources markedly improve energy efficiency in edge AI devices. These case studies provide implementable technical pathways for engineering practice. (3) Identification of critical challenges and evaluation of solutions. Addressing three major challenges, including correlation accumulation, excessive hardware overhead in random number generation, and the precision–efficiency trade-off, the paper not only quantifies their technical origins but also evaluates the effectiveness and limitations of existing solutions, offering clear optimization directions for further research. (4) Strategic guidance for future research. By integrating emerging technological trends, the paper proposes directions such as algorithm–hardware co-design, dynamic correlation suppression, and adaptive precision adjustment. Special emphasis is placed on the potential of reconfigurable methods and novel architectures to overcome current bottlenecks, outlining research frontiers for both academia and industry. Conclusions This paper systematically reviews the historical development and foundational principles of SC, elaborates on representative application scenarios, and examines the core technical challenges it currently faces. Compared with traditional deterministic numerical computation, SC offers advantages including low hardware overhead, high asymptotic precision, and strong fault tolerance, which have enabled its adoption in digital signal processing, neural network acceleration, and edge computing. Nevertheless, several critical challenges persist and must be resolved to advance its practical deployment. Prospects As a promising pathway to address the computing power and energy efficiency challenges of the post-Moore era, the future development of SC will emphasize overcoming technical bottlenecks and adapting to emerging application scenarios. Advances in reconfigurable computing architectures, memristor-based memory devices, and compute-in-memory chips provide new opportunities for architectural innovation and performance optimization of SC systems. These developments further enhance its intrinsic advantages of low power consumption, high fault tolerance, and progressive precision, positioning SC as a key technological foundation for building high-efficiency computing systems in the post-Moore era.
Available online , doi: 10.11999/JEIT250382
Abstract:
Objective RSA, an asymmetric encryption algorithm, is widely recognized as one of the most secure cryptographic methods. Conventional Rivest-Shamir-Adleman(RSA) private keys face challenges of high storage overhead, power consumption, and vulnerability to attacks. To address the dependency on Non-Volatile Memory (NVM) and the risk of physical probing, a novel RSA private key generation architecture is proposed. The design utilizes fully customized Switched Capacitor Physical Unclonable Functions(SC-PUF) cells for random key generation. By mapping the initial output codes of the weak Physical Unclonable Functions(PUF) to the final private key using One-Time Programmable (OTP) memory, the circuit eliminates the need for independent NVM such as flash or EEPROM. This reduces power and area consumption as well as factory testing costs. An integrated capacitive metal shielding layer in the SC-PUF prevents OTP state compromise, thereby ensuring secure key generation. Methods The proposed OTP mapping-based scheme is implemented and validated in a security ASIC. A low-cost capacitive SC-PUF circuit is employed to generate stable initial PUF keys through capacitance ratio mismatch sampling, with comprehensive shielding applied to protect the entire PUF and OTP circuitry from invasive attacks. To further mitigate such attacks, Metal-Insulator-Metal (MIM) capacitors constructed from two high-layer metals are used to realize the sense capacitor of the SC-PUF. Both the PUF and OTP circuits are encapsulated within a capacitive-sensitive protective layer. An on-chip CMOS-compatible eFuse-based OTP serves as the mapping circuit, and the OTP, PUF extraction circuit, and mapping circuit are placed beneath the capacitive metal coating provided by the PUF. This architecture enables secure, low-cost, and power-efficient private key generation. Results and Discussions The defensive efficacy of SC-PUF and metal shielding against invasive attacks is evaluated by removing the corresponding top metal layer using Focused Ion Beam (FIB) techniques. Although the state of the poly eFuse is directly exposed, complete removal of the top metal layer alters the output key of the SC-PUF (Fig. 7a , b ). In a potential attack scenario, all SC-PUF keys may be probed first, followed by metal layer removal to reveal the eFuse state, with the aim of reconstructing the original PUF output codes and mapping control signals. To assess the protective capability of the proposed architecture against such attacks, probing experiments are conducted on the metal layer to determine whether SC-PUF keys can be externally extracted. A total of eight key units are probed (Fig. 7c –f ). The results show that single-ended probing of the top metal layer leads to a rapid increase in parasitic capacitance to ground, which consistently forces the corresponding output code to 0 (Fig. 7c , e ). In contrast, differential probing introduces parasitic capacitance mismatch larger than the original MIM capacitor mismatch, resulting in deviation of the probed output codes from the original values (Fig. 7d , f ). Among the eight SC-PUF units tested, five exhibit probe results that differ from the original output codes. These observations indicate that probing the metal layer changes the keys due to parasitic capacitance variations, and the extracted information does not represent the true SC-PUF outputs. Therefore, even if the eFuse state is exposed, the SC-PUF keys cannot be reconstructed and the RSA private key cannot be derived. Additionally, existing implementations generally rely on on-chip NVM to store private keys, making them susceptible to data bus-based probing attacks (Table 1 ). In contrast, the proposed scheme employs OTP to map the initial weak PUF output codes to the final private key, thereby eliminating the need for independent NVM (Table 1 ). Although the RSA-2048 algorithm increases logic complexity, leading to a higher gate count and a slight reduction in speed, the proposed OTP mapping-based private key generation circuit achieves a throughput of 187.09 kbps at a power consumption of 218 mW, corresponding to an energy efficiency of 0.858 kbps/mW (Table 1 ). Conclusions To address the dependency on NVM storage and the vulnerability of RSA private keys to physical probing, a novel OTP mapping-based private key generation scheme is proposed. The scheme is programmed at the wafer testing stage, directly mapping the raw PUF output to the target RSA private key, thereby reducing circuit overhead and enabling real-time key generation. This approach effectively mitigates the risk of key interception. Experimental results confirm two key advantages: (1) by mapping the initial output codes of the weak PUF to the final private key through OTP, the scheme eliminates the need for NVM, lowers power and area consumption, and reduces factory test cost. The prototype, fabricated in SMIC 180 nm CMOS technology, occupies 18.77 mm2 and consumes 218 mW; (2) the integrated SC-PUF and metal shielding layer provide effective protection against invasive attacks. This work represents the first application of PUF to RSA private key generation. Furthermore, the proposed scheme can be extended to other asymmetric encryption algorithms requiring private keys, including SM4 and ECC.
Available online , doi: 10.11999/JEIT250367
Abstract:
Objective Bilinear pairing operations are fundamental to modern cryptography, forming the basis of advanced systems applied in identity authentication, key exchange, digital signatures, and attribute-based encryption. However, hardware implementations of bilinear pairings face two major challenges: their high computational complexity results in considerable hardware resource consumption, and traditional Field-Programmable Gate Array (FPGA)-based approaches provide limited flexibility. To address these limitations, this study proposes a solution that integrates the RISC-V architecture with Identity-Based Cryptography (IBC) algorithms through instruction set extension and hardwar-software co-design. The proposed approach reduces hardware resource requirements, enhances system flexibility, and enables efficient implementation of cryptographic algorithms. Methods The methodology is composed of three main steps. First, conventional state machine-based control logic is replaced by an extended RISC-V instruction set. Six custom instructions are introduced to control arithmetic units for fundamental operations, which transforms the hardware implementation of bilinear pairings from control-intensive to data-intensive circuits, thereby improving hardware resource utilization. Second, to mitigate the bottleneck caused by the bus width limitation of RISC-V, a modular multiplication unit and a bus-efficient modular multiplication mode are designed. By adjusting algorithmic timesteps and employing a small number of on-chip temporary registers, this mode integrates data transmission with computation, allowing transmission and computation cycles to overlap. As a result, the proportion of computation cycles in the overall cycle count is increased, improving system efficiency. Third, a hardware–software co-design strategy is adopted, in which higher-level algorithmic flows are scheduled in software to invoke hardware instructions, thus enhancing system flexibility. Results and Discussions (1) Compared with conventional data-intensive circuits, the proposed modular multiplication mode (Fig. 5 ) effectively reduces the proportion of data transmission cycles in extension field operations. Furthermore, timing optimization of modular multiplication in the quartic extension field (Fig. 6 ) and the quadratic extension field (Fig. 7 ) further reduces transmission cycles, thereby improving overall system performance. (2) Relative to FPGA-based implementations of bilinear pairing, the proposed design achieves superior performance in modular multiplication within both the prime field and the quadratic extension field (Table 3 ). It also shows a clear advantage in terms of Area-Time Product (ATP) for complete bilinear pairing operations. In addition, the design supports flexible adjustment of instruction invocation sequences to accommodate the requirements of different IBC algorithms, leading to a marked improvement in system flexibility. Conclusions This paper presents an RISC-V coprocessor that supports bilinear pairing operations for IBC algorithms, addressing the limitations of conventional approaches characterized by high hardware resource consumption, low system utilization, and limited flexibility. A method targeting bus transmission bottlenecks is proposed, which effectively reduces transmission cycle ratios in modular multiplication for quadratic and quartic extension fields. System flexibility is further enhanced by adjusting instruction scheduling to meet the requirements of different IBC algorithms. Future work will focus on exploring pipelined operation modes for more advanced algorithms, using small temporary register groups to further reduce transmission ratios, and achieving cost-effective optimization in data-intensive circuits with balanced area efficiency and computational performance.
Available online , doi: 10.11999/JEIT250551
Abstract:
Objective Non-Volatile Memory (NVM) storage keys are exposed to physical attacks, and most lightweight Internet-of-Things (IoT) devices cannot deploy costly protection. A Physical Unclonable Function (PUF) offers a practical defense. However, Static Random-Access Memory PUFs (SRAM-PUFs) used as key generators exhibit environmental sensitivity that degrades stability. Therefore, optimization methods for SRAM-PUF–based key extraction fall into three main categories: (1) circuit-level enhancements that modify the SRAM cell to strengthen its inherent 0/1 bias; (2) cell selection methods that identify and retain only stable cells through dedicated algorithms; and (3) fuzzy-extractor schemes tailored to SRAM-PUFs that correct residual noise to yield reproducible cryptographic keys. Methods The selection of SRAM cells can markedly enhance bit stability. However, although reducing the complexity of Error-Correcting Code (ECC) encoding and decoding, this approach requires consuming a large number of stable cells to satisfy key entropy requirements, which in turn increases ECC code length. To address this contradiction, this paper proposes a new key extraction scheme (Figure 2 ). In the proposed method, SRAM bits are divided into stable and noisy categories. The high entropy of noisy bits is leveraged for key generation: noisy bits are hashed to produce entropy-rich values, whereas stable bits with a low bit error rate are used to generate PUF responses. In the registration stage, the synthesized key is rearranged to form m vectors (R1,R2,…,Rm)according to m different rules. These m vectors are then combined into a new vector R . A repetition code of length 2t+1 (able to correct t errors) is applied to R to generate a codeword C . The codeword C is XORed with the PUF response to obtain helper data w, which is stored in NVM. In the reconstruction stage, w is XORed with a new PUF response to obtain C ′. Due to the repetition coding applied during registration, decoding is performed using a majority decision rule with a threshold of t+1. The decoding result R ' is reshaped into a matrix D with m rows and x columns, followed by reverse interleaving based on the rules used in registration. A majority decision is then executed independently for each column, with a decision threshold of m/2+1. The recovered key is output as the final result. Results and Discussions SRAM. Tests at −40 °C, 25 °C, and 85 °C show that the proposed bit-selection algorithm reduces the bit-change rate of SRAM-PUFs, with the number of screenings inversely proportional to the average change rate. The bit-change rate is highest at elevated temperatures. After 20 screenings, the average change rate at 85 °C decreases from 0.14 to 0.07, and after 80 screenings, it further decreases to 0.06. A quantitative analysis of error-correction capability is also performed. Based on the measured bit-change rates at high temperatures, the probability of key reconstruction failure is derived as low as 1.487 6E-9. In addition, 1 024 bytes of SRAM cells are shown to yield entropy keys of 128 bits. Conclusions This paper proposes a novel SRAM-PUF key extraction scheme that resolves the trade-off between stability requirements and high entropy demands by employing a bit-selection algorithm. The scheme simplifies error-correction encoding and decoding while enhancing the entropy of the generated keys. Compared with existing approaches, the computational complexity is reduced by 40% relative toScheme 2, by 98.9% relative to Scheme 3, and by 99.12% relative to Scheme 4. Furthermore, the method provides an integrated solution for screening stable SRAM cells, highlighting its practical application potential. Based on the bit error rate of 28 nm SRAM-PUFs, the key reconstruction success rate is calculated as (1-1.4876E-9). In tests conducted at –40 °C, 25 °C, and 85 °C, with 200 key reconstruction attempts per condition, all 11 chips achieved successful reconstruction. Considering variations across different fabrication processes, the number of screening cycles as well as parameters m and t can be adjusted to accommodate other process nodes.
Available online , doi: 10.11999/JEIT250364
Abstract:
Objective Processing-In-Memory (PIM) architectures have emerged as a promising solution to the memory wall problem in modern computing systems by bringing computation closer to data storage. By minimizing data movement between processor and memory, PIM reduces data transfer latency and energy consumption, making it well suited for data-intensive applications such as deep neural network inference and training. Among various PIM implementations, Samsung’s High Bandwidth Memory Processing-In-Memory (HBM-PIM) platform integrates simple computing units within HBM devices, leveraging high internal bandwidth and massive parallelism. This architecture shows strong potential to accelerate compute- and memory-bound AI operators. However, our observations reveal that the acceleration ratio of HBM-PIM fluctuates considerably with matrix size, resulting in limited scalability for large model deployment and inefficient utilization for small- and medium-scale workloads. Addressing these fluctuations is essential to fully exploit the potential of HBM-PIM for scalable AI operator acceleration. This work systematically investigates the causes of performance divergence across matrix scales and proposes an integrated optimization framework that improves both scalability and adaptability in heterogeneous workload environments. Methods Comprehensive performance profiling is conducted on matrix–vector multiplication (General Matrix Vector Multiplication, GEMV) operators executed on an HBM-PIM simulation platform (Fig. 2 , Fig. 3 ), covering matrix sizes from 1 024 × 1 024 to 4 096 × 4 096. Profiling results (Table 1 , Table 2 ) indicate that at smaller matrix scales, hardware resources such as DRAM banks are underutilized, leading to reduced bank-level parallelism and inefficient execution cycles. To address these bottlenecks, a collaborative optimization framework is proposed, consisting of three complementary strategies. First, a Dynamic Bank Allocation Strategy is employed to configure the number of active banks according to input matrix dimensions, ensuring alignment of computational resources with task granularity and preventing unnecessary activation of idle banks. Second, an Odd–Even Bank Interleaved Address Mapping mechanism is applied to distribute data blocks evenly across active banks, thereby reducing access hotspots and enhancing memory-level parallelism (Algorithm 1). Third, a Virtual Tile Execution Framework is implemented to logically aggregate multiple fine-grained operations into coarser-grained execution units, effectively reducing the frequency of barrier synchronization and host-side instruction dispatches (Fig. 5 ). Each strategy is implemented and evaluated under controlled conditions using a cycle-accurate HBM-PIM simulator (Table 3 ). Integration is performed while maintaining compatibility with existing hardware configuration constraints, including the 8-lane register file limits per DRAM bank. Results and Discussions Experimental results (Fig. 6 , Fig. 7 ) show that the optimization framework delivers consistent and substantial performance improvements across different matrix scales. For instance, with a 2 048 × 2 048 matrix input, the acceleration ratio increased from 1.296 (baseline) to 3.479 after optimization. With a 4 096 × 4 096 matrix, it improved from 2.741 (baseline) to 8.225. Across all tested sizes, the optimized implementation achieved an average performance gain of approximately 2.7× relative to the baseline HBM-PIM configuration. Beyond raw acceleration, the framework improved execution stability by preventing the performance degradation observed in baseline implementations under smaller matrices. These results demonstrate that the combination of dynamic resource allocation, balanced address mapping, and logical operation aggregation effectively mitigates resource underutilization and scheduling inefficiencies inherent to HBM-PIM architectures. Further analysis confirms that the framework enhances scalability and adaptability without requiring substantial hardware modifications. By aligning resource activation granularity with workload size and reducing host–device communication overhead, the framework achieves better utilization of available parallelism at both memory and computation levels. This leads to more predictable performance scaling under heterogeneous workloads and strengthens the feasibility of deploying AI operators on commercial PIM systems. Conclusions This study presents a collaborative optimization framework to address performance instability of GEMV operators on commercial HBM-PIM architectures under varying matrix scales. By combining dynamic bank allocation, odd–even interleaved address mapping, and virtual tile execution strategies, the framework achieves consistent and scalable acceleration across small to large matrices while enhancing execution stability and resource utilization. These findings provide practical guidance for software–hardware co-optimization in PIM-based AI acceleration platforms and serve as a reference for the design of future AI accelerators targeting data-intensive tasks. Future work will focus on extending the framework to additional AI operators, validating its effectiveness on real hardware prototypes, and investigating integration with compiler toolchains for automated operator mapping and scheduling.
Available online , doi: 10.11999/JEIT250387
Abstract:
Objective Visual grounding requires effective use of textual information for accurate target localization. Traditional methods primarily emphasize feature fusion but often neglect the guiding role of text, which limits localization accuracy. To address this limitation, a Multi-granularity Text Perception and Hierarchical Feature Interaction method for Visual Grounding (ThiVG) is proposed. In this method, the hierarchical feature interaction module is progressively incorporated into the image encoder to enhance the semantic representation of image features. The multi-granularity text-aware module is designed to generate weighted text with spatial and semantic enhancement, and a preliminary Hadamard product–based fusion strategy is applied to refine image features for cross-modal fusion. Experimental results show that the proposed method substantially improves localization accuracy and effectively alleviates the performance bottleneck arising from over-reliance on feature fusion modules in conventional approaches. Methods The proposed method comprises an image–text feature extraction network, a hierarchical feature interaction module, a multi-granularity text perception module, and a graphic–text cross-modal fusion and target localization network (Fig. 1 ). The image–text feature extraction network includes image and text branches for extracting their respective features (Fig. 2 ). In the image branch, text features are incorporated into the image encoder through the hierarchical feature interaction module (Fig. 3 ). This enables text information to filter and update image features, thereby strengthening their semantic expressiveness. The multi-granularity text perception module employs three perception mechanisms to fully extract spatial and semantic information from the text (Fig. 4 ). It generates weighted text, which is preliminarily fused with image features through a Hadamard product–based strategy, providing fine-grained image features for subsequent cross-modal fusion. The graphic–text cross-modal fusion module then deeply integrates image and text features using a Transformer encoder (Fig. 5 ), capturing their complex relationships. Finally, a Multilayer Perceptron (MLP) performs regression to predict the bounding box coordinates of the target location. This method not only achieves effective integration of image and text information but also improves accuracy and robustness in visual grounding tasks through hierarchical feature interaction and deep cross-modal fusion, offering a novel approach to complex localization challenges. Results and Discussions Comparison experiments demonstrate that the proposed method achieves substantial accuracy gains across five benchmark visual localization datasets (Tables 1 and 2 ), with particularly strong performance on the long-text RefCOCOg dataset. Although the model has a larger parameter size, comparisons of parameter counts and training–inference times indicate that its overall performance still exceeds that of traditional methods (Table 3 ). Ablation studies further verify the contribution of each key module (Table 4 ). The hierarchical feature interaction module improves the semantic representation of image features by incorporating textual information into the image encoder (Table 5 ). The multi-granularity text perception module enhances attention to key textual components through perception mechanisms and adaptive weighting (Table 6 ). By avoiding excessive modification of the text structure, it markedly strengthens the model’s capacity to process long text and complex sentences. Experiments on the number of encoder layers in the cross-modal fusion module show that a 6-layer deep fusion encoder effectively filters irrelevant background information (Table 7 ), yielding a more precise feature representation for the localization regression MLP. Generalization tests and visualization analyses further demonstrate that the proposed method maintains high adaptability and accuracy across diverse and challenging localization scenarios (Figs. 6 , and 7 ). Conclusions This study proposes a visual grounding algorithm that integrates multi-granularity text perception with hierarchical feature interaction, effectively addressing the under-utilization of textual information and the reliance on single-feature fusion in existing approaches. Key innovations include the hierarchical feature interaction module in the image branch, which markedly enhances the semantic representation of image features; the multi-granularity text perception module, which fully exploits textual information to generate weighted text with spatial and semantic enhancement; and a preliminary Hadamard product–based fusion strategy, which provides fine-grained image representations for cross-modal fusion. Experimental results show that the proposed method achieves substantial accuracy improvements on classical vision datasets and demonstrates strong adaptability and robustness across diverse and complex localization scenarios. Future work will focus on extending this method to accommodate more diverse text inputs and further improving localization performance in challenging visual environments.
Available online , doi: 10.11999/JEIT250502
Abstract:
Objective In microwave modules, assembly gaps often occur between power amplifier chips and multilayer hybrid circuit boards or among different circuit units. These gaps form deep transition trenches that significantly degrade RF signal transmission quality, particularly at millimeter-wave frequencies. Bonding wires remain a critical solution for establishing electrical interconnections between RF chips and other structures. However, the inherent parasitic inductance of gold bonding wires adversely affects system performance. As RF modules increasingly operate in the Ka-band and W-band, the degradation caused by this parasitic inductance has become more pronounced. The problem is especially severe when the ground–signal return path is excessively long or when the bonding wires themselves are too long. Methods The impedance transformation paths of T-type and π-type matching networks are compared on the Smith chart. The analysis indicates that for a given parasitic inductance of bonding wires, the Q-circle of the π-type matching network is smaller, thereby enabling a broader matching bandwidth. A π-type matching network for chip-to-chip interconnection is realized by optimizing the bonding pad dimensions on the GaAs chip to provide capacitive loading. As the bonding pad size increases, more gold wires can be bonded to the chip, which simultaneously reduces the parasitic inductance of the wires. Additionally, a symmetric “Ground–Signal–Ground (GSG)” bonding pad structure is designed on the GaAs chip, which shortens the ground return path and further reduces the parasitic inductance of the bonding wires. By integrating these three design strategies, the proposed chip and transition structure are shown to substantially improve the performance of cross-deep-gap transitions between different circuit units in microwave modules. Results and Discussions The proposed chip and transition structure substantially improve the performance of cross-trench transitions between different circuit units in microwave modules (Fig. 7 ). Simulation results show that the interconnection architecture effectively mitigates the adverse effects of trench depth on RF characteristics (Fig. 9 ). Experimental validation further confirms that the π-type matching network implemented with the designed chip achieves an ultra-wideband, high-performance cross-trench transition, with a return loss of ≥ 17 dB and an insertion loss of ≤ 0.7 dB over the DC–40 GHz frequency range (Fig. 10 ). Conclusions Comparative analysis of impedance transformation paths between T-type and π-type matching networks demonstrates that in gold-wire bonding interconnections, the π-type configuration is more effective in mitigating the effect of bonding wire parasitic inductance on matching bandwidth, making it suitable for ultra-wideband bonded interconnection circuits. To implement the π-type matching network using GaAs technology, the bonding pad area on the chip is enlarged to provide capacitive loading and to allow additional bonding wires, thereby further reducing parasitic inductance. A GSG structure is also designed on the GaAs chip surface to modify the reference ground return path of the bonded interconnections, leading to additional reduction in parasitic inductance. By integrating these features, an ultra-wideband compensation chip is developed and applied to cross-trench transition structures in microwave modules. Experimental results indicate that for a transition structure with a trench depth of 2 mm and a width of 0.2 mm, the proposed design achieves high-performance characteristics from DC to 40 GHz, with return loss ≥ 17 dB and insertion loss ≤ 0.7 dB. When applied to interconnections between RF chips and circuit boards in microwave modules, the chip also significantly enhances the RF matching performance of bonded interconnections.
Available online , doi: 10.11999/JEIT250633
Abstract:
Significance With the continuous advancement of aerospace technology and the growing demand for space applications, space-based computing chips have assumed increasingly important strategic roles as core hardware infrastructure of space information systems. As the technological foundation enabling intelligent data processing and reliable communications for spacecraft—including satellite platforms, space stations, and deep space probes—space-based computing chips not only safeguard national security and support economic development but also play an irreplaceable role in serving civilian needs. Although existing survey literature has systematically reviewed the development of aerospace Central Processing Units (CPUs), comprehensive analyses of other key components within the space-based computing chip ecosystem remain limited. To address this gap, this paper systematically examines the technological evolution of various space-based computing chips and their principal fault-tolerant mechanisms, and further explores potential future trends in this field. Progress This paper adopts a functional architecture-oriented classification to systematically analyze and summarize the current technological status of space-based computing chips across three dimensions: CPU, Field-Programmable Gate Array (FPGA), and dedicated chip. For CPU technology, a classification study of general-purpose processors widely used in aerospace applications is conducted based on instruction set architectures, with in-depth analysis of the technical characteristics and representative products of various architectures, together with an objective evaluation of their advantages and limitations in space environments. In the FPGA domain, the technical specifications and performance characteristics of mainstream space-grade FPGA products, both domestic and international, are comprehensively reviewed to provide a reference for application selection. For dedicated chips, a detailed categorization is carried out according to functional architectural features and application scenario requirements, covering Digital Signal Processing (DSP) chips for signal processing acceleration, Graphics Processing Unit (GPU) chips for graphics computation, and Neural Processing Unit (NPU) chips for space-based artificial intelligence applications, thereby systematically clarifying the applicability of different architectures in complex space environments. In addition, this paper presents an in-depth analysis of the key fault-tolerant technology framework for space-based computing chips at multiple levels, including system, architecture, circuit, and process library, and provides a comprehensive evaluation of the technical advantages, application limitations, and development prospects of various fault-tolerant mechanisms. This analysis offers theoretical guidance for the reliability design of space-based computing chips. Conclusions This review systematically summarizes the technological development of space-based computing chips, providing a comprehensive analysis of the architectural characteristics of different chip types and their associated fault-tolerant technology frameworks, while elucidating the applicable scenarios and technical limitations of various fault-tolerant mechanisms. The central principle of fault-tolerant design for space-based computing chips is to achieve effective detection and correction of circuit faults through redundancy mechanisms. This paper offers an in-depth analysis of the implementation principles and application characteristics of fault-tolerant technologies at four hierarchical levels: system, architecture, circuit, and process library. Although these multi-level approaches substantially improve system reliability, they inevitably introduce hardware resource overhead and performance penalties. Therefore, the engineering design of space-based computing chips requires optimized strategies that combine multi-level fault-tolerant technologies according to specific reliability requirements, aiming to balance reliability, cost, and performance to meet the intended design objectives and technical specifications. Prospects Looking ahead, space-based computing chips present broad prospects in high computing capability, widespread adoption of Commercial Off-The-Shelf (COTS) devices, and the development of Reduced Instruction Set Computer – Five (RISC-V) instruction set architectures. With the rapid advancement of space technology, space-based systems are undergoing a transformation from traditional single-function platforms to integrated platforms characterized by multi-task collaboration, autonomy, and intelligence. Real-time data processing, multi-task parallel computing, and intelligent decision-making have become the principal driving forces in the evolution of space-based computing technology, all of which demand robust computational foundations. Compared with traditional radiation-hardened specialized devices, COTS devices are emerging as a major trend in space-based computing chip development due to their advantages in cost-effectiveness, computational performance, shorter development cycles, and product diversity. In addition, RISC-V, as an open-source instruction set architecture, offers unique advantages and significant potential for space-based computing chip innovation through its modular design philosophy, exceptional scalability, and open ecosystem.
Available online , doi: 10.11999/JEIT250128
Abstract:
Objective The computational performance of Zeroing Neural Networks (ZNNs) is enhanced by introducing additional power terms into the activation function. However, this strategy complicates the derivation of explicit settling time expressions. To address this issue, a triple power-rate activation function is designed, and a power-rate speeding-up noise-tolerant terminal ZNN is constructed, through which an exact expression for the settling time is derived. In previous studies, the optimization criterion parameter for repetitive motion planning was typically constant, which may reduce the operational efficiency of robotic manipulators. To overcome this limitation, a time-varying parameter optimization criterion is developed to satisfy task requirements at different stages of repetitive motion planning, thereby improving the operational efficiency of redundant robotic manipulators during task execution. Methods A triple power-rate activation function is proposed, extending the conventional bi-power activation function, and a power-rate speeding-up noise-tolerant terminal ZNN is constructed. The convergence process under different parameter settings is analyzed, and explicit settling time expressions are derived. Theoretical analysis confirms that the proposed neural network can effectively suppress vanishing noise. For the repetitive motion planning problem of redundant manipulators, the power-rate speeding-up noise-tolerant terminal ZNN is employed as a solver to ensure acquisition of the desired end-effector trajectory within fixed time. To address the limitations of constant-parameter optimization criteria in repetitive motion planning, a time-varying parameter optimization criterion is designed, which demonstrably improves the operational efficiency of redundant manipulators. Results and Discussions In this study, the power-rate speeding-up noise-tolerant terminal ZNN is employed together with bi-power-rate terminal ZNNs to solve time-varying quadratic programming problems. Simulation results show that the proposed power-rate speeding-up noise-tolerant terminal ZNN achieves a faster convergence rate (Fig.2(a) , Fig.2(b) ) and demonstrates improved capability in suppressing vanishing noise (Fig.2 (c)). The convergence process of neural computational error under different parameter conditions is analyzed without noise (Fig 3 ). Furthermore, the power-rate speeding-up noise-tolerant terminal ZNN is applied to the repetitive motion planning problem of redundant manipulators. Its effectiveness in solving repetitive motion planning is validated (Fig. 4 ), and the integration of a time-varying parameter optimization criterion further enhances the operational efficiency of redundant manipulators (Fig. 5 ). Conclusions A power-rate speeding-up noise-tolerant terminal ZNN is proposed for solving time-varying quadratic programming problem with time-varying equality constraints, ensuring fixed time convergence of neural computing errors. Compared with conventional bi-power-rate terminal ZNNs, the proposed network achieves faster convergence and stronger noise-tolerance performance. To address the limitations of constant-parameter optimization criteria in repetitive motion planning, a time-varying parameter optimization criterion is designed and shown to improve the operational efficiency of redundant manipulators.
Available online , doi: 10.11999/JEIT250322
Abstract:
Objective Modern battlefield environments, characterized by complex and dynamically uncertain target behaviors combined with information asymmetry, present significant challenges for intent prediction. Conventional methods lack robustness in processing incomplete data, rely on oversimplified behavioral models, and fail to capture tactical intent semantics or adapt to rapidly evolving multi-target coordinated scenarios. These limitations restrict their ability to meet the demands of real-time recognition of high-value target intent and comprehensive ground target situational awareness. To address these challenges, this study proposes a Threat Field-integrated Gated Recurrent Unit model (TF-GRU), which improves prediction accuracy and robustness through threat field modeling, dynamic data repair, and multi-target collaboration, thereby providing reliable support for battlefield decision-making. Methods The TF-GRU framework integrates static and dynamic threat field modeling with a hybrid Particle Filtering (PF) and Dynamic Time Warping (DTW) strategy. Static threat fields quantify target-specific threats (e.g., tanks, armored vehicles, artillery) using five factors: enemy-friend distance, range, firepower, defense, and mobility. Gaussian and exponential decay models are employed to describe spatial threat diffusion across different target categories. Dynamic threat fields incorporate real-time kinematic variables (velocity, acceleration, orientation) and temporal decay, allowing adaptive updates of threat intensity. To address incomplete sensor data, a PF-DTW switching mechanism dynamically alternates between short-term PF (N = 1 000 particle) and long-term historical trajectory matching (DTW with β = 50). Collaborative PF introduces neighborhood angular constraints to refine multi-target state estimation. The GRU architecture is further enhanced with Mish activation, adaptive Xavier initialization, and threat-adaptive gating, ensuring effective fusion of trajectory and threat features. Results and Discussions Experiments were conducted on a simulated dataset comprising 40 trajectories and 144,000 timesteps. Under complete data conditions, the TF-GRU model achieved the highest accuracy on both the training and test sets, reaching 94.7% and 92.9%, respectively, indicating strong fitting capability and generalization performance (Fig. 10 ). After integrating static and dynamic threat fields, model accuracy increased from 72% (trajectory-only input) to 83%, accompanied by substantial improvements in F1 scores and reductions in predictive uncertainty (Fig. 6 ). In scenarios with 30% missing data, TF-GRU maintained an accuracy of 86.2%, outperforming comparative models and demonstrating superior robustness (Fig. 10 ). These results confirm that the PF-DTW mechanism effectively reduces the adverse effects of both short-term and long-term data loss, while the collaborative PF strategy strengthens multi-target prediction through neighborhood synergy (η = 0.6). This combination enables robust threat field reconstruction and reliable intent inference (Figs. 8 ～9 ). Conclusions The TF-GRU model effectively addresses the challenges of intent prediction in complex battlefield environments with incomplete data through threat field modeling, the PF-DTW dynamic repair mechanism, and multi-target collaboration. It achieves high accuracy and robustness, providing reliable support for situational awareness and command decision-making. Future work will focus on applying the model to real-world datasets and enhancing computational efficiency to facilitate practical deployment.
Available online , doi: 10.11999/JEIT250447
Abstract:
Objective Ultra-Reliable Low-Latency Communication (URLLC) in 5G and the emerging Hyper-Reliable Low-Latency Communication (HRLLC) in 6G impose exceptionally stringent requirements on both reliability and end-to-end delay. These requirements create opportunities and challenges for short-length channel codes, particularly in scenarios where Maximum-Likelihood (ML) or near-ML decoding is desirable but computational complexity and latency are prohibitive. Ordered Statistic Decoding (OSD) is a universal near-ML decoding technique that can closely approach finite-length performance bounds. However, its re-encoding step suffers from combinatorial explosion, resulting in impractical complexity in high-throughput and low-latency systems. The excessive number of Test-Error-Pattern (TEP) re-encodings fundamentally restricts the deployment of OSD in URLLC and HRLLC contexts. To address this bottleneck, we design multiple efficient skip mechanisms that substantially reduce re-encoding operations while maintaining negligible performance degradation. Methods Three complementary skipping mechanisms are developed to prune the OSD re-encoding search: (1) Soft-information based skipping. Two criteria are introduced—Trivial and Dynamic Approximate Ideal (DAI), to compare the soft metric of each TEP against the minimum soft weight in the current list. Candidates with excessively large soft weights, which are unlikely to be correct, are skipped. Unlike prior work that evaluates only the first TEP at each Hamming weight increment, both criteria are applied to every candidate. The Trivial criterion ensures no performance loss by skipping only when a TEP’s soft metric exceeds the best-so-far. The DAI criterion incorporates an expected residual soft-weight compensation term over non-basis bits, enabling more aggressive skipping with minimal performance degradation. (2) Extra-parity skipping. The search dimension is expanded from \begin{document}$ k $\end{document} \begin{document}$ k+\delta $\end{document} \begin{document}$ \delta $\end{document} \begin{document}$ ({\boldsymbol{e}}_{\mathrm{L}},{\boldsymbol{e}}_{\delta })\in {\mathbb{F}}_{2}^{k+\delta } $\end{document} Results and Discussions Extensive simulations on extended BCH \begin{document}$ \left[\mathrm{128,64}\right] $\end{document} \begin{document}$ \left[\mathrm{127,64}\right] $\end{document} \begin{document}$ t=4 $\end{document} \begin{document}$ 6.7\times {10}^{5} $\end{document} \begin{document}$ 1.2\times {10}^{3} $\end{document} Fig. 1 ). Extra-parity skipping: For \begin{document}$ \delta =4 $\end{document} \begin{document}$ 90 \% $\end{document} Fig. 2 ). Joint skipping: The combined mechanism demonstrates superior performance over individual schemes. It reduces average re-encodings by an additional ～40% compared with the DAI rule alone, and by more than \begin{document}$ > 99.9 \% $\end{document} \begin{document}$ \sim 6.7\times {10}^{5} $\end{document} Fig. 3 ). The joint skipping mechanism is further evaluated on BCH codes with different rates, including \begin{document}$ \left[\mathrm{127,36}\right] $\end{document} \begin{document}$ \left[\mathrm{127,64}\right] $\end{document} \begin{document}$ \left[\mathrm{127,92}\right] $\end{document} Fig. 4 ). A comparative analysis with state-of-the-art schemes—including Probabilistic Sufficient/Necessary Conditions (PSC/PNC), Fast OSD (FOSD), and Order-Skipping OSD (OS-OSD)—shows that the proposed joint skipping OSD with \begin{document}$ \delta =4 $\end{document} Fig. 5 ). Conclusions To address the stringent reliability and latency requirements of 5G URLLC and future 6G HRLLC, this work presents novel skipping mechanisms for OSD that substantially reduce re-encoding complexity. For offline pre-computed TEPs, the soft-information, extra-parity, and joint skipping rules eliminate more than \begin{document}$ 99 \% $\end{document} \begin{document}$ 6.7\times {10}^{5} $\end{document}
Available online , doi: 10.11999/JEIT250527
Abstract:
Objective The globalization of the Integrated Circuit (IC) supply chain has created a crisis of hardware trust, exposing systems to hardware security threats. Logic locking, a key Design-For-Trust (DFT) technique, protects hardware designs by inserting key-driven gates that obfuscate the original circuit, thereby mitigating threats such as intellectual property theft and hardware Trojans. The effectiveness of logic locking is determined by its output obfuscation level, which directly influences resilience against existing attacks. This level is quantified by two sub-metrics: randomness and inconsistency. Weakness in either sub-metric enables targeted attacks, and current methods achieve limited performance on both, restricting their practical security guarantees. To address these limitations, this study proposes a logic locking approach that improves the output obfuscation level of locked circuits using linear programming. Methods A Linear Programming-based Logic Locking (LPLL) method is proposed to optimize output obfuscation under incorrect keys. The core idea is to model each circuit gate as a set of linear constraints, thereby transforming the objective of maximizing the output obfuscation level into a solvable linear objective function. This formulation determines the optimal placement of key gates that are specifically activated by incorrect keys. Because adversaries in real-world attack scenarios rely on random key guessing, key gates may remain inactive, leading to weakened obfuscation. To address this vulnerability, an auto-incrementing key selection algorithm is introduced. This algorithm iteratively builds upon and inherits prior optimization results, thereby strengthening robustness. The iterative mechanism ensures persistent output corruption: even if key gates selected at later stages remain inactive, obfuscation is still enforced by those optimized in earlier iterations. Results and Discussions Experimental results demonstrate that the proposed LPLL method substantially enhances output obfuscation. For equivalent key sizes, LPLL markedly increases the randomness of output obfuscation, consistently sustaining a high degree of unpredictability. Quantitatively, it improves the probability of randomness by up to 24.1% compared with Fault analysis-based Logic Locking (FLL) and by 49.9% compared with Random Logic Locking (RLL) (Fig. 4 ). In addition to randomness, LPLL exhibits a clear advantage in output obfuscation inconsistency. While both LPLL and FLL achieve improved inconsistency with increasing key sizes, LPLL consistently reaches higher inconsistency values across most scenarios. Specifically, it raises the probability of inconsistency by up to 24.1% relative to FLL and by 62.5% relative to RLL (Fig. 5 ). This advantage is particularly pronounced at smaller key sizes, where LPLL achieves greater inconsistency spread and more efficient key utilization, making it especially suitable for resource-constrained applications. Conclusions This work presents LPLL, an approach that redefines logic locking by mapping complex circuit structures onto a linear programming model. The method systematically formulates optimal key-gate selection as a solvable linear optimization problem. To further strengthen security, LPLL incorporates an auto-incrementing key selection algorithm that establishes an iterative mechanism, ensuring persistent high-level output obfuscation even under dynamic attack conditions. LPLL not only exceeds existing methods such as RLL and FLL)in output obfuscation metrics but also, more importantly, provides a systematic and quantifiable paradigm for determining key-gate layouts. This research offers a forward-looking perspective for the design of trustworthy hardware.
Available online , doi: 10.11999/JEIT250626
Abstract:
Significance Chiplet technology, enabled by advanced packaging techniques, integrates multiple chiplets into a single package to form a larger-scale chip system. This approach breaks through the “Area Wall” faced by traditional processes and has become a critical path for improving computing performance in the post-Moore era. The design flexibility afforded by packaging-level integration has created a new design paradigm that drives iterative advances in computing and integration architectures. In traditional monolithic chip design, architecture and packaging are relatively independent stages. By contrast, the ability to integrate chiplets fabricated in different processes and the scalability of chiplet technology greatly expand the design space but also increase design complexity. At the same time, the higher transistor density per unit volume intensifies multi-physics coupling effects, including thermal, mechanical, and electrical interactions. Therefore, traditional methods that rely solely on packaging design to address performance degradation and reliability issues are no longer sufficient for chiplet-based systems. Instead, architecture and packaging in chiplet design must be co-designed in a coordinated manner. Progress This work addresses the critical issues of architecture–packaging co-design in the context of chiplet systems. It reviews architectural design and co-optimization efforts, demonstrates the necessity of co-design, and proposes co-design optimization methodologies. First, it summarizes architectural characteristics and development trends driven by advanced packaging technologies. These technologies are categorized into 2D, 2.5D, 3D, and 3.5D integration according to chiplet arrangement and interconnection technologies, each leading to substantial architectural differences. A detailed comparison of packaging technologies is provided, outlining the architectural features and co-design considerations associated with each. The necessity of co-design is then clarified from the perspective of the profound effect of packaging technologies on performance and reliability. The increased integration density per unit volume in chiplet-based circuits introduces serious reliability challenges, including complex multi-physics coupling effects such as thermal, mechanical, and electrical interactions. Multiple research studies on chiplet reliability are cited, highlighting the severity of thermal, mechanical, and electrical problems arising from these couplings. Unlike traditional monolithic chip designs, reliability issues in chiplet-integrated circuits cannot be resolved through standalone packaging-level design. Separate design of architecture and packaging introduces performance risks and leads to unpredictable design and manufacturing timelines and costs. Therefore, co-design of architecture and packaging is a necessary trend for the advancement of chiplet-based circuits. Finally, by reviewing existing cross-layer co-optimization efforts, an architecture–packaging co-optimization methodology is proposed to provide guidance for design optimization. Key design factors and evaluation metrics at both the architectural and packaging levels are summarized, and the interfaces for cross-layer co-design are clarified. The co-design interface consists of two components: design factors and evaluation metrics. Adjustments to any design factor within the design space affect multiple evaluation metrics, which in turn drive the convergence of the design space. Two key components are summarized for each design layer: (1) the definition of the design parameter space and exploration methods, and (2) the selection of evaluation metrics together with evaluation models and methodologies. The co-design process is outlined in eight key steps, illustrated by prior works. Existing architecture–packaging co-design methods are reviewed, and design workflows are categorized and characterized. Conclusions Driven by the evolution of chiplet technology and objectives such as performance and cost, chiplet-integrated circuit architectures have developed characteristics that differentiate them from traditional monolithic designs. The strong coupling between architecture and packaging layers has substantially increased design complexity, while higher integration density has introduced intricate multi-physics interactions, elevating reliability risks. The traditional design paradigm, in which architecture and packaging are developed independently, now faces challenges including performance degradation, unpredictable verification timelines, and uncontrollable costs. Co-design has therefore emerged as a critical solution. Establishing cross-layer collaborative methods and making trade-offs among multidimensional objectives are essential. By defining the design spaces for both architecture and packaging, formulating efficient exploration strategies, and applying system- and packaging-level evaluation methods, it becomes possible to rapidly and accurately identify optimal design solutions. Architecture–packaging co-design enables performance, reliability, and other objectives to be optimized synergistically at the early stages of chiplet-integrated circuit design with minimal cost. This approach maximizes the benefits of high integration density while mitigating risks in chip design and manufacturing. Prospects Architecture–packaging co-design represents the future paradigm for chiplet design. Current co-design approaches remain limited in applicability: methods that rely on detailed models such as RTL and netlists, together with EDA tools, are unsuitable for early-stage chip development, whereas abstract modeling techniques may neglect critical design issues and introduce substantial inaccuracies. Future co-design methodologies must adapt to different stages of the design process and support the iterative advancement of both computing architectures and integration architectures.
Available online , doi: 10.11999/JEIT250458
Abstract:
Objective Parasitic extraction is a critical stage in the VLSI design flow, as it determines the parasitic parameters of interconnect wires, directly affecting delay evaluation, timing analysis, and performance verification. With the increasing complexity of modern designs, accurate estimation of parasitic parameters has become a central challenge in routing. Developing a fast and accurate extraction algorithm is therefore essential to enable high-performance routing solutions. Methods Pattern matching is a widely used technique for full-layout parasitic extraction. Given an interconnect layout, the method divides it into small sections and determines the parasitics of each section with a pre-built pattern library. However, with billions of transistors placed on a single chip, the continuous growth of design complexity makes full-layout parasitic extraction increasingly challenging. Inspired by pattern matching, this paper presents a probability-based parasitic extraction algorithm tailored for modern VLSI designs. The proposed method consists of two main stages: (1) layout analysis and (2) parasitic extraction. Given a global-routed netlist and technology files containing pre-characterized parasitic values, layout analysis captures coupling segment information and generates a probability-based look-up table for efficient wire-spacing computation. Parasitic extraction then constructs the RC tree for each net and produces accurate interconnect parasitic parameters using the spacing information derived from layout analysis. For layout analysis, a partitioning strategy is employed to identify coupling segments that are parallel to and overlap with the target wire segment. In practice, coupling segments far from the target wire exert negligible effects on parasitics; therefore, the chip layout is divided into regions to improve identification efficiency. During parasitic extraction, coupling segments in both the same layer and in abutting layers are considered. If the target wire fully traverses the grids in an adjacent layer, all segments in those grids are treated as cross segments; otherwise, only partially overlapping segments are included. Once the coupling segments are determined, wire spacing must be calculated. In parasitic extraction, spacing represents the distance between a wire and its nearest neighbor. Because of the vast number of wires in modern circuits, computing exact spacing for every wire is prohibitively expensive. To address this, a probability-based average spacing model is proposed. In multilayer circuit designs, extraction also requires accurate reconstruction of routing information from layout data. In the standard Design Exchange Format (DEF), routing topology is represented by wires and vias. To handle this efficiently, a construction algorithm is developed to build connected RC trees from distributed wires and vias. Leveraging the probability-based wire-spacing model together with the technology files, the algorithm extracts parasitic parameters while accounting for coupling effects. The technology file “.captbl” provides interconnect parasitic tables indexed by wire width and spacing, with widths varying across different metal layers due to process constraints. Interpolation methods are first applied to obtain the unit resistance as a function of wire spacing and width. Wire resistance is then modeled by multiplying this unit resistance by wire length. Similarly, capacitance is extracted using interpolation, with additional coupling effects between neighboring layers captured through a grid-based recognition strategy that identifies the number of cross segments. Relative coupling capacitance is then determined accordingly. Results and Discussions Experiments were conducted on twelve industrial designs to evaluate the proposed extraction algorithm. The results demonstrate that the method achieves high parasitic accuracy while being 21.6% faster than the commercial tool Innovus. The average capacitance error is 1.15% with a standard deviation of 3.09%, and the average resistance error is 0.08% with a standard deviation of 2.63%. Notably, for all twelve circuits, the standard deviation of both capacitance and resistance errors remains below 5%. These findings confirm that the proposed algorithm provides both accuracy and efficiency for full-chip parasitic extraction, offering a practical foundation for developing high-performance routing algorithms. Conclusions This paper presents a probability-based parasitic extractor for addressing full-chip extraction challenges. A partitioning strategy with grid-based data representation is developed to capture coupling segments efficiently. Based on these segments, a probability-driven mathematical model is proposed to calculate wire spacing, with a pre-computed look-up table accelerating the computation. An efficient construction algorithm is further presented to build connected RC trees from distributed wires and vias, followed by a coupling-aware RC extraction method to produce accurate interconnect parasitics. Experimental evaluation on twelve industrial benchmarks demonstrates strong correlation between the extracted parasitics and those obtained from the commercial tool Innovus.
Available online , doi: 10.11999/JEIT250501
Abstract:
Objective Ordered Reliability Bits Guessing Random Additive Noise Decoding (ORBGRAND) is a universal channel decoding algorithm characterized by its simple principles, strong decoding performance, low average latency, and hardware-friendly implementation. Since its proposal, ORBGRAND has attracted considerable attention as a promising alternative to traditional decoding methods. By combining ordered reliability bits with a noise-guessing strategy, it achieves near Maximum-Likelihood Decoding (MLD) performance while avoiding prohibitive resource overhead. However, challenges remain: its worst-case latency and limited throughput restrict practical use in high-speed communication systems. To address these gaps, this work proposes improved ORBGRAND serial and unrolled hardware architectures that incorporate a special parity-check constraint. Methods This study proposes incorporating a specific parity-check constraint into serial and unrolled ORBGRAND architectures. In the serial architecture, the global parity-check bit is used to control the iteration of Hamming Weight (HW) and Logistic Weight (LW), enabling the decoder to skip the generation and verification of invalid error patterns. In the unrolled architecture, error patterns are separately pre-stored and queried according to the global parity-check bit. This design significantly enhances the hardware efficiency of ORBGRAND decoders. Results and Discussions The improved serial and unrolled ORBGRAND decoders with the global parity-check constraint are implemented and compared with their original counterparts. Simulation results for a tested code indicate that the parity-check constraint preserves the decoding performance of conventional ORBGRAND, while reducing the average number of error pattern queries by 50% in the low to medium Signal-to-Noise Ratio (SNR) range. The architectures are synthesized using Synopsys Design Compiler with TSMC 28 nm technology. The serial ORBGRAND architecture achieves an operating frequency of 400 MHz, delivering a throughput of 33.1 Gbps at SNR = 8 dB. The implementation occupies 0.18 mm2 of area, yielding an area efficiency of 183.9 Gbps/mm2. Compared with the prior art, the serial design increases throughput by 80.9% and area efficiency by 48.1%. The unrolled architecture achieves a throughput of 110.6 Gbps and an area efficiency of 3.97 Gbps/mm2, corresponding to improvements of 584% in throughput and 1223 % in area efficiency relative to the prior art. Conclusions The ORBGRAND algorithm offers a promising approach for high-performance decoding in communication systems by combining high parallelism with near MLD performance. The specific parity-check constraint filters out invalid error patterns, significantly reducing the number of error pattern queries in serial and unrolled ORBGRAND architectures, without compromising performance. The serial and unrolled architectural implementations achieve notable gains in throughput and area efficiency compared with original designs. Integrating ORBGRAND with parity-check constraints thus represents a significant advancement, providing a more efficient solution for pratical communication applications. Future work will focus on further optimization of these architectures and their adaptation to diverse communication standards. In particular, the exploration of additional coding contraints may further extend the applicability of the approach.
Available online , doi: 10.11999/JEIT250334
Abstract:
Objective Traditional Through-the-Wall Radar (TWR) systems based on planar multiple-input multiple-output arrays often face high hardware complexity, calibration challenges, and increased system cost. To overcome these limitations, we propose a Three-Dimensional (3D) imaging framework based on array stitching. The method uses either time-sequential or simultaneous operation of multiple small-aperture radar sub-arrays to emulate a large aperture. This strategy substantially reduces hardware complexity while maintaining accurate 3D imaging of concealed human targets. Methods The proposed framework integrates three core techniques: 3D weighted total variation (3DWTV) reconstruction, Lucy–Richardson (LR) deconvolution, and 3D wavelet transform (3DWT)-based fusion. Radar echoes are first collected from horizontally and vertically distributed sub-arrays that emulate a planar aperture. Each sub-array image is independently reconstructed using 3DWTV, which enforces spatial sparsity to suppress noise while preserving structural details. The horizontal and vertical images are then multiplicatively fused to jointly recover azimuth and elevation information. To reduce diffraction-induced blurring, LR deconvolution models system degradation through the Point Spread Function (PSF) and iteratively refines scene reflectivity, thereby enhancing cross-range resolution. Finally, 3DWT decomposes the images into multi-scale sub-bands (e.g., LLL, LLH, LHL), which are selectively fused using absolute-maximum and fuzzy-logic rules. The inverse wavelet transform is then applied to reconstruct the final 3D image, retaining both global and local features. Results and Discussions The proposed method is evaluated through both simulations and real-world experiments using a Stepped-Frequency Continuous-Wave (SFCW) radar operating from 1.6 to 2.2 GHz with a 2Tx–4Rx configuration. In simulations, compared with baseline algorithms such as Back-Projection (BP) and the Fast Iterative Shrinkage-Thresholding Algorithm (FISTA), the proposed method achieves better performance. Image Entropy (IE) decreases from 9.7125 for BP and 9.7065 for FISTA to 8.0711 , which reflects improved image quality. Experimental tests conducted in indoor environments further confirm robustness. For both standing and sitting postures, IE is reduced from 9.9982 to 7.0030 and from 9.9947 to 6.2261 , respectively. Conclusions This study presents a low-cost, high-resolution 3D imaging method for TWR systems based on array stitching. By integrating 3DWTV reconstruction, LR deconvolution, and 3DWT fusion, the method effectively reconstructs concealed human postures using a limited aperture. The approach simplifies hardware design, reduces system complexity, and preserves imaging quality under sparse sampling, thereby providing a practical solution for portable and scalable TWR systems.
Available online , doi: 10.11999/JEIT250503
Abstract:
Objective The rapid proliferation of Internet of Things (IoT) devices and the enforcement of data privacy regulations, including the General Data Protection Regulation (GDPR) and the Personal Information Protection Act, have positioned Federated Unlearning (FU) as a critical mechanism to safeguard the “right to be forgotten” in Edge Computing (EC). Existing class-level unlearning approaches often adopt uniform model pruning strategies. However, because edge nodes vary substantially in computational capacity, storage, and network bandwidth, these methods suffer from efficiency degradation, leading to imbalanced training delays and decreased resource utilization. This study proposes FU with Adaptive Model Pruning (FunAMP), a framework that minimizes training time while reliably eliminating the influence of target-class data. FunAMP dynamically assigns pruning ratios according to node resources and incorporates a parameter correlation metric to guide pruning decisions. In doing so, it addresses the challenge of resource heterogeneity while preserving compliance with privacy regulations. Methods The proposed framework establishes a quantitative relationship among model training time, node resources, and pruning ratios, on the basis of which an optimization problem is formulated to minimize overall training time. To address this problem, a greedy algorithm (Algorithm 2) is designed to adaptively assign appropriate pruning ratios to each node. The algorithm discretizes the pruning ratio space and applies a binary search strategy to balance computation and communication delays across nodes. Additionally, a Term Frequency–Inverse Document Frequency (TF–IDF)-based metric is introduced to evaluate the correlation between model parameters and the target-class data. For each parameter, the TF score reflects its activation contribution to the target class, whereas the IDF score measures its specificity across all classes. Parameters with high TF–IDF scores are iteratively pruned until the assigned pruning ratio is satisfied, thereby ensuring the effective removal of target-class data. Results and Discussions Simulation results confirm the effectiveness of FunAMP in balancing training efficiency and unlearning performance under resource heterogeneity. The effect of pruning granularity on model accuracy (Fig. 2 ): fine granularity (e.g., 0.01) preserves model integrity, whereas coarse settings degrade accuracy due to excessive parameter removal. Under fixed training time, FunAMP consistently achieves higher accuracy than FunUMP and Retrain (Fig. 3 ), as adaptive pruning ratios reduce inter-node waiting delays. For instance, FunAMP attains 76.48% accuracy on LeNet and 83.60% on AlexNet with FMNIST, outperforming baseline methods by 5.91% and 4.44%, respectively. The TF–IDF-driven pruning mechanism fully removes contributions of target-class data, achieving 0.00% accuracy on the target data while maintaining competitive performance on the remaining data (Table 2 ). Robustness under varying heterogeneity levels is further verified (Fig. 4 ). Compared with baselines, FunAMP markedly reduces the training time required to reach predefined accuracy and delivers up to 11.8× speedup across four models. These results demonstrate FunAMP’s capability to harmonize resource utilization, preserve model performance, and ensure unlearning efficacy in heterogeneous edge environments. Conclusions To mitigate training inefficiency caused by resource heterogeneity in FU, this study proposes FunAMP, a framework that integrates adaptive pruning with parameter relevance analysis. A system model is constructed to formalize the relationship among node resources, pruning ratios, and training time. A greedy algorithm dynamically assigns pruning ratios to edge nodes, thereby minimizing global training time while balancing computational and communication delays. Furthermore, a TF–IDF-driven metric quantifies the correlation between model parameters and target-class data, enabling the selective removal of critical parameters to erase target-class contributions. Theoretical analysis verifies the stability and reliability of the framework, while empirical results demonstrate that FunAMP achieves complete removal of target-class data and sustains competitive accuracy on the remaining classes. This work is limited to single-class unlearning, and extending the approach to scenarios requiring the simultaneous removal of multiple classes remains an important direction for future research.
Available online , doi: 10.11999/JEIT250343
Abstract:
Objective The coupled dynamics of the pantograph–catenary system are a critical determinant of current collection stability and the overall operational efficiency of high-speed trains. This study proposes an active control strategy that addresses complex operating conditions to mitigate fluctuations in pantograph–catenary contact force. Conventional approaches face inherent limitations: model-free Reinforcement Learning (RL) suffers from low sample efficiency and a tendency to converge to local optima, while Model Predictive Control (MPC) is constrained by its short optimization horizon. To integrate their complementary advantages, this paper develops a Reinforcement Learning-guided Model Predictive Control (RL-GMPC) algorithm for active pantograph control. The objective is to design a controller that combines the long-term planning capability of RL with the online optimization and constraint-handling features of MPC. This hybrid framework is intended to overcome the challenges of sample inefficiency, short-sighted planning, and limited adaptability, thereby achieving improved suppression of contact force fluctuations across diverse operating speeds and environmental disturbances. Methods A finite element model of the pantograph–catenary system is established, in which a simplified three-mass pantograph model is integrated with nonlinear catenary components to simulate dynamic interactions. The reinforcement learning framework is designed with an adaptive latent dynamics model to capture system behavior and a robust reward estimation module to normalize multi-scale rewards. The RL-GMPC algorithm is formulated by combining MPC for short-term trajectory optimization with a terminal state value function for estimating long-term cumulative rewards, thus balancing immediate and future performance. A Markov decision process environment is constructed by defining the state variables (pantograph displacement, velocity, acceleration, and contact force), the action space (pneumatic lift force adjustment), and the reward function, which penalizes contact force deviations and abrupt control changes. Results and Discussions Experimental validation under Beijing–Shanghai line conditions demonstrates significant reductions in contact force standard deviations: 14.29%, 18.07%, 21.52%, and 34.87% at 290, 320, 350, and 380 km/h, respectively. The RL-GMPC algorithm outperforms conventional H∞ control and Proximal Policy Optimization (PPO) by generating smoother control inputs and suppressing high-frequency oscillations. Robustness tests under 20% random wind disturbances show a 30.17% reduction in contact force variations, confirming adaptability to dynamic perturbations. Cross-validation with different catenary configurations (Beijing–Guangzhou and Beijing–Tianjin lines) reveals consistent performance improvements, with deviations reduced by 19.31%–33.62% across speed profiles. Training efficiency analysis indicates that RL-GMPC requires 57% fewer interaction samples than PPO to achieve convergence, demonstrating superior sample efficiency. Conclusions The RL-GMPC algorithm integrates the predictive capabilities of model-based control with the adaptive learning strengths of reinforcement learning. By dynamically optimizing pantograph posture, it enhances contact stability across varying speeds and environmental disturbances. Its demonstrated robustness to parameter variations and external perturbations highlights its practical applicability in high-speed railway systems. This study establishes a novel framework for improving pantograph–catenary interaction quality, reducing maintenance costs, and advancing the development of next-generation high-speed trains.
Available online , doi: 10.11999/JEIT250226
Abstract:
Objective Electric vehicle battery pack fault diagnosis is challenged by diverse operating conditions, the scarcity of fault data, and the domain shift caused by the non-Gaussian distribution of battery features. Conventional fault diagnosis methods struggle to address multiple fault types, lack the capability for fault isolation, and fail to account for distribution shifts between training and test data. Domain adaptation approaches enable robust multi-fault diagnosis across operating conditions without relying on accurate cell models or abundant labeled data. However, current methods remain limited. (1) They typically assume that aligning global and fine-grained subdomain distributions is equally important, which may not hold in practice. (2) Knowledge transfer cannot be fully achieved by aligning only low-order statistical features; higher-order statistical features are needed to capture the non-Gaussian characteristics of battery discharge profiles. To address these issues, a method is proposed in which global domains and subdomains are dynamically aligned while higher-order statistical moments are extracted to represent complex non-Gaussian distributions, thereby achieving fine-grained domain alignment and effective knowledge transfer. Methods This study proposes a dynamic distribution adaptation method with higher-order moment matching for multi-fault diagnosis of battery packs. The approach consists of three components: (1) Dynamic distribution adaptation. A feature extractor based on a one-dimensional convolutional network with residual connectivity and a multilayer perceptron classifier is constructed. The global distributions of source and target domains are aligned using Maximum Mean Discrepancy (MMD), while subdomain distributions of similar faults are aligned using Local Maximum Mean Discrepancy (LMMD). A dynamic factor is introduced to automatically adjust the relative weights of global and local alignment according to the inter-domain discrepancy, thereby adapting to distribution shifts under different operating conditions. (2) Higher-order moment matching. To address the non-Gaussian characteristics of battery data, higher-order statistical moment matching is incorporated into MMD. Computational complexity in high-dimensional tensors is reduced by random sampling, which enables fine-grained domain alignment across multi-order statistics and enhances the transferability of non-Gaussian distribution features. (3) Multi-fault diagnosis with domain adaptation. Experimental data from three standard vehicle operating conditions are used to jointly optimize classification loss and domain adaptation loss. This enables the diagnosis of multiple faults, including internal short circuit, sensor drift/noise, and battery inconsistency, across operating conditions while reducing reliance on manual annotation. By dynamically integrating global and local feature alignment, the method improves generalization performance under complex operating conditions and non-Gaussian distribution scenarios. Results and Discussions Systematic experiments validate the superiority of the proposed dynamic distribution adaptation with higher-order moment matching for multi-fault diagnosis in electric vehicle battery packs. As shown in Table 3 , the results from six transfer tasks under three operating conditions demonstrate that the proposed method achieves an average F1 score of 95%, which is 13.3% higher than that of the best-performing baseline model (DSAN). The confusion matrix in Fig. 6 indicates that the method achieves the lowest misclassification rate in distinguishing similar faults. Feature visualization results (Fig. 7 ) show that the method effectively reduces cross-domain feature distances of similar faults by dynamically adjusting the weights of global and local distribution alignment. Moreover, it successfully captures non-Gaussian discharge characteristics through higher-order moment matching, thereby achieving fine-grained domain adaptation. In terms of efficiency, the proposed method attains an average diagnosis time of 0.404 3 seconds (Table 4 ), satisfying real-time on-board application requirements. Nonetheless, optimization of computational resource consumption remains necessary for deployment on edge devices. Importantly, the method does not require labeled data from the target domain and overcomes the generalization bottleneck of traditional methods under domain shift and non-Gaussian conditions. However, some cross-domain features (Fig. 7 ) are not completely overlapped, and lightweight model design is still required for practical implementation on edge devices. Conclusions The battery pack is recognized as a critical component of electric vehicles, and reliable multi-fault diagnosis is regarded as essential for safe operation. Considering the unknown and diverse nature of real operating conditions, fault diagnosis is investigated across three driving cycles: UDDS, FUDS, and US06. A dynamic distribution adaptation with higher-order moment matching (DDAMD) is proposed for diagnosing multiple faults in series-connected battery packs. The method dynamically evaluates the relative importance of conditional and marginal distributions to align source and target domains, while non-Gaussian features from charge–discharge curves are effectively extracted for fine-grained alignment. Experimental results across six transfer tasks confirm that DDAMD achieves the highest diagnostic performance. Detailed analyses present diagnostic accuracy for each fault type as well as the diagnostic speed, while feature visualization further improves interpretability by demonstrating how the algorithm extracts domain-invariant and discriminative fault features across domains. Future research will extend this work in two directions: (1) incorporating additional operating conditions and a broader set of fault categories, and (2) exploring transfer tasks from simulation to real-world applications to facilitate data acquisition and labeling.
Available online , doi: 10.11999/JEIT250220
Abstract:
Objective Multivariate time series data, characterized by their high dimensionality and temporal dynamics, are widely generated across diverse application domains, including healthcare monitoring, industrial sensor networks, and autonomous systems. However, these data are often subject to severe missingness caused by sensor malfunctions, transmission errors, or environmental disturbances, which obscures critical spatiotemporal patterns and hinders downstream analytical tasks such as anomaly detection, predictive maintenance, and decision support. Existing imputation methods, ranging from statistical approaches to machine learning models, are primarily tailored to low missing-rate scenarios. When applied to high missing-rate conditions, they face challenges such as gradient vanishing during model training, insufficient capture of spatiotemporal dependencies, and limited ability to represent complex nonlinear features, with performance deteriorating sharply as the missing rate increases. To address these limitations, this study proposes the Spatial Self-Attention Incorporated Imputation algorithm (SSAImpute), designed to enhance imputation performance specifically under severely missing conditions. Methods The proposed SSAImpute algorithm adopts a dual-branch Siamese architecture with adversarial fusion. Each branch comprises two core modules: a spatial self-attention–aware module and a subsequent temporal self-attention encoding module. The spatial self-attention–aware module constructs a dynamic adjacency matrix from the geolocations of data sources to explicitly quantify inter-variable spatial relationships. These spatial dependencies are then integrated with temporal features to strengthen sequence correlation modeling and enrich feature representations with embedded spatial information. The temporal self-attention encoding module employs a multi-dimensional residual attention mechanism with bidirectional temporal dependency learning. A missing-aware positional encoding scheme and a mask-adaptive self-attention mechanism are incorporated to effectively capture temporal dependencies and feature correlations, thereby mitigating severe missingness and alleviating the vanishing gradient problem. The two Siamese branches are fused through adversarial learning and dynamic weighting, which jointly refine the final imputation results. To evaluate the performance of SSAImpute against competing methods, three conventional metrics are used: Mean Absolute Error (MAE), Root Mean Square Error (RMSE), and Mean Relative Error (MRE). Results and Discussions Extensive experiments are conducted on four public datasets—Inter-Sensor, PeMS04, PeMS07, and PeMS11—in comparison with seven state-of-the-art time series imputation models: Mean, Median, K-Nearest Neighbor (KNN), Multi-directional Recurrent Neural Network (M-RNN), Bidirectional Recurrent Imputation for Time Series (BRITS), Transformer, and Self-Attention-based Imputation for Time Series (SAITS). The results show that the proposed method consistently improves imputation accuracy across all datasets, even under severe missingness. On the Inter-Sensor dataset, SSAImpute demonstrates superior performance compared with all competing methods. For all four time series, SSAImpute outperforms the others across all evaluation metrics, with improvements over the best-performing baseline (SAITS) of 15.9% in MAE, 0.19% in RMSE, and 16.6% in MRE for temperature; 11.1% in MAE, 1.7% in RMSE, and 11.7% in MRE for humidity; 9.8% in MAE, 10.2% in RMSE, and 24.3% in MRE for light; and 8.8% in MAE, 0.4% in RMSE, and 9.0% in MRE for voltage. On the PeMS datasets, SSAImpute also exceeds all competing methods across PeMS04, PeMS07, and PeMS11. The achieved MAE, RMSE, and MRE are 0.203, 0.328, and 22.4% for PeMS04; 0.153, 0.274, and 17.5% for PeMS07; and 0.180, 0.284, and 19.6% for PeMS11, respectively. The performance under different missing-ratio scenarios is further investigated. Although accuracy decreases exponentially with higher missingness, SSAImpute consistently outperforms the three strongest baselines. Visualization of the imputed time series further verifies its effectiveness, with reconstructed values closely aligned with the ground truth. These findings confirm the contributions of the spatial self-attention–aware module, the temporal self-attention encoding module, and the adversarial learning with dynamic weighting mechanism. Conclusions This study proposes a spatial self-attention–incorporated imputation method for severely missing multivariate time series data, built on a dual-branch Siamese framework. Each branch integrates a spatial self-attention–aware module, which incorporates geolocation information of the data source, followed by a temporal self-attention encoding mechanism to capture contextual dependencies. These modules jointly strengthen feature extraction of spatiotemporal dependencies, enabling more accurate reconstruction under high missingness. The proposed method provides a robust data foundation for downstream data-driven analysis and decision-making tasks in real-world applications.
Available online , doi: 10.11999/JEIT250303
Abstract:
Objective Graph Neural Networks (GNNs) achieve state-of-the-art performance in modeling complex graph-structured data and are increasingly applied in diverse domains. However, their vulnerability to adversarial attacks raises significant concerns for deployment in security-critical applications. Understanding and improving GNN robustness under adversarial conditions is therefore crucial to ensuring safe and reliable use. Among adversarial strategies, transfer-based black-box attacks have attracted considerable attention. Yet existing approaches face inherent limitations. First, they rely heavily on gradient information derived from surrogate models, while insufficiently exploiting critical structural cues embedded in graphs. This reliance often leads to overfitting to the surrogate, thereby reducing the transferability of adversarial samples. Second, most methods adopt a global perspective in perturbation selection, which hinders their ability to identify local substructures that decisively influence model predictions, ultimately resulting in suboptimal attack efficiency. Methods Motivated by the intrinsic structural characteristics of graph data, the latent association between information entropy and node vulnerability is investigated, and an entropy-guided adversarial attack framework is proposed. For homogeneous GNNs, a transferable black-box attack method, termed NEAttack, is designed. This method exploits node entropy to capture the structural complexity of node-level neighborhood subgraphs. By measuring neighborhood entropy, reliance on surrogate model gradients is reduced and perturbation selection is made more efficient. Based on this framework, the approach is further extended to heterogeneous graphs, leading to the development of GEHAttack, an entropy-based adversarial method that employs graph-level entropy to account for the semantic and relational diversity inherent in heterogeneous graph data. Results and Discussions The effectiveness and generalizability of the proposed methods are evaluated through extensive experiments on multiple datasets and model architectures. For homogeneous GNNs, NEAttack is assessed against six representative baselines on four datasets (Cora, CoraML, Citeseer, and PubMed) and three GNN models (Graph Convolutional Network (GCN), Graph Attention Network (GAT), Simplified Graph Convolution (SGC)). As reported in (Table 3 ) and (Table 4 ), NEAttack consistently outperforms existing approaches. In terms of accuracy, average improvements of 10.25%, 17.89%, 6.68%, and 12.6% are achieved on Cora, CoraML, Citeseer, and PubMed, respectively. For the F1-score, the corresponding gains are 9.41%, 16.83%, 6.21%, and 17.24%. Random Attack and Delete Internal, Connect External (DICE), which rely on randomness, exhibit stable but weak transferability, leading to only minor reductions in model performance. Meta-Self and Projected Gradient Descent (PGD) generate effective adversarial samples in white-box scenarios but show poor transfer performance due to overfitting to surrogate models. AtkSE and GraD perform better but remain affected by overfitting, while their computational cost increases sharply with data scale. For heterogeneous GNNs, GEHAttack is compared with four baselines on three datasets (ACM, IMDB, and DBLP) and six Heterogeneous Graph Neural Network (HGNN) models (Heterogeneous Graph Attention Network (HAN), Heterogeneous Graph Transformer (HGT), Simple Heterogeneous Graph Neural Network (SimpleHGN), Relational Graph Convolutional Network (RGCN), Robust Heterogeneous (RoHe), and Fast Robust Heterogeneous Graph Convolutional Network (FastRo-HGCN)). As shown in (Table 5 and Table 6 ), GEHAttack exhibits clear advantages. On the ACM dataset, compared with the HG Baseline, GEHAttack improves the average Micro-F1 and Macro-F1 scores of HAN, HGT, SimpleHGN, and RGCN by 3.93% and 3.46%, respectively. On the more robust RoHe and FastRo models, the corresponding improvements are 2.75% and 1.65%. Similar improvements are also observed on the IMDB and DBLP datasets, confirming the robustness and transferability of GEHAttack. Conclusions This study presents a unified entropy-oriented adversarial attack framework for both homogeneous and heterogeneous GNNs in black-box transfer settings. By leveraging the relationship between entropy and structural vulnerability, the proposed NEAttack and GEHAttack methods address the key limitations of gradient-dependent approaches and enable more efficient perturbation generation. Extensive evaluations across diverse datasets and models demonstrate their superiority in both performance and adaptability, providing new insights into advancing adversarial robustness research on graph-structured data.
Available online , doi: 10.11999/JEIT250667
Abstract:
Objective With the growing number of operational satellites in orbit, Space Situation Awareness (SSA) has become a critical capability for ensuring the safety of space operations. Traditional ground-based radar and optical systems face inherent limitations in tracking deep-space objects due to atmospheric interference and orbital obscuration. Therefore, spaceborne Inverse Synthetic Aperture Radar (ISAR) has emerged as a pivotal technology for on-orbit target characterization, offering all-weather, long-duration observation. However, higher-order Three-Dimensional (3D) spatial-variant range migration and phase errors, caused by the complex relative motion between a spaceborne ISAR platform and its target, can seriously degrade imaging quality. Meanwhile, conventional Two-Dimensional (2D) Range–Doppler (RD) imaging provides valuable intensity distributions of scattering points but remains a projection of the target’s 3D structure. The absence of geometric information limits accurate attitude estimation and collision risk assessment. To address these challenges and achieve more comprehensive SSA, this paper proposes a joint space target imaging and attitude estimation algorithm. Methods This paper proposes a joint space target imaging and attitude estimation algorithm composed of three main components: space target imaging characterization, high-resolution imaging, and attitude estimation. First, the imaging characteristics of satellite targets are analyzed to establish the mapping relationship between the image domain and the Doppler parameters of individual scattering points. Second, adaptive segmentation in the two-dimensional (2D) image domain combined with high-precision regional compensation is applied to obtain high-resolution imaging results. Finally, the spatial distribution characteristics of the Doppler parameters are exploited to derive an explicit expression for the second-order Doppler parameters and to estimate the planar component attitude of the target, such as that of the solar wing. Results and Discussions The proposed SSA method achieves high-resolution imaging even in the presence of orbital error and complex 3D spatial-variant Doppler error. Moreover, target attitude estimation can be performed without the need for rectangular component extraction. The effectiveness of the algorithm is verified through three simulation experiments. When the target adopts different attitudes, the method successfully produces both high-resolution imaging results and accurate target attitude estimation (Fig. 7 , Fig. 8 ). To further evaluate performance, comparative simulations are conducted (Fig. 9 , Fig. 10 ). In addition, a method for estimating the long- and short-edge pointing of the satellite solar wing is presented in Section 3.3. The effectiveness of the proposed high-precision imaging algorithm for spinning targets is analyzed in Section 3.4, where the third simulation demonstrates the extended SSA capability of the algorithm (Fig. 11 , Fig. 12 ). Conclusions This paper proposes a joint high-resolution imaging and attitude estimation algorithm to address the situational awareness requirements of highly dynamic Doppler space targets. First, the imaging characteristics of satellite targets and the mapping relationship between scattering points and higher-order Doppler parameters are derived. Second, an adaptive region segmentation algorithm is developed to compensate for 3D spatial-variant errors, thereby significantly enhancing imaging resolution. Meanwhile, an explicit correlation between Doppler parameters and satellite attitude is established based on the characteristics of planar components. Simulation results under different imaging conditions confirm the validity and reliability of the algorithm. Compared with conventional approaches, the proposed method achieves joint compensation of orbital and rotational errors. Furthermore, the attitude estimation process does not require rectangular component segmentation and remains effective even when rectangular components are partially obscured.
Available online , doi: 10.11999/JEIT250386
Abstract:
Objective In Word Sense Disambiguation (WSD), the Linguistically-motivated bidirectional Encoder Representation from Transformer (LERT) is employed to capture rich semantic representations from large-scale corpora, enabling improved contextual understanding of word meanings. However, several challenges remain. Current WSD models are not sufficiently sensitive to temporal and spatial dependencies within sequences, and single-dimensional features are inadequate for representing the diversity of linguistic expressions. To address these limitations, a hybrid network is constructed by integrating LERT, Bidirectional Gated Recurrent Units (Bi-GRU), and Graph Convolutional Network (GCN). This network enhances the modeling of structured text and contextual semantics. Nevertheless, generalization and robustness remain problematic. Therefore, an adversarial training algorithm is applied to improve the overall performance and resilience of the WSD model. Methods An adversarial WSD method is proposed based on a pre-trained model, combining Bi-GRU and GCN. First, word forms, parts of speech, and semantic categories of the neighboring words of an ambiguous term are input into the LERT model to obtain the CLS sequence and token sequence. Second, cross-attention is applied to fuse the global semantic information extracted by Bi-GRU from the token sequence with the local semantic information derived from the CLS sequence. Sentences, word forms, parts of speech, and semantic categories are then used as nodes to construct a disambiguation feature graph, which is subsequently input into GCN to update the feature information of the nodes. Third, the semantic category of the ambiguous word is determined through the interpolated prediction layer and semantic classification layer. Fourth, subtle continuous perturbations are generated by computing the gradient of the dynamic word vectors in the input. These perturbations are added to the original word vector matrix to create adversarial samples, which are used to optimize the LERT+Bi-GRU+CA+GCN (LBGCA-GCN) model. A cross-entropy loss function is applied to measure the performance of the LBGCA-GCN model on adversarial samples. Finally, the loss from the network is combined with the loss from AT to optimize the LBGCA-GCN model.. Results and Discussions When the FreeLB algorithm is applied, stronger adversarial perturbations are generated, and the LBGCA-GCN-AT model achieves the best performance (Table 2 ). As the number of perturbation steps increases, the strength of AT improves. However, when the number of steps exceeds a certain threshold, the LBGCA-GCN+AT(LBGCA-GCN-AT) model begins to overfit. The Free Large-Batch (FreeLB) algorithm demonstrates strong robustness with three perturbation steps (Table 3 ). The cross-attention mechanism, which fuses the token sequence with the CLS sequence, yields significant performance gains in complex semantic scenarios (Fig. 3 ). By incorporating AT, the LBGCA-GCN-AT model achieves notable improvements across multiple evaluation metrics (Table 4 ). Conclusions This study presents an adversarial WSD method based on a pre-trained model, integrating Bi-GRU and GCN to address the weak generalization ability and robustness of conventional WSD models. LERT is used to transform discriminative features into dynamic word vectors, while cross-attention fuses the global semantic information extracted by Bi-GRU from the token sequence with the local semantic information derived from the CLS sequence. This fusion generates more complete node representations for the disambiguation feature graph. A GCN is then applied to update the relationships among nodes within the feature graph. The interpolated prediction layer and semantic classification layer are used to determine the semantic category of ambiguous words. To further improve robustness, the gradient of the dynamic word vector is computed and perturbed to generate adversarial samples, which are used to optimize the LBGCA-GCN model. The network loss is combined with the AT loss to refine the model. Experiments conducted on the SemEval-2007 Task #05 and HealthWSD datasets examine multiple factors affecting model performance, including adversarial algorithms, perturbation steps, and sequence fusion methods. Results demonstrate that introducing AT improves the model’s ability to handle real-world noise and perturbations. The proposed method not only enhances robustness and generalization but also strengthens the capacity of WSD models to capture subtle semantic distinctions.
Available online , doi: 10.11999/JEIT250657
Abstract:
Objective In recent years, diversified user demands, dynamic application scenarios, and massive data transmissions have imposed increasingly stringent requirements on modern networks. Network schedulers play a critical role in ensuring efficient and reliable data delivery, enhancing overall performance and stability, and directly shaping user-perceived service quality. Traditional scheduling algorithms, however, rely largely on fixed hardware, with scheduling logic hardwired during chip design. These designs are inflexible, provide coarse and static scheduling granularity, and offer limited capability to represent complex policies. Therefore, they hinder rapid deployment, increase upgrade costs, and fail to meet the evolving requirements of heterogeneous and large-scale network environments. Programmable schedulers, in contrast, leverage flexible hardware architectures to support diverse strategies without hardware replacement. Scheduling granularity can be dynamically adjusted at the flow, queue, or packet level to meet varied application requirements with precision. Furthermore, they enable the deployment of customized logic through data plane programming languages, allowing rapid iteration and online updates. These capabilities significantly reduce maintenance costs while improving adaptability. The combination of high flexibility, cost-effectiveness, and engineering practicality positions programmable schedulers as a superior alternative to traditional designs. Therefore, the design and optimization of high-performance programmable schedulers have become a central focus of current research, particularly for data center networks and industrial Internet applications, where efficient, flexible, and controllable traffic scheduling is essential. Methods The primary objective of current research is to design universal, high-performance programmable schedulers. Achieving simultaneous improvements across multiple performance metrics, however, remains a major challenge. Hardware-based schedulers deliver high performance and stability but incur substantial costs and typically support only a limited range of scheduling algorithms, restricting their applicability in large-scale and heterogeneous network environments. In contrast, software-based schedulers provide flexibility in expressing diverse algorithms but suffer from inherent performance constraints. To integrate the high performance of hardware with the flexibility of software, recent designs of programmable schedulers commonly adopt First-In First-Out (FIFO) or Push-In First-Out (PIFO) queue architectures. These approaches emphasize two key performance metrics: scheduling accuracy and programmability. Scheduling accuracy is critical, as modern applications such as real-time communications, online gaming, telemedicine, and autonomous driving demand strict guarantees on packet timing and ordering. Even minor errors may result in increased latency, reduced throughput, or connection interruptions, compromising user experience and service reliability. Programmability, by contrast, enables network devices to adapt to diverse scenarios, supporting rapid deployment of new algorithms and flexible responses to application-specific requirements. Improvements in both accuracy and programmability are therefore essential for developing efficient, reliable, and adaptable network systems, forming the basis for future high-performance deployments. Results and Discussions The overall packet scheduling process is illustrated in (Fig. 1 ), where scheduling is composed of scheduling algorithms and schedulers. At the ingress or egress pipelines of end hosts or network devices, scheduling algorithms assign a Rank value to each packet, determining the transmission order based on relative differences in Rank. Upon arrival at the traffic manager, the scheduler sorts and forwards packets according to their Rank values. Through the joint operation of algorithms and schedulers, packet scheduling is executed while meeting quality-of-service requirements. A comparative analysis of the fundamental principles of FIFO and PIFO scheduling mechanisms (Fig. 2 ) highlights their differences in queue ordering and disorder control. At present, most studies on programmable schedulers build upon these two foundational architectures (Fig. 3 ), with extensions and optimizations primarily aimed at improving scheduling accuracy and programmability. Specific strategies include admission control, refinement of scheduling algorithms, egress control, and advancements in data structures and queue mechanisms. On this basis, the current research progress on programmable schedulers is reviewed and systematically analyzed. Existing studies are compared along three key dimensions: structural characteristics, expressive capability, and approximation accuracy (Table 1 ). Conclusions Programmable schedulers, as a key technology for next-generation networks, enable flexible traffic management and open new possibilities for efficient packet scheduling. This review has summarized recent progress in the design of programmable schedulers across diverse application scenarios. The background and significance of programmable schedulers within the broader packet scheduling process were first clarified. An analysis of domestic and international literature shows that most current studies focus on FIFO-based and PIFO-based architectures to improve scheduling accuracy and programmability. The design approaches of these two architectures were examined, the main technical methods for enhancing performance were summarized, and their structural characteristics, expressive capabilities, and approximation accuracy were compared, highlighting respective advantages and limitations. Potential improvements in existing research were also identified, and future development directions were discussed. Nevertheless, the design of a universal, high-performance programmable scheduler remains a critical challenge. Achieving optimal performance across multiple metrics while ensuring high-quality network services will require continued joint efforts from both academia and industry.
Available online , doi: 10.11999/JEIT250589
Abstract:
Objective Small targets such as unmanned aerial vehicles and unmanned vessels, which exhibit small Radar Cross Section (RCS) values and weak echoes, are difficult to detect due to their low observability. Traditional Constant False Alarm Rate (CFAR) detection is typically represented by the Cell-Averaged (CA) CFAR method, in which the detection threshold is determined by the statistical power parameter of the signal. However, its detection performance is constrained by the Signal-to-Noise Ratio (SNR). This study focuses on how to exploit and apply signal features beyond power parameters to achieve CFAR detection under lower SNR conditions. Methods After pulse compression, the envelope of a Linear Frequency Modulation (LFM) signal exhibits sinc characteristics, whereas noise retains its random nature. This difference can be used to distinguish target echoes from non-target signals. On this basis, we propose a constant false alarm detection method based on signal feature matching. First, both the ideal echo signal and the actual echo signal are processed with sliding windows of equal length to generate an ideal sample and a set of test samples. A dual-port fully connected neural network is then constructed to extract the deep feature matching degree between the ideal sample and the test samples. Finally, the constant false alarm threshold is obtained by numerically calculating the deep feature matching parameter from a large number of non-target samples compared with the standard sample. Results and Discussions Several sets of simulation experiments are carried out, and measured radar data from different frequency bands are applied to verify the effectiveness of the proposed method. The simulations first confirm that the method maintains stable constant false alarm characteristics (Table 1 ). The detection performance is then compared with traditional CA-CFAR detection, machine learning approaches, and other deep learning methods. The results indicate that, relative to CA-CFAR detection, the proposed method achieve 2–5 dB gain in equivalent SNR across different false alarm probabilities (Fig. 4 ). Under mismatched SNR conditions, the method continues to demonstrate robust detection performance with strong generalization capability (Fig. 5 ). In the processing of measured X-band radar data, the proposed method detects targets that CA-CFAR fails to identify, extending the detection range to 740 distance units, compared with 562 distance units for CA-CFAR, corresponding to an improvement of approximately 28.72% in radar detection capability (Fig. 7 , 8 ). In the case of S-band radar data, the proposed method significantly reduces false alarms (Fig. 10 , 11 ). Conclusions This study exploits the difference between target and noise signal envelopes by introducing a feature extraction network that effectively enhances target detection performance. Comparative simulation experiments and the processing of measured radar data across different frequency bands demonstrate the following: (1) the proposed method markedly improves detection performance over traditional CA-CFAR detection, yielding a 2–5 dB gain in equivalent SNR; (2) under mismatched SNR conditions, the method shows strong generalization capability, achieving better detection performance than other deep learning and machine learning approaches; (3) in X-band radar data processing, the method increases detection capability by approximately 28.72%; and (4) in S-band radar data processing, it significantly reduces false alarms. Future work will focus on accelerating the detection process to further improve efficiency.
Available online , doi: 10.11999/JEIT250078
Abstract:
Objective The exponential growth of 6G wireless communication demands has positioned the Space-Air-Ground Integrated Network (SAGIN) as a promising architecture, aiming to achieve broad coverage and adaptive networking. However, complex geographic environments, including building obstructions, frequently hinder direct communication between ground users and base stations, thereby requiring effective relay strategies to maintain reliability. Reconfigurable Intelligent Surfaces (RIS) have attracted considerable attention for their capacity to improve signal coverage through passive beamforming. This study develops an RIS-assisted SAGIN architecture incorporating aerial RIS clusters and High-Altitude Platforms (HAPS) to enable communication between ground users and a Low Earth Orbit (LEO) satellite. To enhance energy efficiency, the system further optimizes user relay selection, power allocation, and beamforming for both LEO and RIS components. Methods The proposed system integrates LEO satellites, HAPS, Unmanned Aerial Vehicles (UAVs) equipped with RIS, and ground users within a three-dimensional communication space. Due to environmental obstructions, ground users are unable to maintain direct links with base stations; instead, RIS functions as a passive relay node. To improve relay efficiency, users are grouped and associated with specific RIS units. The total system bandwidth is partitioned into sub-channels assigned to different user groups. A matching algorithm is designed for user selection, followed by user group association with each RIS. For LEO communications, HAPS serve as active relay nodes that decode and forward signals to ground base stations. The system considers both direct and RIS-assisted communication links. An optimization problem is formulated to maximize energy efficiency under constraints related to user Quality of Service (QoS), power allocation, and beamforming for both LEO and RIS. To solve this, the proposed Alternating Pragmatic Iterative Algorithm in SAGIN (APIA-SAGIN) decomposes the problem into three sub-tasks: user relay selection, LEO beamforming, and RIS beamforming. The Successive Convex Approximation (SCA) and SemiDefinite Relaxation (SDR) methods are employed to transform the original non-convex problem into tractable convex forms for efficient solution.g. Results and Discussions Simulation results confirm the effectiveness of the proposed APIA-SAGIN algorithm in optimizing the energy efficiency of the RIS-assisted SAGIN. As shown in (Fig. 5 ), increasing the number of RIS elements and LEO antennas markedly improves energy efficiency compared with the random phase shift algorithm. This demonstrates that the proposed algorithm enables channel-aware control by aligning RIS beamforming with the ground transmission channel and jointly optimizing LEO beamforming, RIS beamforming, and LEO-channel alignment. As illustrated in (Fig. 6 ), both energy efficiency and the achievable rate of the LEO link increase with transmission power. However, beyond a certain power threshold, energy consumption rises faster than the achievable rate, leading to diminishing or even negative returns in energy efficiency. (Fig. 7 ) shows that higher power in ground user groups leads to increased achievable rates. Nonetheless, expanding the number of RIS elements proves more effective than increasing transmission power for enhancing user throughput. As shown in (Fig. 8 ), a higher number of RIS elements leads to simultaneous improvements in energy efficiency and achievable rate in the ground segment. Moreover, increasing the number of ground users does not degrade energy efficiency; instead, it results in a gradual increase, suggesting efficient resource allocation. Compared with the random phase shift algorithm, the proposed approach achieves superior performance in both energy efficiency and achievable rate. These findings support its potential for practical deployment in SAGIN systems. Conclusions This study proposes an RIS-assisted SAGIN architecture that utilizes aerial RIS clusters and HAPS to support communication between ground users and LEO satellites. The APIA-SAGIN algorithm is developed to jointly optimize user relay selection, LEO beamforming, and RIS beamforming with the objective of maximizing system energy efficiency. Simulation results demonstrate the effectiveness and robustness of the algorithm under complex conditions. The proposed approach offers a promising direction for improving the energy efficiency and overall performance of SAGIN, providing a foundation for future research and practical implementation.
Available online , doi: 10.11999/JEIT250160
Abstract:
Objective The rapid expansion of Decentralized Finance (DeFi) has been accompanied by a rise in fraudulent activities, with Rug Pull scams posing a significant threat to the security, stability, and credibility of blockchain ecosystems. Due to the permissionless and decentralized nature of DeFi platforms, malicious actors can exploit smart contracts to deceive investors, artificially inflate token prices, and withdraw liquidity abruptly, leaving investors with worthless assets. The anonymous and pseudonymous characteristics of blockchain transactions further hinder fraud detection and regulatory oversight, making Rug Pull scams one of the most challenging forms of financial fraud in the DeFi sector. Although traditional fraud detection approaches, such as rule-based heuristics and statistical analysis, provide basic risk assessment, they often fail to capture the complex transaction patterns, dynamic interactions, and heterogeneous relationships within blockchain networks. To address these limitations, this study proposes Heterogeneous graph Neural Network for Rug Pull detection (HNN4RP), a fraud detection framework based on Heterogeneous Graph Neural Networks (GNNs), specifically designed for the early identification of Rug Pull scams. By leveraging the graph structure of blockchain transactions, HNN4RP models Ethereum transaction data as a heterogeneous graph to capture the relationships among smart contracts, liquidity pools, and trader addresses. The framework integrates advanced representation learning techniques to reveal hidden dependencies, detect anomalous patterns, and differentiate between legitimate and fraudulent behaviors in a scalable, data-driven manner. Furthermore, HNN4RP incorporates temporal dynamics and contextual information to adapt to evolving fraud tactics. Methods HNN4RP models Ethereum transactions as a heterogeneous graph, distinguishing between regular nodes and smart contract nodes while preserving both structured and unstructured transactional data. By leveraging a graph-based representation, the model captures complex interactions within the Ethereum network, supporting comprehensive analysis of transactional behavior. This approach explicitly represents key relationships between entities, including token transfers, contract interactions, and liquidity movements, thereby facilitating more accurate fraud detection.The core components of HNN4RP include a Random Walk with Restart (RWR) sampling mechanism, which mitigates biases caused by skewed transaction distributions and enables balanced exploration of node neighborhoods. This technique captures long-range dependencies in the transaction network while preserving the local structural context, which is essential for detecting anomalous behaviors associated with fraud. By dynamically adjusting the probability of revisiting specific nodes, RWR improves the model’s focus on relevant transactional pathways, reducing the effects of data sparsity and imbalance.In addition to RWR-based sampling, HNN4RP incorporates multi-modal feature encoding to capture both structured transactional relationships and unstructured node attributes, such as smart contract code and token metadata. This integration enables the model to leverage a diverse set of informative features, improving its ability to differentiate between legitimate and fraudulent activities. By encoding both numerical and textual representations of transaction data, the framework enhances the robustness of fraud detection against evasive tactics employed by malicious actors.Furthermore, HNN4RP employs a BiLSTM-based temporal fusion mechanism to retain the sequential dependencies within transaction histories, effectively modeling temporal behavioral patterns. This component is essential for capturing the evolution of fraudulent activities over time, as Rug Pull scams often exhibit time-dependent characteristics. By learning the progression of transactional patterns, the model enhances fraud classification accuracy and enables early detection of fraudulent schemes before they escalate. Through this comprehensive approach, HNN4RP provides a scalable, adaptive, and high-precision solution for fraud detection in decentralized financial ecosystems. Results and Discussions The performance of the proposed HNN4RP model is evaluated against three categories of baseline methods: attribute-based approaches, random walk-based algorithms, and deep learning models. Across all dataset scales, HNN4RP consistently outperforms these baselines across three predefined evaluation metrics, demonstrating superior fraud detection capability. Notably, on the D2 and D3 datasets, HNN4RP achieves an accuracy of 96% and an F1 score of 0.95 (Table 2 ). Ablation experiments indicate that both attribute-based features and textual representations contribute significantly to Rug Pull detection performance (Fig. 3 ). Parameter sensitivity analysis shows that the optimal neighborhood size is 16, and the best embedding dimension is 27 (Figs. 4 and 5 ). Further experiments incorporating different types of noise interference confirm that HNN4RP exhibits strong robustness to data perturbations, with the F1 score declining by no more than 7% under moderate noise levels (Table 3 ). Early fraud detection tests demonstrate that HNN4RP effectively identifies fraudulent activities at an early stage, providing reliable warning signals before scams fully develop (Table 4 ). Conclusions This study addresses the emerging challenge of Rug Pull scams in the DeFi and Web3 domains and proposes a deep learning-based detection model, HNN4RP, with significant implications for the stability and security of decentralized financial ecosystems. By formalizing the Rug Pull detection task using heterogeneous graph modeling, this work tackles three major challenges in Ethereum-based fraud detection: biased transaction exploration, incomplete feature representation, and insufficient temporal pattern recognition. These challenges are addressed through the integration of RWR-based random walks, heterogeneous node feature extraction, and BiLSTM-based temporal feature fusion. Experimental results on real Ethereum transaction datasets demonstrate that HNN4RP achieves 96% accuracy and provides reliable early warnings within four hours before fraudulent activities occur, confirming its practical applicability for early fraud detection in decentralized environments.
Available online , doi: 10.11999/JEIT250189
Abstract:
Objective With the evolution of wireless communication toward ultra-dense networks, optimizing spectrum efficiency in cell-free massive Multiple-Input Multiple-Output (MIMO) Non-Orthogonal Multiple Access (NOMA) systems faces the challenge of balancing algorithmic complexity and performance. Traditional user clustering methods, such as random clustering, exhibit high randomness and easily converge to suboptimal solutions, whereas exhaustive search is computationally prohibitive. Similarly, power allocation schemes with rigid fixed thresholds often fail to accommodate dynamic user demands, resulting in imbalanced resource utilization and reduced fairness. To address these limitations, this study proposes a low-complexity joint optimization algorithm. By collaboratively designing user clustering and power allocation, the algorithm maximizes the system’s sum spectrum efficiency while guaranteeing the quality of service for low-rate users, thereby offering an efficient resource allocation strategy for cell-free massive MIMO-NOMA systems. Methods A downlink sum spectrum efficiency maximization model is first constructed and decomposed into two sub-problems: user clustering and power allocation. A clustering algorithm based on cluster head selection and channel difference maximization is then proposed, which reduces the complexity of pairing searches by optimizing the selection of cluster heads. Based on the clustering results, a minimum-rate enhancement constraint mechanism is incorporated. The resulting non-convex power allocation problem is subsequently transformed into a convex optimization form using the Successive Convex Approximation (SCA) method. Results and Discussions The relationship between sum spectrum efficiency and the number of users under different clustering algorithms is shown in (Fig. 2 ). Under perfect Successive Interference Cancellation (SIC) conditions, the proposed algorithm achieves performance comparable to that of the statistical clustering algorithm, whereas the combined clustering algorithm yields the lowest efficiency. Under imperfect SIC, the proposed algorithm maintains the highest spectrum efficiency, while the performance of the statistical algorithm decreases. The sum spectrum efficiency is markedly reduced by imperfect SIC, particularly when the number of users is small. This reduction arises from insufficient elimination of intra-cluster interference, leading to increased residual interference. Notably, the NOMA system supports twice the user capacity of Orthogonal Multiple Access (OMA), confirming its superior spectrum resource utilization. The relationship between sum spectrum efficiency and the number of Access Points (APs) is shown in (Fig. 3 ). Spectrum efficiency improves substantially as the number of APs increases, owing to enhanced channel hardening and interference suppression. Under perfect SIC, both the proposed algorithm and the statistical clustering algorithm achieve similar performance, exceeding the combined algorithm. The advantage of the proposed algorithm is further demonstrated under imperfect SIC. Increasing the number of deployed APs strengthens anti-interference capability and expands user capacity, verifying the efficiency and robustness of the proposed clustering algorithm under both perfect and imperfect SIC conditions. The effect of intra-cluster user numbers on spectrum efficiency is evaluated in (Fig. 4 ). Spectrum efficiency increases with the number of APs, largely due to improved coverage and channel estimation accuracy. However, efficiency decreases significantly as intra-cluster user numbers increase, which is attributed to aggravated intra-cluster interference and constraints on power resource allocation. The convergence of the proposed algorithm is demonstrated in (Fig. 5 ), where the optimal solution is reached within approximately seven iterations. After power allocation optimization, the efficiency gap between imperfect and perfect SIC remains below 0.2 bit/(s·Hz). Compared with Full Power Control (FPC), the Proposed Power Control (PPC) scheme effectively mitigates residual interference and achieves performance close to perfect SIC under practical conditions. The relationship between sum spectrum efficiency and AP numbers with different antenna configurations is presented in (Fig. 6 ). Efficiency continuously improves with increasing AP numbers and per-AP antenna numbers, owing to stronger channel hardening effects. Across all AP configurations, the PPC scheme demonstrates clear advantages over FPC, with the benefits becoming more pronounced in densely deployed networks. Power allocation optimization further enhances efficiency as antenna numbers increase. Finally, the cumulative distribution of per-user spectrum efficiency under different power control schemes is illustrated in (Fig. 7 ). The PPC scheme substantially reduces the proportion of inefficient users (0～0.2 bit/(s·Hz)), thereby improving system fairness. By contrast, the FPC scheme performs slightly better in the high-efficiency region, but this advantage comes at the expense of user fairness. In user-intensive scenarios, the PPC scheme effectively balances system stability and fairness by ensuring minimum rates for weak users. Conclusions A low-complexity joint optimization algorithm is presented to address the challenge of spectrum efficiency optimization in cell-free massive MIMO-NOMA systems. Through theoretical analysis and simulation, the spectrum efficiency and computational complexity of the system are compared under different user clustering algorithms and power allocation schemes. The results show that the proposed clustering algorithm significantly enhances system performance across various AP deployments and antenna configurations, while reducing computational complexity by 47.5% compared with the statistical clustering algorithm. Furthermore, the joint power allocation scheme demonstrates clear advantages over FPC in terms of spectrum efficiency and user fairness, verifying the effectiveness and practicality of the proposed algorithm.
Available online , doi: 10.11999/JEIT250355
Abstract:
Objective This study aims to design and implement a scalable CPU–FPGA heterogeneous cluster for real-time simulation of high-frequency power electronic systems. With the increasing adoption of wide-bandgap semiconductor devices such as SiC and GaN, modern power systems exhibit complex switching dynamics that require sub-microsecond timestep resolution. This work focuses on the real-time modeling and simulation of 80 Voltage Source Converters (VSCs), equivalent to 480 switches, representing a typical scenario in renewable-integrated power grids with high switching frequency. Three major technical challenges are addressed: (1) enabling efficient task scheduling across multiple FPGAs to support large-scale parallel computation while maintaining load balance; (2) reducing hardware resource usage through precision-aware hybrid quantization that preserves accuracy with reduced bitwidth; and (3) minimizing CPU–FPGA communication latency via a high-throughput, low-latency data exchange framework to ensure stable synchronization between slow and fast subsystems. This work contributes to the development of a practical and extensible platform for simulating future power systems with complex electronic components. Methods To enable real-time simulation with sub-microsecond resolution, the system partitions the power system model into a slow subsystem (AC/DC network) and a fast subsystem (multiple VSCs), following a decoupled computation strategy. A Computation Load-Aware Scheduling (CLAS) strategy is employed to allocate tasks across four Xilinx XCKU060 FPGAs (Fig. 1 and Fig. 2 ), supporting parallel simulation of up to 80 VSCs. The slow subsystem is executed on the CPU using high-precision floating-point arithmetic with a 50 μs timestep. The fast subsystem is implemented on the FPGAs using fixed-point arithmetic at a 1 μs timestep (Fig. 3 and Fig. 4 ). A hybrid-precision quantization scheme is adopted: voltage-processing modules use Q(48,30) format to retain numerical precision, whereas current-dominant modules use Q(48,20) to avoid overflow. The FPGA-based Matrix–Vector Multiplication (MVM) is partitioned into two sub-modules (Sub MVM1 and Sub MVM2), leveraging row-level parallelism and pipelined streaming to achieve 400 ns latency per cycle. For communication, a Data Plane Development Kit (DPDK)-based zero-copy framework with lock-free queues is implemented between the CPU and FPGA, reducing latency to 29 μs and enabling reliable synchronization between fast and slow subsystems. Results and Discussions The proposed system successfully achieves real-time simulation of a wind farm model comprising 80 VSCs using four Xilinx XCKU060 FPGA boards. Each FPGA supports 20 VSCs operating at a 1 μs timestep, with a computation latency of 400 ns, demonstrating the system’s ability to satisfy stringent real-time constraints. The hybrid-precision quantization strategy yields substantial resource savings relative to a 64-bit fixed-point baseline: LookUp Table (LUT) usage is reduced by 32.0%, Flip-Flops (FFs) by 24.2%, and Digital Signal Processors (DSPs) by 43.8%, while preserving simulation accuracy (Table 1 ). These optimizations support scalable deployment without loss of fidelity. Communication between the CPU and FPGA is handled by a DPDK-based zero-copy framework with lock-free queues, achieving an end-to-end latency of 29 μs. This ensures robust synchronization between the slow and fast subsystems. Compared with existing FPGA-based designs, the proposed architecture provides a more resource-efficient solution (Table 1 ), delivering sub-microsecond simulation performance with reduced hardware cost and enabling multi-VSC deployment per FPGA. These findings highlight the platform’s applicability for large-scale industrial power system simulation (Fig. 6 ). Conclusions This study presents a CPU–FPGA heterogeneous cluster designed for real-time simulation of large-scale power systems. The system employs a decoupled, CLAS strategy that enables efficient resource distribution across multiple FPGAs. Real-time requirements are fully met, and the use of hybrid-precision quantization substantially reduces FPGA resource consumption without sacrificing accuracy. The system demonstrates scalability and efficiency by supporting up to 80 VSCs across four FPGA boards. Compared with existing solutions, the proposed architecture achieves the lowest resource utilization while maintaining sub-microsecond resolution, making it a practical platform for industrial-grade power system simulation.
Available online , doi: 10.11999/JEIT250285
Abstract:
Objective As the miniaturization of semiconductor chips approaches physical limitations, integrated chip technologies have become essential to meet the demand for high-performance, low-cost devices in the post-Moore era. Through-Silicon Via (TSV) is a key process in advanced packaging that requires precise testing to ensure reliable interconnections. Quantitative test methods can estimate defect sizes based on test responses; however, variations in Process, Voltage, and Temperature (PVT) hinder accurate defect characterization, making the associated overhead of data capture and analysis difficult to justify. Current techniques often require long test time, with some necessitating two test cycles. While leakage defect detection has reached high accuracy, the detection of resistive open defects—sometimes only tens of milliohms in fault-free states—remains inadequate. This study presents a method that improves detection accuracy for resistive open defects and reduces both test area and time overhead, offering a more efficient and practical TSV testing solution. Methods Previous studies indicate that rising-edge testing provides higher resolution than falling-edge testing and enables simultaneous differentiation of multiple defect types. Based on this principle, a symmetric testing scheme through a single rising-edge test is proposed. To reduce the area overhead associated with shared test structures, MOS gates are employed as selection switches. NMOS transistors, due to their strong 0 and weak 1 characteristics, are placed at the driving end to enable rapid discharge and reset of the reference capacitor voltage. PMOS transistors, exhibiting strong 1 and weak 0 characteristics, are positioned at the receiving end to block interference from low-voltage signals. A two-stage comparator is then employed to amplify the voltage difference between the reference capacitor and the test TSV during the charging phase, producing two intermediate voltage levels. These are subsequently converted into standard high or low logic levels by a Schmitt trigger inverter. Based on the output logic level, both the presence and type of defect can be determined from a single test. Results and Discussions The effectiveness of the proposed method is verified through HSPICE simulations using the Nangate 45 nm open cell library. The detection accuracy for different defect types is modulated by adjusting the Width-to-Length (W/L) ratio of the MOS transistors, as shown in (Table 2 ). For instance, reducing the W/L ratio of NMOS transistors enhances the detection sensitivity to leakage defects. Specific W/L ratios can therefore be selected to meet targeted testing requirements. (Table 3 ) presents the results under PVT variations. Although the accuracy shows minor fluctuations, these remain within acceptable limits. A temperature variation of approximately 27 °C results in only a 1 Ω deviation in resistive open defect detection, and a 1 MΩ range in leakage defect accuracy. Even under the worst-case PVT condition, the minimum detection threshold for resistive open defects reaches 94 Ω, which exceeds the capability of existing methods. Conclusions A prebond TSV testing scheme based on MOS gating is proposed to address the high area and time overheads and limited accuracy of conventional approaches. The scheme adopts a symmetric structure between the reference capacitor and the test TSV to mitigate capacitance variation caused by fabrication inconsistencies. A two-stage comparator amplifies the voltage difference between the defective TSV and the reference capacitor during charging, thereby enhancing detection resolution. Simulation results indicate that the method detects resistive open defects equal of above 50 Ω and leakage defects equal of below 9 MΩ. Compared with existing methods, the proposed approach significantly reduces both testing area and time. When multiple TSVs share the testing circuitry, only one NMOS and one PMOS transistor are added, further minimizing the average area overhead.
Available online , doi: 10.11999/JEIT250258
Abstract:
Objective With the rapid development of quantum communication and computation, efficient error-correction technologies are critical for ensuring the reliability of quantum systems. Maximal Distance Separable (MDS) Entanglement-Assisted Quantum Error-Correcting Codes (EAQECCs) with flexible code lengths and larger minimum distances offer significant advantages in enhancing quantum system robustness. However, classical quantum codes face limitations in parameter flexibility and minimum distance constraints. This study addresses these challenges by leveraging Twisted Generalized Reed-Solomon (TGRS) codes to construct novel MDS EAQECCs, aiming to improve performance in complex quantum communication scenarios. In this paper, TGRS codes are innovatively applied to construct MDS EAQECCs. Different from polynomial construction methods, we determine the dimension of the Hermitian Hull through special matrix rank analysis, and successfully construct \begin{document}$ q $\end{document} \begin{document}$ q+1 $\end{document} \begin{document}$ q $\end{document} \begin{document}$ q+1 $\end{document} Table 2 systematically summarizes the known MDS EAQECCs with a length less than \begin{document}$ {q}^{2} $\end{document} \begin{document}$ q+1 $\end{document} Methods The proposed approach integrates TGRS codes with algebraic techniques to design MDS EAQECCs. Two families of MDS EAQECCs are constructed by using TGRS codes over finite fields. The key steps are as follows: (1) TGRS Code Construction: Utilizing twisted polynomials and hook parameters to generate TGRS codes with adjustable dimensions and minimum distances. (2) Hermitian Hull Analysis: Applying matrix rank analysis to determine the dimensions of the Hermitian Hull of the constructed codes, which is crucial for satisfying the Singleton bound in quantum codes. (3) Twisted Operation Optimization: Employing twisted operations to transform the constructed MDS EAQECCs into ME-MDS EAQECCs. Results and Discussions This paper constructs two families of MDS EAQECCs using TGRS codes and gives certain twisted conditions under which the codes are ME-MDS EAQECCs. Compared with other known codes, these new codes have more flexible parameters and significant advantages in terms of code length, minimum distance, and maximum entanglement state. This paper constructs \begin{document}$ q $\end{document} \begin{document}$ [[i(q-1), $\end{document} \begin{document}$ i(q-1)-2j-q-t+2v+2,q+j+1;q-t+2v+2]{]}_{q} $\end{document} \begin{document}$ i $\end{document} \begin{document}$ [[i(q-1),i(q-1)- 2j-q-t+ $\end{document} \begin{document}$ 2v+3,q+j+1;q-t+2v+3]{]}_{q} $\end{document} \begin{document}$ i $\end{document} Table 1 .Theorems 3-6 give the existence conditions of specific \begin{document}$ q $\end{document} \begin{document}$ \left[\right[i(q-1),i(q-1)-q-j,q+j+1;q+j]{]}_{q} $\end{document} \begin{document}$ q $\end{document} \begin{document}$ \left[\right[i(q+1),(i-1)(q+1)-s,q+2;q-s+1]{]}_{q} $\end{document} \begin{document}$ [[i(q+1),(i-1) $\end{document} \begin{document}$ (q+1),q+2;q+1]{]}_{q} $\end{document} \begin{document}$ q $\end{document} Conclusions Two families of MDS EAQECCs are constructed using TGRS codes, and the parameters of known MDS EAQECCs are systematically summarized. Comparative analysis reveals that the EAQECCs proposed in this paper offer the following advantages: Compared with the known \begin{document}$ q $\end{document} Table 2 ), the parameters of the MDS EAQECCs constructed here are new and have not been covered by previous studies; The codes not only enable flexible code-length adjustments but also achieve a minimum distance that significantly exceeds traditional theoretical bounds; Under specific twisted conditions, the constructed MDS EAQECCs are upgraded to ME-MDS EAQECCs. By introducing the twisted operation on RS codes, more flexible parameter combinations are obtained. This provides greater flexibility in the design of quantum error-correcting codes, enabling better adaptation to different quantum communication requirements. This improvement further optimizes the performance of quantum error-correcting codes, enhancing the entanglement-assisted error-correcting ability and improving the overall efficiency of quantum systems. These research results indicate that TGRS codes are important theoretical tools for constructing high-performance EAQECCs with excellent parameters. They play a pivotal part in advancing the development of quantum communication technology. Moreover, they offer a firm theoretical underpinning for the practical implementation of quantum error-correcting codes. Future research can focus on further exploring the potential of TGRS codes in constructing more advanced quantum error-correcting codes and expanding their applications in different quantum communication scenarios.
Available online , doi: 10.11999/JEIT250651
Abstract:
Objective The Controller Area Network (CAN), the de facto standard for in-vehicle communication, is inherently vulnerable to cyberattacks. Existing Intrusion Detection Systems (IDSs) face a fundamental trade-off: achieving fine-grained classification of diverse attack types often requires computationally intensive models that exceed the resource limitations of on-board Electronic Control Units (ECUs). To address this problem, this study proposes a two-stage attack detection framework for the CAN bus that fuses temporal and deep features. The framework is designed to achieve both high classification accuracy and computational efficiency, thereby reconciling the tension between detection performance and practical deployability. Methods The proposed framework adopts a “detect-then-classify” strategy and incorporates two key innovations. (1) Stage 1: Temporal Feature-Aware Anomaly Detection. Two custom features are designed to quantify anomalies: Payload Data Entropy (PDE), which measures content randomness, and ID Frequency Mean Deviation (IFMD), which captures behavioral deviations. These features are processed by a Bidirectional Long Short-Term Memory (BiLSTM) network that exploits contextual temporal information to achieve high-recall anomaly detection. (2) Stage 2: Deep Feature-Based Fine-Grained Classification. Triggered only for samples flagged as anomalous, this stage employs a lightweight one-dimensional ParC1D-Net. The core ParC1D Block (Fig. 4 ) integrates depthwise separable one-dimensional convolution, Squeeze-and-Excitation (SE) attention, and a Feed-Forward Network (FFN), enabling efficient feature extraction with minimal parameters. Stage 1 is optimized using BCEWithLogitsLoss, whereas Stage 2 is trained with Cross-Entropy Loss. Results and Discussions The efficacy of the proposed framework is evaluated on public datasets. (1) State-of-the-art performance. On the Car-Hacking dataset (Table 5 ), an accuracy and F1-score of 99.99% are achieved, exceeding advanced baselines. On the more challenging Challenge dataset (Table 6 ), superior accuracy (99.90%) and a competitive F1-score (99.70% are also obtained. (2) Feature contribution analysis. Ablation studies (Tables 7 and 8 ) confirm the critical role of the proposed features. Removal of the IFMD feature results in the largest performance reduction, highlighting the importance of behavioral modeling. A synergistic effect is observed when PDE and IFMD are applied together. (3) Spatiotemporal efficiency. The complete model remains lightweight at only 0.39 MB. Latency tests (Table 9 ) demonstrate real-time capability, with average detection times of 0.62 ms on a GPU and 0.93 ms on a simulated CPU (batch size = 1). A system-level analysis (Section 3.5.4) further shows that the two-stage framework is approximately 1.65 times more efficient than a single-stage model in a realistic sparse-attack scenario. Conclusions This study establishes the two-stage framework as an effective and practical solution for CAN bus intrusion detection. By decoupling detection from classification, the framework resolves the trade-off between accuracy and on-board deployability. Its strong performance, combined with a minimal computational footprint, indicates its potential for securing real-world vehicular systems. Future research could extend the framework and explore hardware-specific optimizations.
Available online , doi: 10.11999/JEIT250294
Abstract:
As a key approach to enhancing computing performance and enabling heterogeneous integration in the post-Moore era, chiplet technology relies heavily on the efficiency and reliability of its internal interconnection networks. However, these networks face severe challenges, as frequent link failures and dynamic congestion often coexist and interact, making it difficult to meet the requirements of high-performance and high-reliability systems. To address this issue, this paper proposes a joint Fault- and Congestion-aware Adaptive Routing Algorithm (FCARA). By sensing link status and congestion levels in real time, the algorithm constructs a joint cost function that integrates fault, congestion, and distance factors to dynamically select the optimal path. Simulation-based evaluations and comparisons with benchmark algorithms show that the proposed method markedly reduces average packet delay and improves network saturation throughput. It demonstrates particularly strong performance and robustness under high fault rates and unbalanced traffic conditions. Hardware synthesis and power analysis based on a 65 nm process confirm that the algorithm achieves favorable trade-offs between performance and cost. These findings indicate that the proposed algorithm offers an effective and practical solution to the concurrent challenges of faults and congestion in chiplet interconnect networks. Objective With the rapid advancement of chiplet technology as a key solution for post-Moore era computing, the performance and reliability of its internal interconnect network (NoC) have become critical determinants of overall system efficiency. However, chiplet NoCs face unique challenges arising from the concurrent occurrence and coupling of frequent link faults, caused by advanced packaging and high-density interconnects, and dynamic network congestion. Existing routing algorithms typically address these issues in isolation: fault-tolerant methods often overlook the performance degradation introduced by detours under congestion, whereas congestion-aware methods generally assume fault-free networks and fail to adapt when faults occur. These limitations hinder the realization of truly high-performance and highly reliable chiplet systems. Therefore, developing an adaptive routing algorithm that simultaneously and effectively addresses both link faults and network congestion in chiplet interconnects is a crucial requirement. Methods To address the challenge, a joint FCARA is proposed for chiplet NoCs. The method is based on real-time, distributed perception of the network state at each router. Information on the fault status of local outgoing links (e.g., normal, partial fault, complete fault) and the congestion level of the input port at the next-hop router is collected. A joint cost function is then employed to quantitatively evaluate potential next-hop directions by integrating three weighted factors: severity of link fault, degree of downstream congestion, and distance to the destination. Using the calculated costs for all available deadlock-free paths, the optimal path with the lowest cost is dynamically selected for forwarding incoming flits. The effectiveness of FCARA is evaluated through extensive cycle-accurate simulations on the ChipletSimulator platform. Performance is compared with baseline algorithms including Dimension-Order Routing (DOR), a representative Fault-tolerant Adaptive Algorithm (FT-Adap), and a representative Congestion-aware Adaptive Algorithm (CA-Adap). Hardware overhead is further assessed through RTL modeling and synthesis using a commercial 65 nm standard cell library, and power consumption is analyzed with Synopsys tools. Results and Discussions Simulation results demonstrate the clear advantages of the proposed FCARA algorithm. Across a wide range of fault rates (0%–30%) and traffic patterns, FCARA consistently outperforms baseline algorithms in key performance metrics. In particular, it achieves markedly lower average packet latency and higher network saturation throughput (Fig. 6 , Fig. 7 ). The performance gap becomes especially pronounced under harsh conditions such as high fault rates (≥20%) and non-uniform traffic loads (Fig. 9 ), highlighting FCARA’s robustness. This improvement results from its joint cost function and adaptive decision-making, which enable it to simultaneously bypass faulty links and congested regions (Algorithm 1). Hardware overhead analysis, based on synthesis and power estimation (Table 2 , Table 3 ), shows that FCARA increases router area by 13.1% and total power consumption by 15.6% compared with the baseline DOR router. Conclusions This study developed and evaluated FCARA, a novel adaptive routing strategy tailored for chiplet interconnect networks operating under concurrent link faults and network congestion. The results demonstrate that by jointly incorporating fault and congestion information into routing decisions, FCARA substantially improves network performance in terms of latency and throughput while enhancing robustness compared with conventional approaches that address these issues separately. With its proven effectiveness and moderate hardware overhead, FCARA offers a practical and efficient solution for achieving high-performance, high-reliability communication in next-generation chiplet-based systems.
Available online , doi: 10.11999/JEIT250238
Abstract:
Objective As a core task in computer vision, object detection is vital for intelligent transportation, supporting applications such as autonomous driving, Electronic Toll Collection (ETC), and traffic violation monitoring. However, complex urban environments—characterized by extreme weather, dense traffic occlusions, intense illumination, and reflective surfaces—pose substantial challenges, leading traditional methods to high false detection and missed detection rates. Despite recent progress, accuracy issues remain unresolved. To address these limitations, this study proposes YOLO-SCDI, a lightweight and effective vehicle detection model systematically optimized from YOLOv8 across four components: backbone network, neck structure, detection head, and loss function. These improvements significantly enhance detection accuracy and robustness in complex traffic conditions while maintaining model compactness and inference efficiency. Methods Building on the YOLOv8n architecture, four top-down optimization strategies are designed to balance detection accuracy, parameter efficiency, and lightweight deployment. First, to address the limited feature representation capacity, an attention-enhanced C2f-SCSA module (Fig. 4 ) is proposed. This module dynamically integrates local and global features through multi-scale convolutions and a dual spatial–channel attention mechanism, thereby improving the quality of input features. Second, to achieve effective multi-scale information integration while preserving both detailed and contextual features, a lightweight Cross-scale Feature Fusion Module (CCFM) is introduced into the Neck structure (Fig. 5 ). This results in the CCFM-Neck architecture, which reduces parameter size and enhances sensitivity to small-scale targets. Third, to mitigate the limitations of YOLOv8’s detection head—such as fixed feature fusion patterns and weak dynamic cross-scale interactions—a Dynamic Head module is incorporated. This module jointly models scale, spatial, and task attention, and includes a dynamic convolution-kernel generation network that adjusts convolution weights in real time according to input features. These improvements strengthen classification and regression feature responses, increasing the adaptability and discriminability of the detection head. Finally, because the CIoU loss function shows insufficient localization accuracy for small or irregular targets, ShapeIoU is adopted as the loss function. It is further improved using the Inner-IoU concept, which accelerates model convergence and enhances localization performance. Results and Discussions YOLO-SCDI is evaluated against mainstream detection models on the UA-DETRAC and BDD100K datasets. On the UA-DETRAC dataset (Table 4 ), YOLO-SCDI achieves an optimal balance between resource efficiency and detection performance. It requires only 2.37 M parameters and 7.6 GFLOPs—substantially fewer than competing models—while attaining 95.8% mAP@0.5, a 2.5% improvement over the baseline YOLOv8n and higher than most mainstream detectors. Under the stricter mAP@0.5:0.95 metric, YOLO-SCDI reaches 80.3%, clearly outperforming other lightweight designs. On the BDD100K dataset (Table 5 ), YOLO-SCDI improves mAP@0.5 and mAP@0.5:0.95 by 1.4% and 1.1%, respectively, compared with the baseline. These results are consistent with those from the UA-DETRAC dataset, confirming strong generalization and robustness. Detection results under varying illumination (Fig. 7 ) and adverse weather (Fig. 8 ) further validate its performance in realistic complex scenarios. Compared with models such as NanoDet, YOLOv12n, and YOLOv8n, YOLO-SCDI effectively reduces missed and false detections while providing higher-confidence predictions and more precise localization. Additionally, ablation studies (Table 3 ) confirm the contributions of the proposed C2f-SCSA, Dynamic Head, and Inner-ShapeIoU modules to performance gains. Collectively, these results demonstrate that YOLO-SCDI markedly enhances detection accuracy while maintaining a lightweight structure, thereby meeting practical requirements for vehicle detection in complex traffic environments. Conclusions This study proposes YOLO-SCDI, a vehicle detection algorithm built on an improved YOLOv8 framework. By optimizing the backbone network, neck structure, detection head, and loss function, the method enhances detection accuracy while substantially reducing model parameters. Experimental evaluations demonstrate that YOLO-SCDI exceeds existing approaches in both accuracy and model efficiency, making it well suited for practical vehicle detection tasks in complex traffic environments.
Available online , doi: 10.11999/JEIT250236
Abstract:
Objective Conventional low-elevation angle estimation algorithms for Multiple-Input Multiple-Output (MIMO) radar generally assume a single-path propagation model, which limits their applicability in complex terrain where multipath effects are time-varying. Compressive Sensing (CS) algorithms exploit the sparsity of direct and multipath signals in the spatial domain and remain effective in such environments. Nonetheless, CS-based approaches for MIMO radar require the construction of a two-dimensional grid dictionary, and their computational complexity increases sharply as the number of multipath components grows. Existing complexity-reduction methods sacrifice array aperture, leading to degraded estimation accuracy. To resolve the trade-off between aperture utilization and computational complexity in low-elevation angle estimation for MIMO radar under complex terrain conditions, a tensor-based two-step estimation algorithm is proposed. Methods A three-dimensional tensor observation model is first established to fully preserve the multi-dimensional structure of the received signal, and the tensor signal subspace is extracted using High-Order Singular Value Decomposition (HOSVD). After eliminating redundancy in the tensor subspace, Sparse Bayesian Learning (SBL) is applied to rapidly obtain initial estimates of the low-elevation and multipath angles. These initial results are then refined by an alternating iterative Generalized Multiple Signal Classification (GMUSIC) algorithm, which leverages the complete tensor subspace. The proposed method maintains full array aperture, adapts to scenarios with unknown numbers of multipaths, and achieves a favorable balance between estimation accuracy and computational efficiency. Results and Discussions Simulation results demonstrate that the proposed algorithm achieves high estimation accuracy under both single- and double-reflection paths (Fig. 2 –5 ) compared with other benchmark algorithms, while maintaining lower computational complexity (Table 1 ). Relative to the sub-optimal Alternative Projection Maximum Likelihood (APML) algorithm, the running speed is improved by 92.16%. In addition, the method remains robust under time-varying multipath conditions (Fig. 6 ) without requiring prior knowledge of the spatial distribution of reflection paths. Validation with real measured data (Fig. 8 –10 ) further confirms its practical applicability: 86.95% of estimates fall within the 0–0.4° error range, and the error remains consistently below 0.6° across the observation window. These findings highlight the superior estimation accuracy and reliability of the proposed method, supporting its suitability for real-world engineering applications. Conclusions By integrating tensor modeling, sparse preliminary estimation, and alternating iterative optimization, the proposed algorithm fully exploits the multi-dimensional structure of the received signal and the complete array aperture of MIMO radar. It demonstrates high estimation accuracy while maintaining low computational complexity. Simulation results confirm its effectiveness and robustness in complex terrain, and validation with measured data further verifies its feasibility and engineering applicability. Nonetheless, this study is limited to a single-target scenario with a relatively simple motion trajectory. Future research should extend the method to address complex motion patterns with multiple targets.
Available online , doi: 10.11999/JEIT250567
Abstract:
Significance With the continuous advancement of information technology, digital images are evolving toward ultra-high-definition formats characterized by increased resolution, dynamic range, color depth, sampling rates, and multi-viewpoint support. In parallel, the rapid development of artificial intelligence is reshaping both the generation and application paradigms of digital imagery. As visual big data converges with AI technologies, the volume and diversity of image data expand exponentially, creating unprecedented challenges for storage and transmission. As a core technology in digital image processing, image compression reduces storage costs and bandwidth requirements by eliminating internal information redundancy, thereby serving as a fundamental enabler for visual big data applications. However, traditional image compression standards increasingly struggle to meet rising industrial demands due to limited modeling capacity, inadequate perceptual adaptability, and poor compatibility with machine vision tasks. Deep Neural Network (DNN)-based image compression methods, leveraging powerful modeling capabilities, end-to-end optimization mechanisms, and compatibility with both human perception and machine understanding, are progressively exceeding conventional coding approaches. These methods demonstrate clear advantages and broad potential across diverse application domains, drawing growing attention from both academia and industry. Progress This paper systematically reviews recent advances in DNN-based image compression from three core perspectives: signal fidelity, human visual perception, and machine analysis. First, in signal fidelity–oriented compression, the rate–distortion optimization framework is introduced, with detailed discussion of key components in lossy image compression, including nonlinear transforms, quantization strategies, entropy coding mechanisms, and variable-rate techniques for multi-rate adaptation. The synergistic design of these modules underpins the architecture of modern DNN-based image compression systems. Second, in perceptual quality–driven compression, the principles of joint rate–distortion–perception optimization models are examined, together with a comparative analysis of two major perceptual paradigms: Generative Adversarial Network (GAN)-based models and diffusion model–based approaches. Both strategies employ perceptual loss functions or generative modeling techniques to markedly improve the visual quality of reconstructed images, aligning them more closely with the characteristics of the human visual system. Finally, in machine analysis–oriented compression, a co-optimization framework for rate–distortion–accuracy trade-offs is presented, with semantic fidelity as the primary objective. From the perspective of integrating image compression with downstream machine analysis architectures, this section analyzes how current methods preserve essential semantic information that supports tasks such as object detection and semantic segmentation during the compression process. Conclusions DNN-based image compression shows strong potential across signal fidelity, human visual perception, and machine analysis. Through end-to-end jointly optimized neural network architectures, these methods provide comprehensive modeling of the encoding process and outperform traditional approaches in compression efficiency. By leveraging the probabilistic modeling and image generation capabilities of DNNs, they can accurately estimate distributional differences between reconstructed and original images, quantify perceptual losses, and generate high-quality reconstructions that align with human visual perception. Furthermore, their compatibility with mainstream image analysis frameworks enables the extraction of semantic features and the design of collaborative optimization strategies, allowing efficient compression tailored to machine vision tasks. Prospects Despite significant progress in compression performance, perceptual quality, and task adaptability, DNN-based image compression still faces critical technical challenges and practical limitations. First, computational complexity remains high. Most high-performance models rely on deep and sophisticated architectures (e.g., attention mechanisms and Transformer models), which enhance modeling capability but also introduce substantial computational overhead and long inference latency. These limitations are particularly problematic for deployment on mobile and embedded devices. Second, robustness and generalization continue to be major concerns. DNN-based compression models are sensitive to input perturbations and vulnerable to adversarial attacks, which can lead to severe reconstruction distortions or even complete failure. Moreover, while they perform well on training data and similar distributions, their performance often degrades markedly under cross-domain scenarios. Third, the evaluation framework for perceptual- and machine vision–oriented compression remains immature. Although new evaluation dimensions have been introduced, no unified and objective benchmark exists. This gap is especially evident in machine analysis–oriented compression, where downstream tasks vary widely and rely on different visual models. Therefore, comparability across methods is limited and consistent evaluation metrics are lacking, constraining both research and practical adoption. Overall, DNN-based image compression is in transition from laboratory research to real-world deployment. Although it demonstrates clear advantages over traditional approaches, further advances are needed in efficiency, robustness, generalization, and standardized evaluation protocols. Future research should strengthen the synergy between theoretical exploration and engineering implementation to accelerate widespread adoption and continued progress in areas such as multimedia communication, edge computing, and intelligent image sensing systems.
Available online , doi: 10.11999/JEIT250495
Abstract:
Objective Accurate recognition of aerial adversarial maneuvers is essential for situational awareness and tactical decision-making in modern air warfare. Conventional supervised approaches face major challenges: obtaining labeled flight data is costly due to the intensive human effort required for collection and annotation, and these methods are limited in capturing temporal dependencies inherent in sequential flight parameters. Temporal dynamics are crucial for describing the evolution of maneuvers, yet existing models fail to fully exploit this information. To address these challenges, this study proposes a weakly supervised maneuver recognition framework based on contrastive learning. The method leverages a small proportion of labeled data to learn discriminative representations, thereby reducing reliance on extensive manual annotations. The proposed framework enhances recognition accuracy in data-scarce scenarios and provides a robust solution for maneuver analysis in dynamic adversarial aerial environments. Methods The proposed framework extends the Simple Framework for Contrastive Learning of visual Representations (SimCLR) into the time-series domain by incorporating five temporal-specific data augmentation strategies: time compression, masking, permutation, scaling, and flipping. These augmentations generate multi-view samples that form positive pairs for contrastive learning, thereby ensuring temporal invariance in the feature space. A customized ResNet-18 encoder is employed to extract hierarchical features from the augmented time-series data, and a Multi-Layer Perceptron (MLP) projection head maps these features into a contrastive space. The Normalized Temperature-scaled cross-entropy (NT-Xent) loss is adopted to maximize similarity between positive pairs and minimize it between negative pairs, which effectively mitigates pseudo-label noise. To further improve recognition performance, a fine-tuning strategy is introduced in which pre-trained features are combined with a task-specific classification head using a limited amount of labeled data to adapt to downstream recognition tasks. This contrastive learning framework enables efficient analysis of time-series flight data, achieves accurate recognition of fighter aircraft maneuvers, and reduces dependence on large-scale labeled datasets. Results and Discussions Experiments are conducted on flight simulation data obtained from DCS World. To address the class imbalance issue, hybrid datasets (Table 1 ) are constructed, and training data ratios ranging from 2% to 30% are employed to evaluate the effectiveness of the weakly supervised framework. The results demonstrate that contrastive learning effectively captures the temporal patterns within flight data. For example, on the D1 dataset, accuracy with the base method increases from 35.83% with 2% labeled data to 89.62% when the fine-tuning ratio reaches 30% (Tables 3 –6 , Fig. 2(a) –2(c) ). To improve recognition of long maneuver sequences, a linear classifier and a voting strategy are introduced. The voting strategy markedly enhances few-shot learning performance. On the D1 dataset, accuracy reaches 54.5% with 2% labeled data and rises to 97.9% at a 30% fine-tuning ratio, representing a substantial improvement over the base method. On the D6 dataset, which simulates multi-source data fusion scenarios in air combat, the accuracy of the voting method increases from 0.476 with 2% labeled data to 0.928 with 30% labeled data (Fig. 2(d) –2(f) ), with a growth rate in the low-data phase 53% higher than that of the base method. Additionally, on the comprehensive D7 dataset, the accuracy standard deviation of the voting method is only 0.011 (Fig. 2(g) , Fig. 3 ), significantly lower than the 0.015 observed for the base method. The superiority of the proposed framework can be attributed to two factors: the suppression of noise through integration of multiple prediction results using the voting strategy and the extraction of robust features from unlabeled data via contrastive learning pre-training. Together, these techniques enhance generalization and stability in complex scenarios, confirming the effectiveness of the method in leveraging unlabeled data and managing multi-source information. Conclusions This study applies the SimCLR framework to maneuver recognition and proposes a weakly supervised approach based on contrastive learning. By incorporating targeted data augmentation strategies and combining self-supervised learning with fine-tuning, the method exploits the latent information in time-series data, yielding substantial improvements in recognition performance under limited labeled data conditions. Experiments on simulated air combat datasets demonstrate that the framework achieves stable recognition across different data categories, offering practical insights for feature learning and model optimization in time-series classification tasks. Future research will focus on three directions: first, integrating real flight data to evaluate the model’s generalization capability in practical scenarios; second, developing dynamically adaptive data augmentation strategies to enhance performance in complex environments; and third, combining reinforcement learning and related techniques to improve autonomous decision-making in dynamic aerial missions, thereby expanding opportunities for intelligent flight operations.
Available online , doi: 10.11999/JEIT250396
Abstract:
Objective Fully digital beamforming architectures provide high spectral efficiency but demand one Radio-Frequency (RF) chain per antenna element, resulting in substantial cost, power consumption, and hardware complexity. These limitations hinder their practical deployment in large-scale antenna systems. Hybrid beamforming offers a feasible alternative by reducing hardware requirements while retaining much of the performance. In such systems, analog beamforming modules follow a reduced number of RF chains to control massive antenna arrays. Analog phase shifters are energy-efficient and cost-effective but restricted to constant modulus constraints, which are essential for hardware implementation. In contrast, digital phase shifters offer flexible control over amplitude and phase. The central challenge is to approximate the spectral efficiency of fully digital systems while adhering to analog-domain constraints and minimizing energy and hardware demands. To overcome this challenge, this study proposes a novel hybrid beamforming algorithm that integrates Riemannian manifold optimization with a non-monotonic line search strategy (MO-NMLS). This approach achieves improved trade-offs among spectral efficiency, energy consumption, and hardware complexity. Methods The proposed methodology proceeds as follows. First, the joint matrix optimization problem for maximizing spectral efficiency in hybrid beamforming is decomposed into separate transmitter and receiver subproblems by formulating an appropriate objective function. This objective is then reformulated using a least squares approach, reducing the dimensionality of the search space from two to one. To accommodate the constant modulus constraints of analog beamforming, the problem is transformed into an unconstrained optimization on Riemannian manifolds. Both the Euclidean and Riemannian gradients of the modified objective function are derived analytically. Step sizes are adaptively determined using a MO-NMLS, which incorporates historical gradient information to compute dynamic step factors. This mechanism guides the search direction while avoiding convergence to suboptimal local minima due to fixed step sizes. Distinct update rules for the step factor are applied depending on whether the iteration count is odd or even. In each iteration, the current objective function value is compared with those from the preceding L iterations to decide whether to accept the new step and iteration point. After updating the step size, tangent vectors are retracted onto the manifold to generate new iterates until convergence criteria are satisfied. Once the analog precoder is fixed based on the optimized search direction, the corresponding digital precoder is derived in closed form. The dynamic step factor is computed using gradient data from the current and preceding L iterations, allowing the objective function to exhibit non-strict monotonicity within bounded ranges. This adaptive strategy results in faster convergence compared with conventional fixed-step methods. Results and Discussions The relationship between internal iteration count and Signal-to-Noise Ratio (SNR) for different beamforming algorithms is shown in Fig. 4 . The MO-NMLS algorithm requires significantly fewer iterations than the conventional Conjugate Gradient (CG) method under both fully connected and overlapping subarray architectures. This improved efficiency arises from the use of Riemannian manifold optimization, which inherently satisfies the constant modulus constraints without necessitating computationally intensive Hessian matrix evaluations. Runtime performance is benchmarked in Fig. 5 . The MO-NMLS algorithm reduces runtime by 75.3% relative to CG in the fully connected structure and by 79.2% in the overlapping subarray structure. Additionally, MO-NMLS achieves a further 21.1% reduction in runtime under the overlapping subarray architecture compared with the fully connected one, owing to simplified hardware requirements. Spectral efficiency as a function of SNR is presented in Fig. 6 . In fully connected systems, MO-NMLS achieves a 0.64% improvement in spectral efficiency over CG while maintaining comparable stability in overlapping subarray architectures. This performance gain stems from the algorithm’s ability to avoid local optima, a key limitation of Orthogonal Matching Pursuit (OMP), which selects paths based solely on residual correlation. The scalability of MO-NMLS with respect to the number of antennas and data streams is demonstrated in Fig. 7 . In fully connected systems, MO-NMLS outperforms CG by 1.94%, 2.16%, and 2.74% in spectral efficiency at antenna and data stream configurations of (32, 2), (64, 4), and (128, 8), respectively. While spectral efficiency increases across all algorithms as system scale grows, MO-NMLS exhibits the most substantial gains at higher scales. Energy efficiency improvements under the overlapping subarray architecture are shown in Fig. 8 . Compared with the fully connected configuration, MO-NMLS yields energy efficiency gains of 1.2%, 10.9%, and 25.9% at subarray offsets of 1, 8, and 16, respectively. These improvements are attributed to the reduced number of required phase shifters and power amplifiers, which decreases total system power consumption as the subarray offset increases. Conclusions The proposed MO-NMLS algorithm achieves an effective balance among spectral efficiency, hardware complexity, and energy consumption in hybrid beamforming systems, while substantially reducing computational runtime. Moreover, the overlapping subarray architecture attains spectral efficiency comparable to that of fully connected systems, with significantly lower execution times. These results highlight the practical advantages of the proposed approach for large-scale antenna systems operating under resource constraints.
Available online , doi: 10.11999/JEIT250430
Abstract:
Objective Facial age progression has become increasingly important in applications such as criminal investigation and digital identity authentication, making it a key research area in computer vision. However, existing mainstream facial age progression networks face two primary limitations. First, they tend to overemphasize the embedding of age-related features, often at the expense of preserving identity-consistent multi-scale attributes. Second, they fail to effectively eliminate interference from non-age-related elements such as hair and glasses, leading to suboptimal performance in complex scenarios. To address these challenges, this study proposes a global–local co-embedding and semantic mask-driven aging method. The global–local co-embedding strategy improves the accuracy of input portrait reconstruction while reducing computational cost during the embedding phase. In parallel, a semantic mask editing mechanism is introduced to remove non-age-related features—such as hair and eyewear—thereby enabling more accurate embedding of age-related characteristics. This dual strategy markedly enhances the model’s capacity to learn and represent age-specific attributes in facial imagery. Methods A Global–Local Collaborative Embedding (GLCE) strategy is proposed to achieve high-quality latent space mapping of facial images. Distinct learning objectives are assigned to separate latent subspaces, which enhances the representation of fine-grained facial features while preserving identity-specific information. Therefore, identity consistency is improved, and both training time and computational cost are reduced, increasing the efficiency of feature extraction. To address interference from non-age-related elements, a semantic mask-driven editing mechanism is employed. Semantic segmentation and image inpainting techniques are integrated to accurately remove regions such as hair and glasses that hinder precise age modeling. A differentiable generator, DsGAN, is introduced to align the transferred latent codes with the embedded identity-preserving codes. Through this alignment, the expression of age-related features is enhanced, and identity information is better retained during the age progression process. Results and Discussions Experimental results on benchmark datasets, including CCAD and CelebA, demonstrate that GLS-Age outperforms existing methods such as IPCGAN, CUSP, SAM, and LATS in identity confidence assessment. The age distributions of the generated portraits are also more closely aligned with those of the target age groups. Qualitative analysis further shows that, in cases with hair occlusion, GLS-Age produces more realistic wrinkle textures and enables more accurate embedding of age-related features compared with other methods. Simultaneously, it significantly improves the identity consistency of the synthesized facial images. Conclusions This study addresses core challenges in facial age progression, including identity preservation, inadequate detail modeling, and interference from non-age-related factors. A novel Global–Local collaborative embedding and Semantic mask-driven Aging method (GLS-Age) is proposed to resolve these limitations. By employing a differentiated latent space learning strategy, the model achieves hierarchical decoupling of structural and textural features. When integrated with semantic-guided portrait editing and a differentiable generator for latent space alignment, GLS-Age markedly enhances both the fidelity of age feature expression and the consistency of identity retention. The method demonstrates superior generalization and synthesis quality across multiple benchmark datasets, effectively reproducing natural wrinkle patterns and age-related facial changes. These results confirm the feasibility and advancement of GLS-Age in facial age synthesis tasks. Furthermore, this study establishes a compact, high-quality dataset focused on Asian facial portraits, supporting further research in image editing and face generation within this demographic. The proposed method not only contributes technical support to practical applications such as cold case resolution and missing person identification in public security but also offers a robust data and modeling framework for advancing human age-based simulation technologies. Future work will focus on enhancing controllable editing within latent spaces, improving anatomical plausibility in skull structure transformations, and strengthening model performance across extreme age groups, including infants and the elderly. These efforts aim to expand the application of facial age progression in areas such as forensic analysis, humanitarian family search, and social security systems.
Available online , doi: 10.11999/JEIT250506
Abstract:
Objective Chiplet technology, which packages multiple dies with different functions and processes together, offers a cost-effective way for fabricating high-performance chips. For die-to-die data transmission, the edge density, Bit Error Rate (BER), and power consumption of the interface are crucial to the chip’s key performance metrics, such as computing power and throughput. Simultaneous Bi-Directional (SBD) signaling is an effective way to double the edge density by transmitting and receiving data on the same channel. However, with higher data rate and smaller channel pitch, channel reflection and crosstalk bring severe challenges to the design of interface circuits. This paper presents a single-ended SBD transceiver with echo and crosstalk cancellation to achieve a larger edge density and a lower BER. Methods The transceiver improves the per-wire data rate by utilizing the SBD signaling and denser shield-less channels. However, as both ends of the channel transmit data simultaneously, bi-directional signal coupling arises. Signal coupling, echo from impedance mismatch, and crosstalk from adjacent channels degrade the received data’s Signal-to-Noise Ratio (SNR). To decouple the bi-directional signal and cancel the echo and Near-End Crosstalk (NEXT), this paper proposes a Dynamic Voltage ThresHold generator (D-VTH). It generates the slicer’s threshold voltage according to the interfering signals needing to be subtracted. To cancel the Far-End Crosstalk (FEXT), a channel with the same capacitive and inductive coupling is designed by adjusting its width and space. FEXT is the subtraction of these two kinds of coupling, so it is canceled as expected. The source-synchronize architecture enhances the clock-data tracking performance, thereby reducing the clock-to-data jitter to improve the link’s noise margin. The synchronous clock distribution circuit includes a standing wave-based half-rate clock (CK2) distribution and a delay-controlled reset chain. The end of the CK2’s Transmission Line (TL) is terminated by a dedicated inductor, making the reflected wave have a proper amplitude and phase relative to the incident wave; thus, a standing wave can be formed, and CK2 synchronization is realized. To ensure the divided clocks (up to 1/32-rate) are synchronous, the dividers’ reset signals must be released at the same time or skewed with an integer multiple of 32 Unit Interval (UI). A reset chain is proposed to release the reset signals with controlled delay. The delay increases by 2 UI at each lane and is compensated by different stages of DFFs. After the CK2 and the divided clocks’ synchronization, the transmitter’s output and NEXT cancellation synchronization are achieved. Results and Discussions The test chip, including the proposed transceiver and the 3 mm on-chip channel, is fabricated in 28 nm CMOS. The shield-less data channels are routed in the M9 layer, with a channel pitch of 6.1 um. An electromagnetic field solver calculates the channel’s frequency response and the equivalent lumped model. The equivalent \begin{document}$ {C}_{\mathrm{m}}/{C}_{\mathrm{s}} $\end{document} \begin{document}$ {L}_{\mathrm{m}}/{L}_{\mathrm{s}} $\end{document} Fig.12 ). The D-VTH filter’s coefficients are obtained from the Sign-Sign Least Mean Square (SS-LMS) adaptation algorithm, and the data is received correctly using the adapted coefficients. The bi-directional decoupling coefficient is the largest because the local transmitter’s output is the strongest compared to the echo and crosstalk. The echo cancellation coefficient is the smallest because it has to undergo additional insertion loss in the channel (Fig.13 ). The simulated clock-to-data tracking performance shows the transceiver’s robustness against power supply noise (Fig.15 ). The standing wave distribution’s simulation results show its amplitude is double that of the conventional traveling wave because of the superposition of incident and reflected waves. A slight skew of 0.6 ps is observed, caused by the residual traveling wave due to the TL’s loss (Fig.18 ). The measured internal eye diagrams and bathtub curves at 64 Gb/s shows the eye-opening is 0.68 UI/80 mV at 10-9 BER and 0.64 UI/77 mV at 10-12 BER, with both crosstalk cancellation and echo cancellation enabled (Fig.21 ). In addition, the measured BER at the optimal sampling point is less than 10-16 with all the lanes counting bit errors. The Crosstalk-Induced Jitter (CIJ) is reduced from 0.58 UI to 0.06 UI after crosstalk cancellation is enabled, representing a reduction ratio of 89.6% (Table 1 ). The measured power efficiency is 1.21 pJ/b, and the simulated power breakdown shows that the transmitter, receiver, D-VTH, and clock distribution account for 40%, 23%, 34%, and 3%, respectively (Fig.22 ). This work achieves the best per-wire data rate and per-layer edge density compared with previous works (Table 2 ). Conclusions This paper utilizes SBD signaling and denser shield-less channels to achieve a per-wire data rate of 64 Gb/s and a per-layer edge density of 10.5 Tb/s/mm. The proposed echo and crosstalk cancellation circuit ensures an extremely low BER of less than 10-16. It provides new insights for increasing the edge density of die-to-die interfaces.
Available online , doi: 10.11999/JEIT250263
Abstract:
Objective The growing demand for massive computing power and big data processing has exposed bottlenecks in conventional Von Neumann architectures, known as the “storage wall” and the “power wall”. Computing-in-Memory (CiM) offers a promising solution by integrating storage and computation, thereby reducing delays and energy consumption caused by data transfer. Emerging non-volatile memories used in CiM circuit design include Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), and Ferroelectric Field-Effect Transistors (FeFETs). FeFETs have become key components in CiM designs due to their non-volatile storage capability, low power consumption, high on–off ratio, compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) processes, and voltage-driven writing mechanism. Various FeFET-based CiM circuit designs have been proposed, with most focusing on array-based structures. However, the potential of FeFET-based CiM logic circuits remains underexplored. This study proposes a methodology for mapping Boolean functions onto FeFET-based CiM logic circuits by designing a reconfigurable FeFET Multiplexer (FeFET-MUX) and developing corresponding Boolean function partitioning algorithms. Methods The reconfigurable FeFET-MUX consists of an elementary 2-to-1 MUX, as shown in Fig. 2(a) , with multiple data inputs and selection inputs, illustrated in Fig. 2(b) . The sub-circuit enclosed within the dashed box in Fig. 2(b) functions as the storage element of the FeFET-MUX and is time-shared by the data pathways. To ensure correct logical function execution, at any given time, no more than one address input is permitted to write to the FeFETs, and no more than one data input is selected simultaneously. Logical functions can be expressed using Binary Decision Diagrams (BDDs). By replacing each node in the BDD with a 2-to-1 MUX, the corresponding functions can be implemented using 2-to-1 MUX circuits. This technique is also applicable to mapping with 2-to-1 FeFET-MUXs; however, its major limitation is the relatively high area overhead. In this work, instead of replacing each individual BDD node with a 2-to-1 MUX, a sub-BDD is mapped onto the proposed FeFET-MUX, reducing area consumption. To prevent logic errors caused by incorrect rewriting of stored data due to the shared structure, a BDD partitioning approach is proposed. After applying specific partitioning rules, each sub-BDD can be independently implemented using the proposed FeFET-MUX, ensuring that stored data is preserved until it is no longer needed, thereby maintaining the logical function’s correctness.The operation of the proposed FeFET-MUX follows a three-phase cycle: (1) The polarization states of the two FeFETs are programmed by applying complementary gate pulses Vg1 and Vg2; (2) During each computation cycle, the selection gate pulses are temporally modulated to select distinct input data, which are routed to the FeFET drains; (3) Finally, the output enable pulses control the transmission of the computed result to the inverter’s output for storage. The proposed BDD partitioning algorithms are presented in Algorithm 1 and Algorithm 2. The methodology proceeds as follows: First, the target BDD, constructed using the Colorado University Decision Diagram (CUDD) library, is traversed through a breadth-first search. Next, upon identifying the starting node of a sub-BDD via the subroutine “find_node_start”, the subroutine “Extend_node” iteratively evaluates candidate nodes for inclusion in the current sub-BDD. After the traversal is complete, Algorithm 1 invokes the subroutine “Out_node_check” to determine whether additional sub-BDDs need to be created. Results and Discussions The proposed algorithms are implemented in C++ and executed on an Ubuntu 24.04 platform with an Intel Ultra 7 processor and 32 GB of memory. The compiler used is g++, version 13.3.0. Test benchmarks are selected from open-source designs described in Verilog. Prior to mapping, the benchmarks are converted into Reduced Ordered Binary Decision Diagrams (ROBDDs) using the CUDD library. Node information is extracted and stored in data structures, and ROBDD partitioning is performed using the proposed algorithms. The experimental results show that the number of sub-BDDs is not directly determined by the number of circuit inputs or outputs but is associated with the maximum number of nodes present at the same level within the BDD. This relationship results from the constraint that each sub-BDD cannot contain multiple nodes at the same level. For example, ROBDDs such as “parity,” which contain only one sub-BDD, exhibit a maximum of one node per level. However, the reverse does not always apply. For example, the circuit “i3” has a maximum of one node per level but still requires multiple sub-BDDs due to the presence of nodes with level differences greater than one, which violate the partitioning constraint and necessitate additional sub-BDDs to ensure correct function mapping. By integrating the reconfigurable FeFET-MUX with the proposed partitioning algorithms, the number of FeFET devices required decreases by an average of 79.9% compared with conventional mapping approaches (Table 2 ). In addition, the methodology successfully processes large-scale benchmarks, such as “i10,” which contains over 30,000 BDD nodes, demonstrating its scalability. Conclusion This work presents a novel methodology for mapping Boolean functions to FeFET-based CiM logic circuits. The approach consists of two core contributions: (1) A reconfigurable FeFET-MUX circuit is designed, featuring shared FeFET components and a common output drive stage. This configuration consolidates multiple 2-to-1 MUX functions into a single circuit, significantly improving resource utilization. (2) A BDD partitioning strategy is proposed, in which the Boolean logic circuit is partitioned into sub-BDDs, each implemented by a corresponding FeFET-MUX. Experimental results based on open-source logic synthesis benchmarks demonstrate an average reduction of 79.9% in FeFET usage (Table 2 ) compared to conventional mapping techniques. This is particularly important because FeFET devices occupy considerably more area than conventional Metal-Oxide-Semiconductor (MOS) transistors. Reducing FeFET usage leads to substantial area savings at the circuit level. Moreover, the proposed algorithms effectively process large and complex designs, including circuits exceeding 30,000 BDD nodes, confirming their applicability to large-scale CiM logic implementations.
Available online , doi: 10.11999/JEIT250313
Abstract:
Objective New Energy Vehicles (NEVs) have gained rapid popularity in recent years due to their environmental benefits and high efficiency. However, as their market share continues to grow, concerns regarding frequent malfunctions and safety risks have also increased. Among these issues, Internal Short Circuit (ISC) faults are particularly concerning due to their strong concealment and the potential for severe consequences. Without accurate diagnosis and timely intervention, ISC faults can result in serious safety incidents. Therefore, developing efficient and reliable diagnostic methods for ISC faults is of practical significance. Methods A novel ISC fault diagnosis method is proposed for battery packs by combining an improved battery phase plane approach with a Conformer-BiGRU network. First, the improved battery phase plane method is employed to extract two-dimensional features from voltage sequences, providing deeper spatial and structural information. Second, a Conformer-BiGRU network is employed to learn features from the voltage data. The network integrates a CNN branch for local feature extraction and a Transformer branch for global representation. A feature coupling unit fuses the outputs of both branches, which are then passed to a BiGRU module to classify individual cells within the battery pack and detect ISC faults. Results and Discussions The proposed method is evaluated using fault data collected from an experimental platform. The results demonstrate that the improved battery phase plane effectively distinguishes between normal and faulty batteries within a two-dimensional plane (Figure 6 ) and further confirm its capability to detect ISC faults with varying severity under different data volumes (Figure 9 ). Using the Conformer-BiGRU network for fault diagnosis, the method achieves classification accuracies of 94.30%, 92.70%, and 94.85% under FUDS, UDDS, and US06 operating conditions, respectively (Table 3 ), significantly exceeding the performance of comparative models. Additionally, the feature extraction module contributes to an overall performance improvement of approximately 2.04% (Table 4 ). These findings indicate that the proposed method exhibits strong robustness (Table 4 and Figure 11 ) and offers a promising approach for enhancing the safety of NEVs. Conclusions This study proposes a novel method for diagnosing ISC faults in battery packs by integrating an improved battery phase plane approach with a Conformer-BiGRU network. The main contributions are as follows: First, the improved battery phase plane method enhances the separability of different fault states in two-dimensional space by incorporating both voltage and its first-order differential distribution, addressing the limitations of conventional one-dimensional feature extraction. Second, a hybrid Conformer-BiGRU architecture is developed, in which the Conformer module captures local discharge characteristics, while the BiGRU module models temporal dependencies. These features are integrated through a feature coupling unit to achieve cross-level feature fusion. Third, an experimental ISC fault dataset with varying severity levels is established using a self-built testing platform. Experimental results demonstrate average diagnostic accuracy, recall, and F1-scores of 91.26%, 85.17%, and 88.09%, respectively, across three international driving cycles. Although laboratory testing verifies the effectiveness of the proposed method, real-world application requires targeted optimization. This includes adapting BiGRU parameters during the migration of the Improved Battery Phase Plane (IBPP) module and refining the Conformer’s local perception weights through transfer learning to enhance feature decoupling. Future research focuses on improving diagnostic performance under concurrent fault scenarios to enhance engineering robustness in complex operating conditions.
Available online , doi: 10.11999/JEIT241145
Abstract:
Objective Ultra-WideBand (UWB) ranging in confined indoor environments is prone to coarse ranging errors and Gaussian noise, which substantially degrade localization accuracy for both static and dynamic targets, even under Line-of-Sight (LOS) conditions. In addition, during indoor operations of wheeled vehicles, obstacles often obstruct the LOS between onboard UWB tags and anchors, resulting in Non-Line-of-Sight (NLOS) propagation. NLOS-induced interference results in abrupt fluctuations in range measurements, which severely compromise the estimation of the vehicle’s motion state. Methods To address these challenges, this study proposes a Gaussian Process Regression (GPR)-calibrated indoor UWB/Inertial Measurement Unit (IMU) fusion localization algorithm (GIU-EKF). The proposed approach offers two key features. First, a UWB ranging error model for the entire two-dimensional localization area is established by collecting UWB measurements at a limited set of reference points under LOS conditions. This model is applied to correct LOS-related ranging biases. Second, by leveraging the low short-term drift characteristics of inertial measurements, the algorithm fuses IMU and UWB data to mitigate NLOS ranging errors. Results and Discussions Under LOS conditions, a GPR-based error calibration model is constructed by sampling and analyzing UWB ranging deviations at known reference coordinates. This model captures the statistical association between two-dimensional spatial positions and the corresponding ranging errors. For any queried location, the model generates a set of probabilistic range estimates, with the final range value obtained by weighting nearby sample points according to their normalized likelihoods. This enables real-time suppression of LOS-related ranging errors. A threshold-based detection mechanism identifies NLOS conditions when the UWB range increment exceeds a predefined threshold. In NLOS scenarios, a subordinate Extended Kalman Filter (EKF) fuses UWB range data with short-term IMU measurements to compensate for NLOS-induced ranging errors during motion. The corrected range data are then incorporated into a primary EKF to update the vehicle’s motion state estimation. Experimental results demonstrate that the proposed GPR-based coarse error correction reduces localization errors by 64% and 58% for static and dynamic tags under LOS conditions, respectively. In three representative NLOS scenarios, the GIU-EKF algorithm maintains reliable motion state estimation for low-speed targets, achieving an average localization error of 7.5 cm. For tags moving at speeds between 0.2 m/s and 0.8 m/s, localization errors remain below 10 cm. The robustness of the proposed algorithm under extreme conditions is also validated. As shown in Section 4.3.2, the algorithm maintains stable velocity vector estimation even when the wheeled vehicle experiences alternating occlusions between single-anchor and multi-anchor configurations. Under low-speed conditions (2.2 cm/s), the localization error remains as low as 6.7 cm. Section 4.3.3 further verifies the algorithm’s convergence capability under large initial deviations. When subjected to initial heading errors between 5° and 50°, or a combined 1.5-meter position offset and 10° heading deviation, the proposed method consistently converges to the true position within a 2-meter travel distance. Conclusions This study presents a GPR-assisted indoor UWB/IMU fusion localization algorithm. By independently suppressing LOS and NLOS ranging errors from four UWB anchors, the proposed approach enhances localization accuracy in complex indoor environments. Under LOS conditions, a GPR-based correction mitigates coarse UWB ranging errors. In NLOS scenarios, short-term inertial estimates compensate for anomalous UWB measurements. A subordinate EKF adaptively balances observation uncertainties from the two sensing modalities, maintaining motion state observability when the tag moves slowly in confined spaces. This design avoids long-term drift accumulation, which is often observed in tightly coupled systems that treat IMU data as a strong prior, particularly when using low-cost inertial sensors. Experimental results demonstrate that the proposed algorithm achieves sub-10 cm localization accuracy under both LOS and NLOS conditions. During low-speed operations, the system maintains convergence of both velocity and position estimates. Furthermore, even with significant initial motion state biases, the algorithm consistently converges to the true trajectory. These findings indicate that the proposed method effectively meets the operational requirements of mobile robots in narrow indoor environments. However, practical application still requires further attention to two key aspects: efficient and autonomous collection of coordinate samples for GPR model training, and integration of real-time localization outputs with vehicle path planning and motion control systems.
Available online , doi: 10.11999/JEIT250026
Abstract:
Objective With the rapid growth of data volume at the edge of the Internet of Things (IoT), traditional centralized computing architectures are inadequate to meet real-time processing requirements. Due to the limited computing and storage capabilities of IoT devices, data overflow frequently occurs when handling large volumes of information. Meanwhile, the reliance on battery power exacerbates energy shortages, further hindering continuous operation and data processing. Unmanned Aerial Vehicles (UAVs), with their flexible deployment capabilities, are increasingly being integrated into distributed computing environments to improve IoT data processing efficiency. However, the stochastic and dynamic nature of IoT user demands presents significant challenges for existing resource scheduling schemes, which struggle to effectively coordinate UAV deployments. Moreover, most studies focus on single-objective optimization, making it difficult to simultaneously balance energy harvesting, energy consumption, system latency, and data transmission rates under complex environmental conditions. To address these challenges, this paper proposes an optimization framework for a UAV-assisted, wireless-powered Mobile Edge Computing (MEC) system based on an improved Multi-Objective Deep Deterministic Policy Gradient (MODDPG) algorithm. The proposed method jointly optimizes task offloading, energy harvesting, flying energy consumption, and system latency, enhancing the overall performance and feasibility of IoT systems. Methods This paper designs a UAV-assisted, wireless-powered MEC system model, where the UAV follows a “fly-hover-communicate” protocol and operates in full-duplex mode during hovering to simultaneously perform data collection and energy transmission. The system model integrates a propulsion energy consumption model and a nonlinear energy harvesting model, formulating a multi-objective optimization problem based on task generation, energy state, and wireless channel conditions of IoT devices. To address this optimization problem, an improved MODDPG algorithm is proposed. A multi-dimensional reward function is constructed to maximize the data transmission rate and total harvested energy while minimizing system energy consumption and task offloading latency within a unified reinforcement learning framework. The agent continuously interacts with the dynamic environment to optimize the UAV’s flight trajectory, task offloading ratio, and energy transmission strategy. The proposed method is implemented and validated through extensive simulations conducted on the Python platform under various experimental settings. Results and Discussions To evaluate the performance of the proposed algorithm, comparative experiments are conducted against four other control strategies. The impact of different data collection coverage radii on the proposed strategy is analyzed (Fig. 3 , Fig. 4 ). In terms of total data transmission rate, the \begin{document}${P_{\rm{MODDPG}}}$\end{document} Fig. 3 (a)). Regarding total harvested energy, \begin{document}${P_{\rm{MODDPG}}}$\end{document} Fig. 3 (b)), demonstrating its capability to enhance energy transmission coverage and system efficiency. In terms of system energy consumption, the \begin{document}${P_{{V_{\max }}}}$\end{document} \begin{document}${P_{\rm{MODDPG}}}$\end{document} Fig. 3 (c)). For average latency, \begin{document}${P_{\rm{MODDPG}}}$\end{document} Fig. 3 (d)). In terms of service performance, \begin{document}${P_{\rm{MODDPG}}}$\end{document} Fig. 4 (a), Fig. 4 (b), Fig. 4 (c), Fig. 4 (d)). In experiments with varying IoT device densities (Fig. 5 , Fig. 6 ), \begin{document}${P_{\rm{MODDPG}}}$\end{document} \begin{document}${P_{\rm{MODDPG}}}$\end{document} Fig. 7 ) indicate that \begin{document}${P_{\rm{MODDPG}}}$\end{document} \begin{document}${P_{\rm{MODDPG}}}$\end{document} \begin{document}${P_{\rm{MODDPG}}}$\end{document} Conclusions This paper addresses the critical challenges of energy limitations, data overflow, and high latency in IoT environments by proposing an optimization framework for a UAV-assisted wireless-powered MEC system, which integrates UAV, MEC, and Wireless Power Transfer (WPT) technologies. In the proposed system, IoT devices’ data upload demands are updated in real time, with the UAV sequentially accessing each device based on the priority of its demands using a "fly-hover-communicate" protocol. An improved MODDPG algorithm, based on deep reinforcement learning, is introduced to jointly optimize data transmission rate, energy harvesting, energy consumption, and system latency. Training results demonstrate that, under all optimization scenarios, the proposed scheme consistently achieves the highest total harvested energy while simultaneously balancing the other three optimization objectives. Compared to other baseline strategies, the proposed method exhibits better adaptability by dynamically adjusting to environmental changes and varying device priorities, ultimately achieving coordinated multi-objective optimization and superior performance across different conditions. Future research will focus on extending this work to address multi-UAV cooperative task allocation, resource management, energy harvesting coordination, and multi-UAV trajectory planning.
Available online , doi: 10.11999/JEIT250135
Abstract:
Objective The rapid development of 5G and the Internet of Vehicles (IoV) has accelerated the demand for intelligent services and large-scale data processing. However, limited computational capacity at vehicle terminals and frequent topology changes due to high mobility reduce transmission efficiency and reliability. While current task offloading and resource allocation methods meet basic processing needs, they fall short in supporting fine-grained task segmentation and in adapting to the dynamic characteristics of vehicular networks. To address these limitations, this study proposes an optimization approach for task segmentation and computing resource allocation based on Reinforcement Learning (RL). By combining the time-series modeling capabilities of advanced Deep Learning (DL) models with the resource scheduling flexibility of a Multi-Agent Deep Reinforcement Learning (MADRL) algorithm, this method enables intelligent, prediction-driven task segmentation and allocation. It supports decoupled processing and multi-objective optimization of latency and resource use. The proposed framework enhances offloading efficiency and resource utilization in Vehicular Edge Computing (VEC) environments and provides theoretical support for real-time resource management in highly dynamic vehicular networks. Methods The proposed method integrates vehicle trajectory prediction, dynamic task segmentation, and adaptive resource scheduling. For trajectory prediction, historical movement data are preprocessed through trajectory mapping. A Transformer-based model captures long-range temporal dependencies to achieve accurate path prediction. Based on predicted routes and estimated dwell times in different edge zones, a segmentation strategy divides tasks into subtasks to distribute load evenly across edge servers. The resource allocation challenge under this segmentation strategy is modeled as a Markov Decision Process (MDP), with each edge server acting as an agent that interacts with its environment. The state space includes task sizes, server loads, and available resources, while the action space defines the scheduling decisions each agent may select. The reward function is designed to minimize delay and improve efficiency, promoting cooperative behavior across agents. Through continual environmental feedback, the MADRL framework adaptively adjusts resource allocation in response to real-time task demands and server workloads. Results and Discussions The Transformer-based path prediction model outperforms baseline models (Table 1 ), achieving a Mean Squared Error (MSE) of 0.0116 , substantially lower than that of LSTM (0.0246 ) and BiLSTM (0.0323 ). To identify the optimal prediction horizon, the model is evaluated across different prediction steps (Fig. 5 ). The reward increases from 2 to 5 steps but declines beyond 5 due to increased transmission delays caused by frequent edge node handovers. Thus, 5-step prediction is adopted as the optimal setting. The proposed algorithm is assessed against three baseline strategies: binary offloading, random segmentation, and alternating convex search. Under a 5-step horizon and a five-task vehicle scenario (Fig. 6 ), the proposed method reduces average task latency by 54.1% compared with random segmentation and by 16.5% compared with alternating convex search. By tuning the weight coefficient (Fig. 7 ), the method demonstrates balanced performance across latency and resource efficiency objectives. Specifically, at a coefficient of 0.8, it achieves a convergence reward of 39.224, exceeding that of alternating convex search (35.872) by 9.4%. Scalability is evaluated under varying vehicle numbers (Fig. 8 ). The proposed method consistently yields the highest convergence reward across all cases. With four vehicles, it reaches a reward of 41.059, 7.3% higher than alternating convex search (38.277). With seven vehicles, it maintains a reward of 35.630, exceeding the baseline’s 32.524 by 9.6%. Overall, the proposed method exhibits superior latency reduction, higher resource efficiency, and better adaptability across different vehicle densities, validating its effectiveness and scalability for task offloading and resource allocation in VEC systems. Conclusions This study proposes a task segmentation and computing resource allocation method tailored for VEC scenarios. By exploiting the time-series modeling capacity of Transformer networks, the accuracy of vehicle trajectory prediction is enhanced. A dynamic task segmentation strategy is then applied to optimize workload distribution across Mobile Edge Computing (MEC) servers. The use of a MADRL-based cooperative resource allocation approach effectively reduces task latency while improving resource use. Simulation results confirm the method’s effectiveness in minimizing processing delay and enhancing system efficiency. Future research will explore the role of task prioritization in resource allocation and investigate strategies to sustain performance under increased vehicle counts and task complexity in large-scale deployments.
Available online , doi: 10.11999/JEIT250141
Abstract:
Objective Human activities in shallow-sea regions have increased with the progressive development and utilization of marine environments. However, interference from noise sources such as water currents, vessels, and marine organisms substantially reduces the Signal-to-Noise Ratio (SNR) of received signals, leading to performance degradation in conventional Direction of Arrival (DOA) estimation algorithms. These limitations affect accurate target localization and detection, which are essential for underwater acoustic applications. This paper proposes a method that combines Wiener filtering with deep learning, specifically an improved Convolutional Neural Network (CNN), to enhance the robustness and accuracy of DOA estimation in shallow-sea environments by addressing challenges such as noise interference and grid mismatch. Methods The proposed algorithm integrates Wiener filtering and deep learning to optimize DOA estimation. First, Wiener filtering is applied to the covariance matrix of received signals to reduce noise. Considering the complexity of underwater acoustic environments, this preprocessing step is essential for preserving spatial signal features and enhancing the effectiveness of network training. Second, an improved CNN architecture is designed to perform both classification and regression tasks, enabling accurate DOA angle estimation while correcting off-grid errors. A fractional label correction strategy is introduced to mitigate grid mismatch, allowing prediction errors to be compensated and estimated angles to align more closely with true values. The network is trained using a large-scale dataset of simulated underwater acoustic signals, and its feasibility is verified through real-world sea trial data. Results and Discussions The proposed method is validated using both simulation data and sea trial data, demonstrating superior performance under low SNR conditions. Simulation results show that incorporating Wiener filtering improves overall network performance by 25.20% (Fig. 4 ). The proposed algorithm achieves lower estimation errors in low SNR environments (Fig. 4 , Fig. 5 ). Compared with the MUSIC and ESPRIT algorithms, the Root Mean Square Error (RMSE) is reduced by 93.42% and 92.14%, respectively, at an SNR of –20 dB. Moreover, as the SNR increases, the algorithm exhibits a gradual reduction in estimation error (Fig. 6 ). In sea trial experiments, the algorithm accurately identifies target azimuths and achieves lower estimation errors compared to conventional methods (Fig. 9 , Table 1 ). These results indicate that the proposed method meets the requirements for robustness and accuracy in practical underwater acoustic applications. Conclusions This paper proposes a method for direction estimation in shallow-water environments that integrates Wiener filtering with a deep learning-based CNN to address the performance degradation caused by low SNR conditions in conventional algorithms. The combination of noise reduction preprocessing with CNN model training enhances both network efficiency and estimation accuracy. Simulation and sea trial experiments yield the following results: (1) Overall network performance is improved by 25.20% through Wiener filtering optimization; (2) The improved binary cross-entropy loss function enables the network to perform both classification and regression tasks for DOA estimation; (3) The algorithm demonstrates higher robustness to noise interference and grid mismatch, particularly under low SNR and limited snapshot conditions, making it suitable for practical deployment. However, the network is trained using datasets with known source numbers. Future research will focus on network designs that accommodate more diverse source conditions, including blind source scenarios and adaptive noise reduction models.
Available online , doi: 10.11999/JEIT250224
Abstract:
Objective Image Super-Resolution (SR) is a critical computer vision task aimed at reconstructing High-Resolution (HR) images from Low-Resolution (LR) inputs, with broad applications in fields such as medical imaging and satellite imaging. Recently, diffusion-based SR methods have attracted significant attention due to their generative capability and strong performance in restoring fine image details. Existing diffusion model-based SR approaches have demonstrated potential in recovering textures and structures, with some methods focusing on spatial domain features and others utilizing frequency domain information. Spatial domain features aid in reconstructing overall structural information, whereas frequency domain decomposition separates images into amplitude and phase components across frequencies. High-frequency components capture details, textures, and edges, whereas low-frequency components describe smooth structures. Compared to purely spatial modeling, frequency domain features improve the aggregation of dispersed high-frequency information, enhancing the representation of image textures and details. However, current frequency domain SR methods still show limitations in restoring high-frequency details, with blurring or distortion persisting in some scenarios. To address these challenges, this study proposes SR-FDN, a SR reconstruction network based on a frequency-domain diffusion model. Methods SR-FDN leverages the distribution mapping capability of diffusion models to improve image reconstruction. The proposed network integrates spatial and frequency domain features to enhance high-frequency detail restoration. Two constraints guide the model design: (1) The network must generate plausible HR images conditioned solely on LR inputs, which serve as the primary source of structural information, ensuring high-fidelity reconstruction. (2) The model should balance structural reconstruction with enhanced detail restoration. To achieve this, a dual-branch frequency domain attention mechanism is introduced. A portion of the features undergoes Fourier transform for frequency domain processing, where high-frequency information is emphasized through self-attention. The remaining features adjust frequency domain weights before being combined with spatial domain representations. Skip connections in the U-Net architecture preserve LR structural information while enhancing frequency domain details, improving both structural and textural reconstruction. Wavelet downsampling replaces conventional convolutional downsampling within the U-Net noise predictor, reducing spatial resolution while retaining more detailed information. In addition, a Fourier frequency domain loss function constrains amplitude and phase components of the reconstructed image, further enhancing high-frequency detail recovery. To guide the generative process, additional image priors are incorporated, enabling the diffusion model to restore textures consistent with semantic category features. Results and Discussions The results of SR-FDN on face datasets and general datasets for 4× and 8× SR (Table 1 , Table 2 , Table 3 ) demonstrate that the proposed method achieves strong performance across objective evaluation metrics. These results indicate that SR-FDN can effectively restore image detail information while better preserving structural and textural features. A comparison of iteration counts between SR-FDN and two diffusion-based methods (Fig. 2 ) shows that SR-FDN can reconstruct higher-quality images with fewer iterations. Despite the reduced number of iterations, SR-FDN maintains high-fidelity reconstruction, reflecting its ability to lower computational overhead without compromising image quality. To further verify the effectiveness of the proposed SR-FDN, visual comparisons on the FFHQ dataset (Fig. 3 ) and the DIV2K dataset (Fig. 4 ) are presented. The results show that SR-FDN offers clearer and more detailed image reconstruction, particularly in high-frequency regions such as facial features and hair textures. Ablation experiments (Table 5 ) and feature visualization results (Fig. 5 ) are also provided. These results confirm that the proposed dual-branch frequency domain design and the Fourier domain loss function significantly contribute to improved restoration of fine details. Conclusions This study proposes SR-FDN, a diffusion-based SR reconstruction model that integrates frequency domain information to enhance detail restoration. The SR-FDN model incorporates a dual-branch frequency domain attention mechanism, which adaptively reinforces high-frequency components, effectively addressing the limitations of conventional methods in recovering edge structures and texture details. In addition, SR-FDN employs wavelet downsampling to preserve informative features while reducing spatial resolution, and introduces a frequency domain loss function that constrains amplitude and phase information, enabling more effective fusion of frequency and spatial domain features. This design substantially enhances the model’s ability to recover high-frequency details. Extensive experiments on benchmark datasets demonstrate that SR-FDN reconstructs images with superior quality and richer details, exhibiting clear advantages in both qualitative and quantitative evaluations.
Available online , doi: 10.11999/JEIT250252
Abstract:
Objective Maritime wireless communication networks face significant challenges, including dynamic topology drift, large-scale channel fading, and cross-layer resource competition. These factors hinder the effectiveness of traditional single-layer resource allocation methods, which struggle to maintain the balance between high-quality communications and heterogeneous service demands under limited network resources. This results in degraded Quality of Service (QoS) and uneven service guarantees. To address these challenges, this study proposes a cross-layer collaborative resource allocation framework that achieves balanced enhancement of system throughput and QoS assurance through closed-loop optimization, integrating physical-layer power control with network-layer service scheduling. First, a cross-layer wireless network transmission model is established based on the coupling mechanism between physical-layer channel capacity and transport-layer TCP throughput. Second, a dual-threshold water-level adjustment mechanism, incorporating both Signal-to-Noise Ratio (SNR) and QoS metrics, is introduced into the classical water-filling framework, yielding a QoS-aware dual-threshold water-filling algorithm. This approach strategically trades controlled throughput loss for improved QoS of high-priority services. Furthermore, a conflict resolution strategy optimization filter with dual-channel feature decoupling is designed within a twin deep reinforcement learning framework to enable real-time, adaptive node-service dynamic matching. Simulation results demonstrate that the proposed framework improves average QoS scores by 9.51% and increases critical service completion by 1.3%, while maintaining system throughput degradation within 10%. Methods This study advances through three main components: theoretical modeling, algorithm design, and system implementation, forming a comprehensive technical system. First, leveraging the coupling relationship between physical-layer channel capacity and transport-layer Transmission Control Protocol (TCP) throughput, a cross-layer joint optimization model integrating power allocation and service scheduling is established. Through mathematical derivation, the model reveals the nonlinear mapping between wireless resources and service demands, unifying traditionally independent power control and service scheduling within a non-convex optimization structure, thus providing a theoretical foundation for algorithm development. Second, the proposed dynamic dual-threshold water-filling algorithm incorporates a dual-regulation mechanism based on SNR and QoS levels. A joint mapping function is designed to enable flexible, demand-driven power allocation, enhancing system adaptability. Finally, a twin deep reinforcement learning framework is constructed, which achieves independent modeling of node mobility patterns and service demand characteristics through a dual-channel feature decoupling mechanism. A dynamic adjustment mechanism is embedded within the strategy optimization filter, improving critical service allocation success rates while controlling system throughput loss. This approach strengthens system resilience to the dynamic, complex maritime environment. Results and Discussions Comparative ablation experiments demonstrate that the dynamic dual-threshold water-filling algorithm within the proposed framework achieves a 9.51% improvement in QoS score relative to conventional water-filling methods. Furthermore, the Domain Knowledge-Enhanced Siamese DRL (DKES-DRL) method exceeds the Siamese DRL approach by 3.25% (Fig. 6 ), albeit at the expense of a 9.3% reduction in the system’s maximum throughput (Fig. 7 ). The average number of completed transactions exceeds that achieved by the traditional water-filling algorithm by 1.3% (Fig. 8 , Fig. 9 ). In addition, analysis of the effect of node density on system performance reveals that lower node density corresponds to a higher average QoS score (Fig. 10 ), indicating that the proposed framework maintains service quality more effectively under sparse network conditions. Conclusions To address the complex challenges of dynamic topology drift, multi-scale channel fading, and cross-layer resource contention in maritime wireless communication networks, this paper proposes a cross-layer collaborative joint resource allocation framework. By incorporating a closed-loop cross-layer optimization mechanism spanning the physical and network layers, the framework mitigates the imbalance between system throughput and QoS assurance that constrains traditional single-layer optimization approaches. The primary innovations of this work are reflected in three aspects: (1) Cross-layer modeling is applied to overcome the limitations of conventional hierarchical optimization, establishing a theoretical foundation for integrated power control and service scheduling. (2) A dual-dimensional water-level adjustment mechanism is proposed, extending the classical water-filling algorithm to accommodate QoS-driven resource allocation. (3) A knowledge-enhanced intelligent decision-making system is developed by integrating model-driven and data-driven methodologies within a deep reinforcement learning framework. Simulation results confirm that the proposed framework delivers robust performance in dynamic maritime channel conditions and heterogeneous traffic scenarios, demonstrating particular suitability for maritime emergency communication environments with stringent QoS requirements. Future research will focus on resolving engineering challenges associated with the practical deployment of the proposed framework.
Available online , doi: 10.11999/JEIT250241
Abstract:
Objective The globalization of Integrated Circuit (IC) design and increasing reliance on outsourcing have heightened the vulnerability of hardware supply chains to malicious modifications, such as hardware Trojans. These covert circuits may remain dormant until triggered, causing data leakage, system performance degradation, or physical damage. Detecting such threats is essential for safeguarding the security and reliability of semiconductor devices. Traditional side-channel detection methods based on power consumption or timing analysis often depend on manually designed features, which are sensitive to noise and lack generalizability across hardware platforms. Therefore, these techniques suffer from low detection accuracy and high false-positive rates under practical conditions. To address these limitations, this study proposes a deep learning-based side-channel detection method. By leveraging the ability of neural networks to automatically extract features from raw power signals, the proposed approach targets the identification of subtle anomalies associated with Trojan activation. The aim is to develop a robust, scalable detection solution applicable to real-world industrial scenarios. Methods The proposed detection framework integrates a hybrid deep learning architecture that combines a One-Dimensional Convolutional Neural Network (1D-CNN) with a Long Short-Term Memory (LSTM) network (Fig. 5 ). This architecture is designed to exploit the complementary advantages of CNNs and LSTMs for feature extraction. Specifically, the 1D-CNN component captures local spatial correlations within transient power traces, which are critical for detecting short-term fluctuations indicative of Trojan activity. The convolutional filters automatically learn edges, patterns, and shifts in signal magnitude, thereby reducing reliance on manual feature engineering. In parallel, the LSTM component is employed to model long-range temporal dependencies in the power signal sequence. Compared with conventional Recurrent Neural Networks (RNNs), LSTMs incorporate memory gates that enable selective retention or dismissal of past information, making them suitable for analyzing time-series data such as power traces. This enhances the framework’s ability to detect sequential patterns and context-dependent anomalies that may emerge over extended periods. The dataset comprises real-world transient power traces collected from fabricated Application-Specific Integrated Circuit (ASIC) chips, including both Trojan-free and Trojan-infected samples. Each power trace contains 125,000 sample points, capturing high-resolution dynamic power consumption under controlled activation scenarios. To reduce computational complexity and focus the model on signal segments most relevant to Trojan detection, a preprocessing step is applied. Specifically, windows of power data are extracted around the rising edges of the clock signal, where circuit state transitions are most likely to reveal Trojan-induced anomalies. This reduces the data dimensionality to 22,485 points per sample. To enhance the robustness of the model and mitigate overfitting, Gaussian noise is injected into the training data for data augmentation. This simulates realistic environmental and sensor-related noise conditions. The final dataset is divided into training, validation, and test sets in a 50%-25%-25% ratio, with balanced distributions of Trojan-free and Trojan-infected samples. Results and Discussions The experimental evaluation confirms the effectiveness of the proposed hybrid deep learning model for accurate and efficient hardware Trojan detection. By applying preprocessing to reduce input dimensionality, the training time is reduced by approximately an order of magnitude, substantially lowering computational requirements without compromising detection accuracy. The final model, trained using the RMSProp optimizer with a learning rate of 0.0005 and a batch size of 64, achieves a detection accuracy of 99.6% for the four-class classification task (Table 1 ). Analysis of the confusion matrix (Fig. 6 ) demonstrates that the model reliably distinguishes Trojan-free samples from three different types of Trojan-infected samples. Precision and recall rates exceed 99% across all classes, with minimal misclassification. The introduction of Gaussian noise during training further enhances the model’s generalization ability, ensuring stable performance on previously unseen test data. The macro-average F1-score reaches 99.6%, indicating balanced detection performance for all classes. In comparative evaluations with existing state-of-the-art methods, including Domain-Adversarial Neural Networks (DANN), Principal Component Analysis combined with LSTM (PCA-LSTM), and Siamese networks (Table 3 ), the proposed 1D-CNN-LSTM model consistently achieves superior accuracy and robustness. A key advantage is the model’s ability to process real-world measured power traces, rather than relying solely on simulated data. These results highlight the significance of combining spatial and temporal modeling for side-channel analysis and demonstrate the potential of deep learning techniques for hardware security applications. Nevertheless, the current experiments are conducted under ideal laboratory conditions with controlled data acquisition. Practical deployments are likely to encounter additional challenges, such as environmental fluctuations, measurement noise, and potential adversarial interference with power signals. Addressing these limitations remains an open research problem. Conclusions This paper proposes a deep learning-based hardware Trojan side-channel detection method that integrates a 1D-CNN-LSTM hybrid model to automatically extract and analyze features from power consumption signals. The method achieves substantial improvements in both detection efficiency and accuracy, supporting the feasibility of deep learning for hardware security applications. Future research will focus on addressing real-world challenges, including sensor noise, environmental variability, and adversarial attacks, as well as exploring semi-supervised or unsupervised learning to reduce reliance on labeled data. These findings provide a promising basis for enhancing the security and reliability of IC designs against hardware Trojan threats.
Available online , doi: 10.11999/JEIT250357
Abstract:
Significance Processor security is a cornerstone of computer system security, providing a trusted execution environment for upper-layer systems and applications. However, the increasing complexity of processor microarchitectures and the widespread integration of performance-driven optimization mechanisms have introduced significant security risks. These mechanisms, primarily designed to enhance performance and energy efficiency, often lack comprehensive security evaluation, thereby expanding the potential attack surface. Therefore, numerous microarchitectural security vulnerabilities have emerged, presenting critical challenges in architectural security research. Progress Although recent years have witnessed notable progress in the study of hardware vulnerabilities, several key issues remain unresolved. First, the landscape of hardware vulnerabilities is both diverse and complex, yet existing literature lacks a consistent and systematic classification framework. This gap complicates researchers’ efforts to understand, compare, and generalize vulnerability characteristics. Second, current studies predominantly focus on individual vulnerability discovery or specific attack implementations, with limited attention to modeling the full vulnerability lifecycle. A comprehensive research framework including vulnerability identification, attack instantiation, and exploitation is still lacking. One pressing challenge is how to efficiently and systematically convert potential vulnerabilities into practical, high-risk attack paths. In addition, unlike software vulnerabilities, hardware vulnerabilities are inherently more difficult to mitigate and impose higher defense costs. These characteristics highlight the need for a more structured and integrated approach to hardware vulnerability research. Contributions This paper systematically reviews and analyzes processor hardware vulnerabilities reported in major architecture security conferences and academic journals since 2010. It first outlines four primary methods for discovering hardware vulnerabilities and, based on prior studies, proposes a three-step attack model and a novel attack scenario framework. The paper then categorizes and describes existing hardware vulnerabilities according to their behavioral characteristics and consolidates eight evaluation metrics for side-channel vulnerabilities derived from related research. To assess the feasibility and scope of various attack types, representative vulnerabilities are selected for experimental validation across multiple processor platforms, with in-depth analysis of the results. In addition, the study provides a systematic evaluation of current defense and mitigation mechanisms for hardware vulnerabilities. Finally, it discusses future research directions from both offensive and defensive perspectives. Prospects Future research in processor hardware security is expected to focus on new attack surfaces introduced by increasingly diversified microarchitectural optimizations. Key areas will include the development of system-level collaborative defense mechanisms, automated verification tools, and integrated strategies to enhance awareness and precision in mitigating hardware-level information leakage risks.
Available online , doi: 10.11999/JEIT250237
Abstract:
Objective Silicon Carbide Metal Oxide Semiconductor Field Effect Transistors (SiC MOSFETs) are considered ideal power devices for power systems due to their ultra-low on-resistance and excellent switching characteristics. However, Conventional SiC MOSFETs (CON-MOS) present considerable limitations in reverse current applications. These limitations stem primarily from their reliance on the body diode during reverse conduction, which exhibits a high reverse conduction voltage, significant reverse recovery loss, and is prone to bipolar degradation during long-term operation, adversely affecting power system stability. Furthermore, CON-MOS devices in high-frequency switching circuits suffer from substantial switching losses, reducing overall circuit efficiency. A widely adopted solution is to connect an external Schottky Barrier Diode (SBD) in parallel to enhance reverse current continuity. However, this approach increases device size and parasitic capacitance. Moreover, Schottky contacts are susceptible to large reverse leakage currents at elevated temperatures. Although SiC MOSFETs with integrated SBDs mitigate issues caused by external parallel SBDs, they still exhibit degraded blocking characteristics and thermal stability. SiC MOSFETs incorporating integrated MOS channel diodes have also been proposed to improve reverse conduction performance. Nonetheless, these devices raise reliability concerns due to increased process complexity and the presence of an ultra-thin (10 nm) oxide layer. Alternative industry structures employing polysilicon heterojunctions with 4H-SiC epitaxial layers aim to enhance reverse current continuity in SiC MOSFETs. However, these structures exhibit high reverse leakage currents and lack avalanche capability, primarily because the heterojunction barrier is insufficient to sustain the full blocking voltage. Devices integrating channel accumulation diodes have demonstrated lower reverse conduction voltage and reduced reverse recovery charge. Nevertheless, the barrier height in these designs is highly sensitive to oxide layer thickness, imposing stricter process control requirements. To address these challenges, this paper proposes an Integrated Junction Field Effect Transistor (JFET) SiC MOSFET (IJ-MOS) structure. The IJ-MOS effectively reduces reverse recovery loss, eliminates bipolar degradation, and significantly improves performance and reliability in reverse continuous current applications. Methods Technology Computer-Aided Design (TCAD) simulations are conducted to evaluate the performance of the proposed and conventional structures. Several critical models are included in the simulation process, such as mobility saturation under high electric fields, Auger recombination, Okuto–Crowell impact ionization, bandgap narrowing, and incomplete ionization. Furthermore, the effects of traps and fixed charges at the SiC/SiO2 interface are also considered. This study proposes an IJ-MOS structure based on the physical mechanism of energy band bending within the space charge region of the PN junction. Specifically, the IJ-MOS blocks the intermediate channel region through PN junctions formed between the Current Spreading Layer (CSL) and the P-body and P-shield layers, respectively. The blocking mechanism relies on the PN junction inducing conduction band bending within the CSL layer, thereby raising the conduction band energy and forming a barrier region. During reverse conduction, the integrated JFET provides a unipolar, low-barrier reverse conduction path, which mitigates bipolar degradation and significantly reduces reverse recovery charge. This improves device performance and reliability under reverse current conditions. Furthermore, the IJ-MOS reduces gate-drain coupling by separating the polysilicon gate and extended oxide structure, while optimising the internal electric field distribution. These design features enhance the device’s blocking voltage capability, increasing the potential of IJ-MOS for high-voltage applications. Results and Discussions Simulation results indicate that, compared to CON-MOS, the proposed IJ-MOS structure significantly reduces the reverse conduction voltage from 2.92 V in CON-MOS to 1.83 V (Fig. 3 ). The reverse recovery charge is reduced by 43.6%, and the peak reverse recovery current decreases by 31.6%, while maintaining comparable forward conduction characteristics (Fig. 7 ). Furthermore, due to the split gate and extended oxide structure, the IJ-MOS exhibits a lower gate-drain capacitance, effectively reducing the coupling between the gate and drain. The extended oxide layer also improves the internal electric field distribution, leading to an increase in breakdown voltage and a 60% improvement in the Baliga Figure of Merit (BFOM) (Table 2 ). Benefiting from the lower gate-drain capacitance, the total switching loss of IJ-MOS is reduced by 24.2% compared to CON-MOS (Fig. 8 ). Conclusions This paper proposes a novel SiC MOSFET structure evaluated through TCAD simulation. The proposed IJ-MOS reduces reverse conduction voltage and significantly lowers reverse recovery charge, thereby enhancing reverse conduction performance. Since the barrier region of the integrated JFET is lower than that of the PN junction, the JFET conducts prior to the body diode, which effectively suppresses bipolar conduction of the body diode and avoids bipolar degradation. The primary carriers in the JFET are electrons rather than both electrons and holes, meaning only electrons must be removed during the reverse recovery process, reducing reverse recovery charge. Additionally, the split gate and extended oxide structure reduce gate-drain coupling, which decreases gate-drain capacitance, switching time, and overall switching losses. These advantages make the IJ-MOS a promising candidate for high-performance power electronics applications.
Available online , doi: 10.11999/JEIT250200
Abstract:
Objective The growing demand for maritime target detection and recognition has made multi-source information fusion a critical area of research. Different sensing modalities including radar, visible-light imaging, and infrared imaging offer complementary information that can improve detection and classification. However, the correlation among heterogeneous features extracted from these sources remains insufficiently understood. In addition, the effects of observational conditions on feature stability and discriminability needs further investigation. This study investigates the intrinsic relationships among multi-source features, evaluates their robustness under varying conditions, and provides theoretical support for effective multi-source feature fusion in maritime target detection. Methods Nine physically interpretable features are extracted across three categories: radar features (radial dimension, number of peaks, position distribution entropy, cross-range dimension, and relative average amplitude), visible image features (number of edges and horizontal projected width), and infrared image features (high-temperature connected component count and thermal texture energy). To ensure accurate feature extraction, data preprocessing consists of cleaning each compressed dataset. Radar data with excessively low signal-to-noise ratios and images with extensive occlusion are excluded. For dataset construction, radar echo data are visualized frame by frame, and a subset of radar, visible-light, and infrared images is manually annotated using LabelImg. Targets are classified into five types: passenger ships, dry cargo ships, container ships, tugboats, and search-and-rescue vessels. Based on these annotations, deep learning models are independently trained for each modality to automate annotation, and the results are manually validated to ensure quality. A standardized target dataset is then constructed by integrating the manually and automatically labeled data. Radar echo data are temporally aligned with visible-light and infrared images using prior time synchronization information. Features are extracted from each modality, and inter-feature correlations are analyzed. Spearman correlation coefficients are used to quantify relationships, and hypothesis testing is conducted to assess significance, revealing intrinsic associations among multi-source features. Results and Discussions Comparative analysis indicates that the correlation between radar echo and image features is strongly affected by feature attributes. Size-related features show stronger correlations, reflecting greater stability for multi-source data fusion, whereas structural features are more sensitive to observation conditions and exhibit weaker correlations. External factors including target motion state, ship type, and radar polarization mode also influence feature extraction and intermodal correlation. When targets are anchored, posture remains stable and motion blur is reduced, strengthening the correlation between radar structural features and image features. Larger vessels, such as container ships and passenger ships, benefit from multiple scattering centers and larger physical dimensions, which enhance feature extraction and intermodal correlation. In contrast, smaller vessels, such as tugboats and search-and-rescue boats, exhibit irregular structures and weaker radar backscatter, leading to lower correlations. The HH polarization mode, being less sensitive to background clutter, improves radar feature stability across various target types and enhances alignment with image features. Image feature stability also varies by modality: visible-light imaging is effective for extracting structural features, such as contours and edges, but is sensitive to illumination and occlusion; infrared imaging offers more stable size-related features and performs robustly in complex and low-visibility environments. These results highlight the complementary properties of multi-source features and establish a theoretical basis for their integration, supporting improved maritime target detection and classification. Conclusions This study demonstrates the complementary characteristics of multi-source features and their potential to improve maritime target detection and recognition. By analyzing feature correlations and stability across varying observational conditions, the results provide a theoretical foundation for refining multi-source fusion strategies. These insights support the development of more robust and reliable detection algorithms, contributing to enhanced situational awareness in maritime surveillance and defense.
Available online , doi: 10.11999/JEIT250169
Abstract:
Objective As Radio Frequency (RF) spectrum congestion intensifies and electromagnetic interference incidents occur more frequently, the reliable operation of the Global Navigation Satellite System (GNSS) is increasingly threatened. To ensure GNSS functionality, interference sources must be accurately monitored and localized. Conventional localization methods are constrained by the limited aperture of physical antenna arrays and often incur high deployment costs. With the gradual opening of low-altitude airspace, small Unmanned Aerial Vehicles (UAVs) are increasingly used as platforms for remote sensing, electronic reconnaissance, and communication tasks, offering a practical alternative for GNSS interference localization. Passive Synthetic Aperture (PSA) techniques have emerged as a solution to overcome the aperture limitations of physical arrays and are well suited for integration with UAV platforms. In this study, PSA technology is combined with a UAV-based system to locate GNSS interference sources. A unified signal model is established to describe various interference types. Based on this model, a slant-range-accurate Range-Doppler (RD) algorithm is derived and further integrated with the Back Projection (BP) algorithm to perform joint localization. This combined RD–BP approach enhances positioning accuracy while reducing computational complexity, demonstrating the feasibility and efficiency of the proposed UAV-based PSA localization framework. Methods This approach integrates a RD positioning algorithm based on a precise slant range expression with a BP algorithm. First, an accurate slant range expression is derived using the interference source direction and Doppler frequency. Applying this expression and the principle of stationary phase, the signal is transformed into the RD domain. Multiple matched filters are then constructed in the Doppler domain using the range gate. The outputs of these filters are converted into the range-azimuth domain for peak detection, yielding a coarse estimate of the interference source location. However, this initial estimate is susceptible to errors due to factors such as platform sampling rate and azimuth sampling interval. To refine the estimate, the BP algorithm is employed for fine positioning. A grid is defined around the coarse estimate, and each grid point is used to compute the projected signal. These projected signals are coherently accumulated with the received signals and integrated along the azimuth direction. Peak searching is then performed on the accumulated results to obtain the final, high-precision localization result. Results and Discussions Simulation results validate the effectiveness and excellent performance of the proposed RD-BP algorithm. As shown in (Fig. 7 ), (Fig. 10 ), and (Fig. 13 ), the algorithm successfully localizes interference sources after preprocessing for narrowband interference, Linear Frequency Modulated (LFM) interference, and spoofing interference. These results indicate the algorithm’s broad applicability across various interference types. (Fig. 14 ) illustrates the Root Mean Square Error (RMSE) under two scenarios in which the interference source is either close or distant. In both cases, RMSE decreases as the Signal-to-Noise Ratio (SNR) increases. When the source is nearby, RMSE changes slowly, indicating stable performance. When the source is distant, the algorithm maintains strong performance at higher SNRs. (Fig. 15 ) shows that under SNR conditions of –10 dB and 15 dB, RMSE increases with target distance. However, the RD-BP algorithm consistently outperforms other methods in accuracy, demonstrating its robustness and adaptability across varying distances. (Fig. 16 ) further confirms that RMSE stabilizes as the synthetic aperture length increases under both –10 dB and 15 dB SNR conditions. When the aperture length exceeds 100 m, the RD-BP algorithm achieves superior performance relative to other methods and approaches the Cramér–Rao Lower Bound (CRLB), indicating near-optimal estimation accuracy. (Table 1 ) compares the computational and localization performance of the proposed algorithm with that of the RD algorithm alone. While the RD algorithm is sensitive to platform sampling frequency, flight velocity, and other operational parameters, the RD-BP algorithm mitigates these limitations. It improves localization accuracy while maintaining manageable computational complexity, offering an effective trade-off between precision and efficiency. Conclusions This study addresses the problem of locating GNSS interference sources using low-altitude, low-speed UAV platforms. A localization method based on single-antenna synthetic aperture technology is proposed. The study begins by categorizing different types of GNSS interference and their respective preprocessing strategies. An RD algorithm is then derived based on the precise slant range representation, leveraging the relative direction of the interference source with respect to the UAV to achieve coarse localization. To address the accuracy limitations inherent in the RD algorithm due to initial condition constraints, an improved approach is proposed by incorporating the BP algorithm. This enhancement enables refined localization within a narrowed search region. Simulation results confirm that the proposed algorithm can reliably localize common GNSS interference sources under various interference conditions. Compared to conventional methods such as array antenna direction finding, the proposed technique requires only a single antenna mounted on the UAV platform, thereby increasing system flexibility and reducing both cost and design complexity. This demonstrates the feasibility of the method for rapid and efficient localization of GNSS interference sources.
Available online , doi: 10.11999/JEIT250309
Abstract:
Objective Frequency Selective Surfaces (FSS), as artificial ElectroMagnetic (EM) periodic structures, regulate the transmission and reflection of EM waves. Radomes integrating FSS can protect antennas, preserve the aerodynamic profile of radio-frequency systems, shape spatial scattering field distributions, and suppress backward Radar Cross Section (RCS). However, when illuminated by multiple radars, such radomes often fail to maintain low detectability due to their inability to achieve bistatic low RCS. Recent efforts have focused on developing absorptive structures based on FSS, where active FSS-based absorbers offer adaptive tunability across frequency and time domains. Nonetheless, achieving absorption in the P-band remains challenging due to the inherent limitations of existing dielectric materials. While FSS bandpass properties are frequently employed in radomes and the tunability of active FSS supports the design of reconfigurable absorbers, the two functionalities have largely been pursued independently, resulting in limited multifunctional surface designs. This study proposes a P-band ultra-thin absorber using FSS composed of cascaded unit cells with gradually curved meander lines. By exploiting the distinct equivalent circuit characteristics of absorbing and transmitting FSS structures, an integrated system is developed that enables both EM wave transmission and tunable wideband absorption in the P-band. Methods This paper proposes a novel design method for a dual-polarized, ultra-thin absorptive-transmissive EM surface element operating in the P-band, based on the FSS technique. The method uses cascaded elements with a gradient-bending structure to increase the effective current path length and incorporates lumped components to achieve wideband tunable absorption at low frequencies. By analyzing the equivalent circuit characteristics of both absorptive and transmissive FSS-based elements, an integrated absorptive-transmissive structure is developed. The difference in their equivalent circuits effectively suppresses mutual coupling, enabling the relatively independent design of absorptive and transmissive functions. To demonstrate this approach, a dual-polarized ultra-thin EM surface element is designed that simultaneously exhibits high transmittance and tunable wideband absorptivity. The step-by-step design process is presented, and the operating mechanism of the proposed element is thoroughly analyzed. Results and Discussions Both simulation and experimental results confirm that the proposed integrated element achieves dual-polarized absorptive performance in the P-band and dual-polarized transmissive performance in the C-band. The element features an ultra-thin profile, requires few lumped components, and exhibits a broad operational bandwidth. Notably, the proposed method combines equivalent circuit modeling with field-based analysis to facilitate the design of multifunctional EM surfaces, thereby streamlining the integration of absorptive and transmissive functionalities within a single structure. Conclusions Structural absorbers face a fundamental trade-off between achieving efficient low-frequency absorption and maintaining a low profile or lightweight design, making the development of P-band absorbing surfaces particularly challenging. FSS, commonly used in radomes, also offer potential for tunable absorber design. This study integrates both functionalities to develop a multifunctional EM surface capable of simultaneous wave absorption and transmission, based on an FSS architecture. When irradiated from one direction, the surface achieves absorptivity above 0.9 across 0.34～1.1 GHz. When irradiated from the opposite direction, it exhibits transmittivity exceeding 0.8 over 4.26～4.48 GHz. These two functions operate with relative independence. The proposed structure features a wide operational bandwidth, ultra-thin profile, and minimal reliance on electronic components. The method enables not only effective P-band absorption but also the integrated design of multifunctional EM surfaces. It offers strong scalability and holds significant potential for future applications.
Available online , doi: 10.11999/JEIT250301
Abstract:
Objective In complex dynamic environments such as industrial parks and urban roads, inspection robots depend heavily on visual Simultaneous Localization And Mapping (SLAM) systems. However, the presence of moving objects often causes feature drift and map degradation, reducing SLAM performance. Furthermore, conventional semantic segmentation models typically require extensive computational resources, rendering them unsuitable for embedded platforms with limited processing capabilities, thereby constraining SLAM deployment in autonomous inspection tasks. To address these challenges, this study proposes a lightweight semantic visual SLAM framework designed for inspection robots operating in dynamic environments. The framework incorporates a semantic segmentation-based dynamic feature rejection method to achieve real-time identification of dynamic regions at low computational cost, thereby improving SLAM robustness and mapping accuracy. Methods Building upon the 11th generation lightweight YOLO segmentation model (YOLOv11n-seg), a systematic lightweight redesign is implemented. to enhance performance under constrained computational resources. First, the original neck is replaced with DyCANet, a lightweight multi-scale feature fusion module that integrates dynamic point sampling and channel attention to improve semantic representation and boundary segmentation. DyCANet combines DySample, a dynamic upsampling operator that performs content-aware spatial sampling with minimal overhead, and ChannelAttention_HSFPN, a hierarchical attention structure that strengthens multi-scale integration and highlights critical semantic cues, particularly for small or occluded objects in complex scenes. Second, a Dynamic Convolution module (DynamicConv) is embedded into all C3k2 modules to enhance the adaptability and efficiency of feature extraction. Inspired by the Mixture-of-Experts framework, DynamicConv applies a conditional computation mechanism that dynamically adjusts kernel weights based on the input feature characteristics. This design allows the network to extract features more effectively across varying object scales and motion patterns, improving robustness against dynamic disturbances with low computational cost. Third, the original segmentation head is replaced by the Reused and Shared Convolutional Segmentation Head (RSCS Head), which enables decoder structure sharing across multi-scale branches. RSCS reduces redundant computation by reusing convolutional layers and optimizing feature decoding paths, further improving overall model efficiency while maintaining segmentation accuracy. These architectural modifications result in DHSR-YOLOSeg, a lightweight semantic segmentation model that significantly reduces parameter count and computational cost while preserving performance. DHSR-YOLOSeg is integrated into the tracking thread of ORB-SLAM3. to provide real-time semantic information. This enables dynamic object detection and the removal of unstable feature points during localization, thereby enhancing the robustness and trajectory consistency of SLAM in complex dynamic environments. Results and Discussions Ablation experiments on the COCO dataset demonstrate that, compared with the baseline YOLOv11n-seg, the proposed DHSR-YOLOSeg achieves a 13.8% reduction in parameter count, a 23.1% decrease in Giga Floating Point Operations (GFLOPs), and an approximate 2% increase in mean Average Precision at IoU 0.5 (mAP50) (Table 1 ). On the KITTI dataset, DHSR-YOLOSeg reaches an inference speed of 60.19 frame/s, which is 2.14% faster than YOLOv11n-seg and 275% faster than the widely used Mask R-CNN (Table 2 ). For trajectory accuracy evaluation on KITTI sequences 00～10, DHSR-YOLOSeg outperforms ORB-SLAM3 in 8 out of 10 sequences, achieving a maximum Root Mean Square Error (RMSE) reduction of 16.76% and an average reduction of 8.78% (Table 3 ). Compared with DynaSLAM and DS-SLAM, the proposed framework exhibits more consistent error suppression across sequences, improving both trajectory accuracy and stability. In terms of runtime efficiency, DHSR-YOLOSeg achieves an average per-frame processing time of 48.86 ms on the KITTI dataset, 18.44% and 41.38% lower than DS-SLAM and DynaSLAM, respectively (Table 4 ). The per-sequence processing time ranges from 41 to 55 ms, which is comparable to the 35.64 ms of ORB-SLAM3, indicating that the integration of semantic segmentation introduces only a modest computational overhead. Conclusions This study addresses the challenge of achieving robust localization for inspection robots operating in dynamic environments, particularly in urban road settings characterized by frequent interference from pedestrians, vehicles, and other moving objects. To this end, a semantic-enhanced visual SLAM framework is proposed, in which a lightweight semantic segmentation model, DHSR-YOLOSeg, is integrated into the stereo-based ORB-SLAM3 pipeline. This integration enables real-time identification of dynamic objects and removal of their associated feature points, thereby improving localization robustness and trajectory consistency. The DHSR-YOLOSeg model incorporates three key architectural components—DyCANet for feature fusion, DynamicConv for adaptive convolution, and the RSCS Head for efficient multi-scale decoding. Together, these components reduce the model’s size and computational cost while preserving segmentation performance, providing an efficient and deployable perception solution for resource-constrained platforms. Experimental findings show that: (1) ablation tests on the COCO dataset confirm substantial reductions in complexity with preserved accuracy, supporting embedded deployment; (2) frame rate comparisons on the KITTI dataset demonstrate superior performance over both lightweight and standard semantic segmentation methods, meeting real-time SLAM requirements; (3) trajectory evaluations indicate that the dynamic feature rejection strategy effectively mitigates localization errors in dynamic scenes; and (4) the overall system maintains high runtime efficiency, ensuring a practical balance between semantic segmentation and real-time localization performance. However, current experiments are conducted under ideal conditions using standardized datasets, without fully reflecting real-world challenges such as multi-sensor interference or unstructured environments. Moreover, the trade-offs between model complexity and accuracy for each lightweight module have not been systematically assessed. Future work will focus on multimodal sensor fusion and adaptive dynamic perception strategies to enhance the robustness and applicability of the proposed system in real-world autonomous inspection scenarios.
Available online , doi: 10.11999/JEIT250529
Abstract:
Objective A novel cross-modal hashing framework driven by Large Language Models (LLMs) is proposed to address the semantic misalignment between medical images and their corresponding textual reports. The objective is to enhance cross-modal semantic representation and improve retrieval accuracy by effectively mining and matching semantic associations between modalities. Methods The generative capacity of LLMs is first leveraged to produce high-quality textual descriptions of medical images. These descriptions are integrated with diagnostic reports and structured clinical data using a dual-stream semantic enhancement module, designed to reinforce inter-modality alignment and improve semantic comprehension. A structural similarity-guided hashing scheme is then developed to encode both visual and textual features into a unified Hamming space, ensuring semantic consistency and enabling efficient retrieval. To further enhance semantic alignment, a prompt-driven attention template is introduced to fuse image and text features through fine-tuned LLMs. Finally, a contrastive loss function with hard negative mining is employed to improve representation discrimination and retrieval accuracy. Results and Discussions Experiments are conducted on a multimodal medical dataset to compare the proposed method with existing cross-modal hashing baselines. The results indicate that the proposed method significantly outperforms baseline models in terms of precision and Mean Average Precision (MAP) (Table 3 ; Table 4 ). On average, a 7.21% improvement in retrieval accuracy and a 7.72% increase in MAP are achieved across multiple data scales, confirming the effectiveness of the LLM-driven semantic mining and hashing approach. Conclusions Experiments are conducted on a multimodal medical dataset to compare the proposed method with existing cross-modal hashing baselines. The results indicate that the proposed method significantly outperforms baseline models in terms of precision and Mean Average Precision (MAP) (Table 3 ; Table 4 ). On average, a 7.21% improvement in retrieval accuracy and a 7.72% increase in MAP are achieved across multiple data scales, confirming the effectiveness of the LLM-driven semantic mining and hashing approach.
Available online , doi: 10.11999/JEIT250412
Abstract:
Significance The data prefetcher is a key microarchitectural component in modern processors, designed to enhance memory access performance by speculatively preloading data into the cache based on predictions of future access patterns. While effective at reducing cache misses, prefetcher design has historically neglected security considerations, resulting in various forms of information leakage. Recent studies have shown that data prefetchers can be exploited in side-channel attacks targeting cryptographic libraries, operating systems, hypervisors, and trusted execution environments. However, most existing attacks focus on specific implementations (eg., "one-spot" attacks) fail to comprehensively capture the broader attack surface exposed by diverse prefetcher designs. Two fundamental research questions remain open: (1) Do current attacks fully characterize all exploitable vectors in modern prefetchers, or are additional vectors yet to be explored? (2) How can the security of different prefetcher designs be systematically and quantitatively assessed to support comparative analysis and guide secure design? This paper addresses both questions through a systematic survey of data prefetcher attacks and a model-driven analysis. By generalizing known attack mechanisms, this work proposes a formalized framework for understanding and evaluating the security of data prefetchers. Methods To capture the behavior of data prefetchers, this study first presents a memory access model that specifies the instruction address, data address, and access attributes for each memory operation, which can be extended to represent access sequences. Building on this, a prefetcher model is proposed in which a prefetcher is trained by a sequence of memory accesses and triggered by a single access to generate a set of prefetches. Each prefetcher is characterized by design parameters. Attacker and victim profiles are then incorporated to construct attack models based on reduced memory access representations, enabling formalization of 20 known prefetcher-based attacks. Finally, a security evaluation framework is proposed, comprising 24 metrics across three dimensions—design parameters, isolation, and attack feasibility. This framework supports quantitative scoring and comparison of prefetcher designs. Results and Prospects In terms of attack modeling, the analysis shows that the 20 known attacks cover only a limited portion of the overall attack space. This study proposes several previously unexplored attack vectors, including those that exploit cache hit effects and speculative execution, attacks that leverage indexing collisions using instruction and data addresses, and additional side channels resulting from prefetcher-induced effects on other microarchitectural components, such as Translation Lookaside Buffer (TLB) state and cache coherence state. In terms of evaluation, this paper examines five commercial processors featuring different prefetchers: Intel’s Stride prefetcher and eXtended Page Table (XPT), AMD’s Stride prefetcher, Arm’s Spatial Memory Streaming (SMS) prefetcher, and Apple’s Data Memory Prefetcher (DMP). The findings reveal that all five prefetchers exhibit varying degrees of vulnerability to side-channel leakage, depending on their design parameters, isolation strategies, and the feasibility of exploitation. The paper further assesses three mitigation strategies and shows that while some measures substantially enhance security, residual risks remain, highlighting the need for improved countermeasures. Discussion Beyond characterizing existing attack vectors and evaluating the security of current prefetcher implementations, this study also outlines emerging directions for secure prefetcher design. Existing work primarily focuses on the Stride prefetcher, with preliminary defenses based on control registers that allow software to constrain the address range eligible for prefetching. This reduces the likelihood that secret-dependent memory accesses affect prefetcher state or trigger the prefetching of sensitive cache lines. Nevertheless, these approaches remain at an early stage, and a comprehensive framework for the systematic design of secure prefetchers has yet to be developed. Conclusions This paper presents a systematic study of data prefetcher security. It proposes a model-driven framework for analyzing potential attack vectors and introduces a quantitative method for evaluating prefetcher security. These contributions lay a theoretical foundation for identifying new attack mechanisms, guiding the development of effective countermeasures, and informing the secure design of data prefetchers in future processor architectures.
Available online , doi: 10.11999/JEIT250466
Abstract:
Objective The proliferation of Internet of Things (IoT) devices and the growing demand for edge computing have driven increased reliance on edge systems. However, deploying compute-intensive tasks on resource-constrained edge devices significantly raises computational demands and power consumption, thereby placing additional strain on energy-limited terminals. On-chip cache, which temporarily stores frequently accessed data and instructions, plays a crucial role in reducing latency and improving system performance. To address the stringent requirements of edge environments, it is essential to design on-chip caches that offer low power consumption, low manufacturing cost, and stable performance. Methods The proposed on-chip cache employs SRAM-based storage cells and a block-based architecture to store intermediate data between neural network layers. The memory capacity is configured as 40.5 Kb, based on the output feature map of the first neural network layer, which generates the largest data volume. This feature map has spatial dimensions of 72×72 with 8 channels. To enable efficient data scheduling during neural network computation, data from each channel is stored in an independent sub-array. Therefore, the buffer consists of 8 sub-arrays, each implemented as a 72×72 SRAM array with dedicated bit-line and word-line drivers. A memory control module is implemented to exploit the progressive reduction in data volume across convolutional layers. During access to the second convolutional layer, only the required sub-arrays are activated. Unused memory blocks are dynamically powered down by the control module to achieve deep power optimization. Performance evaluation is carried out through simulations using TSMC 180 nm CMOS technology. The evaluation includes measurements of access latency under different process corners and temperatures; read/write dynamic power consumption under varying supply voltages, temperatures, and clock frequencies; and a comparative analysis of dynamic power consumption between monolithic and block-based storage architectures. Results and Discussions The proposed on-chip cache demonstrates strong performance across key evaluation metrics. First, a comprehensive design summary is provided, detailing supply voltage, memory capacity, and layout area under different process variations (Table 1 ). Second, dynamic read/write power measurements under varying operating temperatures, supply voltages, and clock frequencies (Tables 2 –4 ) confirm excellent energy efficiency, satisfying the stringent power-performance requirements of edge visual sensing applications across diverse conditions. Access latency analysis further confirms stable memory read/write behavior under process corner variations and thermal fluctuations (Fig. 8 ). A comparative evaluation of power consumption between monolithic and partitioned storage architectures (Table 5 ), together with benchmarking against state-of-the-art designs (Table 6 ), demonstrates that the proposed cache achieves significantly lower read/write energy consumption at the same process node, while maintaining stable access characteristics at reduced operating voltages. This design adopts a system-level optimization strategy that emphasizes architectural innovation over costly process scaling. When implemented in more advanced technology nodes, the architecture is expected to achieve substantial gains in energy-per-access, minimum operating voltage, and area efficiency. Conclusions This paper presents the architecture and circuit-level design of an on-chip cache tailored for edge visual perception systems. By optimizing the cache structure for neural network workloads, the proposed design reduces dynamic power consumption through block-based storage and dynamic memory control, thereby enhancing energy efficiency and extending operational endurance. The approach offers broad applicability for edge-based visual perception devices.
Available online , doi: 10.11999/JEIT250369
Abstract:
Significance Combinatorial optimization problems (COPs) are ubiquitous, profoundly impacting diverse fields from logistics and finance to advanced AI and drug discovery. At their core, these problems demand identifying the absolute best solution from an often unfathomably vast set of possibilities. The vast majority of COPs are classified as NP-hard problems, representing one of the most significant computational challenges in computer science. Traditional digital computers, operating on the von Neumann architecture, face immense difficulties in solving COPs; as problem scales expand, required computational resources, particularly latency, increase exponentially. Given these limitations, there's an urgent need to explore novel architectures for efficiently solving COPs, a pursuit with both significant theoretical importance and profound practical implications for tackling complex, resource-intensive real-world problems. Addressing these challenges, researchers have actively explored various novel hardware-based combinatorial optimization solutions, often transforming COPs into Ising models or Quadratic Unconstrained Binary Optimization (QUBO) problems for hardware implementation. Broadly, existing approaches fall into two categories: digital Application-Specific Integrated Circuit (ASIC) annealers, which suffer from data movement bottlenecks, and dynamical system solvers, which leverage physical dynamics but often demand high device parameter precision, struggle with cross-chip scalability, and may find it difficult to integrate Ising model self-interaction terms. Beyond these, other non-traditional methods like quantum computing (e.g., D-Wave's quantum annealers requiring cryogenic cooling and having limited connectivity) and certain optical computing approaches (e.g., relying on extremely long optical fibers) exist. While offering unique physical advantages, they generally face substantial challenges in integrating with mature silicon-based Very Large Scale Integration (VLSI) circuits. Consequently, despite a range of novel hardware solutions, their individual limitations highlight the critical need for new combinatorial optimization solvers that offer higher integration, better scalability, superior energy efficiency, and broader problem type support. Process Ferroelectric field-effect transistors (FeFETs), with their unique threshold voltage programmability and multi-port input structure, are opening exciting new avenues for efficiently solving combinatorial optimization problems (COPs). The FeFET-based compute-in-memory (CiM) architecture is particularly well-suited for these challenges, boasting high energy efficiency, low latency, and the inherent ability to accelerate complex operations like vector-matrix and vector-matrix-vector multiplications. Recent research has seen numerous works proposing FeFET-based CiM COP solvers to tackle a diverse range of problems, including those with equality constraints, inequality constraints, and Nash equilibrium scenarios. The overall solving process for these innovative FeFET-based CiM solutions generally involves four key steps: (1) Problem transformation, where the COP is converted into a hardware-friendly objective function, often by encoding equality constraints, introducing slack variables or penalty methods for inequality constraints, or formulating coupled optimization problems for Nash equilibrium scenarios; (2) Following transformation, the objective function undergoes a crucial compression process. This is specifically achieved by analyzing the simulated annealing algorithm itself, which allows for the partial activation of matrix columns, thus significantly reducing the typical computational complexity associated with fully active matrices. Furthermore, this step involves approximating and merging the exponential function components inherent in the algorithm directly into the matrix representation, thereby optimizing the function for efficient hardware implementation on the CiM array; (3) Leveraging the unique three-port and four-port structures of FeFETs, specialized CiM circuit designs are utilized to achieve high-speed acceleration of the compressed objective function. This allows for the efficient computation of a single iteration or a key part of the objective function often within a single clock cycle, significantly mitigating the von Neumann bottleneck; and (4) Finally, based on the optimized and simplified objective function, combinatorial optimization algorithms, such as simulated annealing, are simplified and applied over multiple cycles. This iterative process, efficiently accelerated by the underlying CiM hardware, aims to achieve high-quality and efficient solutions for the given problem. This structured approach highlights the adaptability and potential of FeFET-based CiM for a broad spectrum of challenging combinatorial optimization tasks. Conclusions This paper provides a comprehensive review of FeFET-based CiM solvers for solving COPs, which are prevalent across various domains and demand significant computational resources. It first outlines the device characteristics of FeFET and the fundamental process of solving COPs. The core of the paper focused on recent advancements in FeFET-based CiM solvers tailored for three specific scenarios: equality constraints, inequality constraints, and Nash equilibrium. The discussion highlighted how these architectures leverage the unique properties of FeFET to address the computational intensity of these problems. Prospects FeFET-based COP solvers show immense potential. By merging FeFET device strengths with CiM advantages, these solvers offer an efficient path to tackling highly complex optimization challenges, leading to substantial gains in speed and energy efficiency for real-world problems. However, significant challenges remain: (1) FeFET endurance is limited, restricting the number of processable problems. (2) Analog-to-digital converters (ADCs) in FeFET CiM arrays incur large area, power, and latency overheads. (3) Simulated annealing algorithms, when applied to large-scale problems, suffer from slow convergence due to increased iterations. Addressing these will be crucial for the widespread adoption and advancement of FeFET-based CiM solutions.
Available online , doi: 10.11999/JEIT250125
Abstract:
Objective To address sparse circular array deployment in practical engineering scenarios, where the number and positions of array elements are constrained, this study proposes an optimization algorithm based on Double Deep Q-Networks (DDQN) to maintain Direction-of-Arrival (DOA) estimation performance under limited channel conditions. This method enables flexible and efficient array design strategies and overcomes challenges that conventional optimization approaches are unable to resolve effectively. The sparse circular array design problem is formulated by minimizing the two-dimensional DOA estimation Ziv–Zakai Bound (ZZB) and Peak Sidelobe Level (PSL) as joint objectives to ensure both angular resolution and estimation accuracy. The state space, action space, and reward function are constructed accordingly, and the DDQN algorithm is employed to solve the optimization task. Experimental results demonstrate that the proposed method achieves stable convergence and robust DOA estimation performance under deployment constraints, and confirm its practical effectiveness. Methods To optimize sparse circular arrays under structural and channel limitations, a DDQN-based design approach is proposed. The method selects a subset of elements from a uniform circular array to maximize DOA estimation accuracy and angular resolution while satisfying constraints on the number of antennas and inter-element spacing. The array design task is cast as a constrained optimization problem with the two-dimensional DOA ZZB and PSL as the performance metrics. Within the reinforcement learning framework, the state space reflects potential array configurations, the action space corresponds to candidate element selections, and the reward function is derived from the optimization objectives. Once trained, the DDQN model outputs an optimized sparse array configuration that balances resolution and sidelobe suppression under the given constraints. Results and Discussions Simulation results show that the reward function of the proposed algorithm converges as the number of training episodes increases (Fig. 8 ). In contrast, traditional reinforcement learning algorithms exhibit slower convergence and yield suboptimal solutions, while genetic algorithms tend to suffer from premature convergence. The designed sparse circular array satisfies the optimization constraints, including the maximum inter-element spacing requirement (Fig. 9(a) ). Under a six-source scenario, the array demonstrates robust DOA estimation capability, effectively resolving multiple incident signals DOA estimation problem (Fig. 10 ). In evaluations of DOA estimation with Root Mean Squared Error (RMSE) under varying Signal-to-Noise Ratio (SNR) conditions (Fig. 11 ), the proposed array achieves an estimation error below 0.5° when SNR is ≥ 0 dB. Compared with other sparse circular arrays, it achieves the lowest RMSE, indicating superior estimation performance. In angular resolution tests, the proposed array also exhibits lower PSL values (Table 3 ) and a higher angle estimation success rate. When the angular separation is ≥ 3°, the success rate exceeds 95% (Fig. 12 ), confirming the array’s high DOA estimation accuracy and strong angular resolution. Conclusions This study formulates sparse circular array optimization as a constrained problem with the maximum inter-element spacing as a design constraint. To enhance both DOA estimation accuracy and angular resolution, the two-dimensional DOA estimation ZZB and PSL are minimized as joint objectives function. A DDQN algorithm with a dual-network structure is employed to solve the optimization problem and generate the array configuration. Simulation experiments verify that, under channel limitations, the proposed array satisfies the imposed constraints and achieves the intended optimization goals. Compared with other sparse circular arrays, the design demonstrates superior overall DOA estimation performance.
Available online , doi: 10.11999/JEIT250360
Abstract:
Objective Physical Unclonable Functions (PUFs) serve as unique chip identifiers and have broad application in resource-constrained Internet of Things (IoT) devices. Strong PUFs are widely adopted for device authentication and state verification due to their capacity to generate exponential Challenge–Response Pairs (CRPs). However, the deterministic relationship between input and output arising from their physical construction renders them vulnerable to machine learning attacks. Attackers can model this relationship by collecting a subset of CRPs and applying algorithms such as Logistic Regression (LR), Support Vector Machines (SVM), or Artificial Neural Networks (ANN), enabling prediction of unseen CRPs. The arbiter PUF is the most representative strong PUF. To enhance its security, researchers typically employ XOR architectures or algorithmic obfuscation to increase response complexity. However, these approaches incur substantial hardware overhead, particularly when implemented in circuit form. In this study, we propose a high-security, low-cost PUF based on a cross-coupling structure that enhances resistance to machine learning attacks. The design leverages competition between bistable elements to transition from a reset to a stable state, producing exponential CRPs. Each PUF unit comprises two NOR gates and two access transistors. An XOR tree further obfuscates the output, increasing nonlinearity. Although the XOR tree requires multiple parallel outputs, the design remains compatible with embedded memory architectures such as SRAM, enabling macro-level integration. Overall, this architecture achieves improved attack resistance with minimal additional hardware, as the primary cost lies in a limited number of XOR gates. Methods A strong PUF based on a cross-coupled structure is proposed by analyzing the transient behavior of cross-coupled NOR and NAND gates transitioning from a reset state to a stable state. In this design, the word line serves as the excitation signal, and exponential CRPs are generated by sequentially traversing the word line with a fixed bit width. The implementation focuses on cross-coupled NOR gates as a representative case. Before the PUF response is generated, a reset signal drives the storage nodes of the cross-coupled NOR gates to a low level. Different digital word lines are then activated to provide excitation, while the bit lines are pre-discharged to ground. Upon deactivation of the reset signal, due to inherent process variation—specifically, mismatch in device characteristics—each activated NOR gate exhibits a unique transient response. The mismatch in strengths between different units causes competing voltage transitions at the storage nodes, resulting in a final logic state of 0 or 1 on the corresponding bit line. To reveal the intrinsic entropy mechanisms, the system is modeled by decomposing the entropy sources using the superposition principle. Two independent contributors are identified: (1) variation in charging speed induced by PMOS parasitic capacitance mismatch and (2) difference in positive feedback triggering priority due to NMOS threshold voltage mismatch. The final PUF response arises from the combined effect of these two factors. To enhance resistance to machine learning attacks, multi-bit parallel outputs from the PUF array are processed through an XOR tree. This obfuscation increases response nonlinearity, thereby improving both uniqueness and randomness while rendering the PUF immune to modeling attacks such as those based on LR, SVM, or neural networks. Results and Discussions Simulation results confirm that the proposed cross-coupled strong PUF effectively resists machine learning-based modeling attacks while maintaining favorable statistical properties in reliability, uniqueness, and randomness. The architecture demonstrates strong resilience against modeling attacks from widely used algorithms, including LR, SVM, convolutional neural networks, and ANN (Fig. 7 ). The average inter-slice Hamming distance is 0.4991 (standard deviation: 0.022), indicating excellent uniqueness (Fig. 8 ). The average intra-slice Hamming distance is 0.0926 (mean: 0.0116 ), confirming strong reproducibility. Output logic levels are evenly distributed, with logic 0 and logic 1 accounting for 49.97% and 50.03% of responses, respectively. The minimum Shannon entropy exceeds 0.99, and overall randomness reaches 97.64% (Figs. 9 and 10 ), indicating near-ideal entropy characteristics. Autocorrelation analysis shows a limit within ±0.02, aligning with the 95% confidence interval of Gaussian white noise and suggesting negligible correlation among response bits (Fig. 11 ). The native error rate increases from 0.9% before XOR obfuscation to 5.9% after obfuscation, reflecting the trade-off between enhanced security and response stability. Under voltage and temperature variations, the worst-case error rates after XOR obfuscation are 13.55% and 12.21%, respectively (Fig. 12 ), indicating robust reliability across environmental conditions. A comparative evaluation with existing strong PUF architectures is summarized in Table 1 , highlighting the advantages of the proposed design in both security performance and hardware efficiency. Conclusions This study investigates the transition dynamics of bistable circuits from metastable to steady states and integrates delay-based and threshold voltage–based entropy sources to enhance the complexity of strong PUF models. The implementation of XOR tree obfuscation further increases output nonlinearity, reduces hardware overhead, and strengthens resistance to machine learning attacks. Experimental results demonstrate that, even when trained on 104 CRPs, machine learning algorithms such as LR, SVM, and ANN fail to predict PUF responses. The proposed design also exhibits favorable statistical properties and strong reliability. Its structural compatibility with memory architectures makes it particularly suitable for secure authentication in memory-based IoT devices.
Available online , doi: 10.11999/JEIT250647
Abstract:
Objective With the rapid advancement of Artificial Intelligence (AI) and growing demands in ecological monitoring, high-quality multimodal datasets have become essential for training and deploying AI models in specialized domains. Existing bird datasets, however, face notable limitations, including challenges in field data acquisition, high costs of expert annotation, limited representation of rare species, and reliance on single-modal data. To overcome these constraints, this study proposes an efficient framework for constructing large-scale multimodal datasets tailored to ecological monitoring. By integrating heterogeneous data sources, employing intelligent semi-automatic annotation pipelines, and adopting multi-model collaborative validation based on heterogeneous attention fusion, the proposed approach markedly reduces the cost of expert annotation while maintaining high data quality and extensive modality coverage. This work offers a scalable and intelligent strategy for dataset development in professional settings and provides a robust data foundation for advancing AI applications in ecological conservation and biodiversity monitoring. Methods The proposed multimodal dataset construction framework integrates multi-source heterogeneous data acquisition, intelligent semi-automatic annotation, and multi-model collaborative verification to enable efficient large-scale dataset development. The data acquisition system comprises distributed sensing networks deployed across natural reserves, incorporating high-definition intelligent cameras, custom-built acoustic monitoring devices, and infrared imaging systems, supplemented by standardizedpublic data to enhance species coverage and modality diversity. The intelligent annotation pipeline is built upon four core automated tools: (1) spatial localization annotation leverages object detection algorithms to generate bounding boxes; (2) fine-grained classification employs Vision Transformer models for hierarchical species identification; (3) pixel-level segmentation combines detection outputs with SegGPT models to produce instance-level masks; and (4) multimodal semantic annotation uses Qwen large language models to generate structured textual descriptions. To ensure annotation quality and minimize manual verification costs, a multi-scale attention fusion verification mechanism is introduced. This mechanism integrates seven heterogeneous deep learning models, each with different feature perception capacities across local detail, mid-level semantic, and global contextual scales. A global weighted voting module dynamically assigns fusion weights based on model performance, while a prior knowledge-guided fine-grained decision module applies category-specific accuracy metrics and Top-K model selection to enhance verification precision and computational efficiency. Results and Discussions The proposed multi-scale attention fusion verification method dynamically assesses data quality based on heterogeneous model predictions, forming the basis for automated annotation validation. Through optimized weight allocation and category-specific verification strategies, the collaborative verification framework evaluates the effect of different model combinations on annotation accuracy. Experimental results demonstrate that the optimal verification strategy—achieved by integrating seven specialized models—outperforms all baseline configurations across evaluation metrics. Specifically, the method attains a Top-1 accuracy of 95.39% on the CUB-200-2011 dataset, exceeding the best-performing single-model baseline, which achieves 91.79%, thereby yielding a 3.60% improvement in recognition precision. The constructed BIRD1445 dataset, comprising 3.54 million samples spanning 1,445 bird species and four modalities, outperforms existing datasets in terms of coverage, quality, and annotation accuracy. It serves as a robust benchmark for fine-grained classification, density estimation, and multimodal learning tasks in ecological monitoring. Conclusions This study addresses the challenge of constructing large-scale multimodal datasets for ecological monitoring by integrating multi-source data acquisition, intelligent semi-automatic annotation, and multi-model collaborative verification. The proposed approach advances beyond traditional manual annotation workflows by incorporating automated labeling pipelines and heterogeneous attention fusion mechanisms as the core quality control strategy. Comprehensive evaluations on benchmark datasets and real-world scenarios demonstrate the effectiveness of the method: (1) the verification strategy improves annotation accuracy by 3.60% compared to single-model baselines on the CUB-200-2011 dataset; (2) optimal trade-offs between precision and computational efficiency are achieved using Top-K = 3 model selection, based on performance–complexity alignment; and (3) in large-scale annotation scenarios, the system ensures high reliability across 1,445 species categories. Despite its effectiveness, the current approach primarily targets species with sufficient data. Future work should address the representation of rare and endangered species by incorporating advanced data augmentation and few-shot learning techniques to mitigate the limitations posed by long-tail distributions.
Available online , doi: 10.11999/JEIT250453
Abstract:
Objective As software systems increase in scale and complexity, the frequency of security vulnerabilities in source code rises accordingly, threatening system reliability, data integrity, and user privacy. Conventional automated vulnerability detection methods typically depend on a narrow set of shallow features—such as API call sequences, opcode patterns, or syntactic heuristics—rendering them susceptible to learning spurious correlations and unable to capture the rich semantic and structural information essential for accurate detection. Moreover, most existing approaches either rely on single-modal representations or weakly integrate multiple modalities without explicitly addressing distribution mismatches across them. This often results in overfitting to seen datasets and limited generalization to unseen codebases, particularly across different projects or programming languages. Although recent advances in machine learning and deep learning have improved source code analysis, effectively modeling the complex interactions between code semantics and execution structures remains a major challenge. To overcome these limitations, this paper proposes a multi-modal joint Distillation Optimization for Vulnerability Detection (mVulD-DO), a multimodal framework that combines deep feature distillation with dynamic global feature alignment. The proposed method aims to enhance semantic comprehension, structural reasoning, and cross-modal consistency, which are critical for robust vulnerability detection. By enforcing both intra-modality refinement and inter-modality alignment, mVulD-DO addresses the semantic-structural gap that constrains traditional methods. Methods The mVulD-DO framework begins by extracting multiple semantic modalities from raw source code—function names, variable names, token_type attributes, and local code slices—using program slicing and syntactic parsing techniques. In parallel, a Program Dependency Graph (PDG) is constructed to capture both control-flow and data-flow relationships, generating a heterogeneous graph that represents explicit and implicit program behaviors. Each semantic modality is embedded using pretrained encoders and subsequently refined via a deep feature distillation module, which integrates multi-head self-attention and multi-scale convolutional layers to emphasize salient patterns and suppress redundant noise. To model the sequential dependencies intrinsic to program execution, a Bidirectional Long Short-Term Memory (BLSTM) network captures long-range contextual interactions. For structural representation, a Graph Attention Network (GAT) processes the PDG-C to produce topology-aware embeddings. To bridge the gap between modalities, adaptive dynamic Sinkhorn regularization is applied to globally align the distributions of semantic and structural embeddings. This approach mitigates modality mismatches while preserving flexibility by avoiding rigid one-to-one correspondences. Finally, the distilled and aligned multimodal features are fused and passed through a lightweight fully connected classifier for binary vulnerability prediction. The model is jointly optimized using both classification and alignment objectives, improving its ability to generalize across unseen codebases. Results and Discussions Comprehensive comparisons conducted on the mixed CVEFixes+SARD dataset—covering 25 common CWE vulnerability types with an 8:1:1 train:validation:test split—demonstrate that traditional source code detectors, which directly map code to labels, often rely on superficial patterns and show limited generalization, particularly for out-of-distribution samples. These methods achieve accuracies ranging from 55.41% to 85.84%, with recall typically below 80% (Table 1 ). In contrast, mVulD-DO leverages multi-layer feature distillation to purify and enhance core representations, while dynamic Sinkhorn alignment mitigates cross-modal inconsistencies. This results in accuracy of 87.11% and recall of 83.59%, representing absolute improvements of 1.27% and 6.26%, respectively, over the strongest baseline method (ReGVD). Although mVulD-DO reports a slightly higher False Positive Rate (FPR) of 3.54%—2.92% above that of ReGVD—it remains lower than that of most traditional detectors. This modest increase is considered acceptable in practice, given that failing to detect a critical vulnerability typically incurs greater cost than issuing additional alerts. Compared with instruction-tuned large language models (e.g., VulLLM), which maintain low FPRs below 10% but suffer from recall below 75%, mVulD-DO offers a more favorable trade-off between false alarms and coverage of true vulnerabilities. Ablation studies (Table 2 ) further validate the contribution of each component. Removing function name embeddings (unfunc) results in a 1.3% decrease in F1 score; removing variable name embeddings (unvar) causes a 1.3% drop; and omitting token_type attributes (untype) leads to a 3.35% reduction. The most substantial performance degradation—9.11% in F1—occurs when the deep feature distillation module is disabled (undis), highlighting the critical role of multi-scale semantic refinement and noise suppression. Additional evaluations on vulnerability-sensitive subsets—Call, OPS, Array, and PTR—demonstrate consistent benefits from Sinkhorn alignment. F1 score improvements over unaligned variants are observed as follows: 1.45% for Call, 4.22% for OPS, 1.38% for Array, and 0.36% for PTR (Table 3 ), confirming the generalization advantage across a broad spectrum of vulnerability types. Conclusions Experimental results demonstrate that the proposed mVulD-DO framework consistently outperforms existing vulnerability detection methods in recall, F1-score, and accuracy, while maintaining a low FPR The effectiveness of deep feature distillation, multi-scale semantic extraction, and dynamic Sinkhorn alignment is validated through extensive ablation and visualization analyses. Despite these improvements, the model incurs additional computational overhead due to multimodal distillation and Sinkhorn alignment, and shows sensitivity to hyperparameter settings, which may limit its suitability for real-time applications. Moreover, while strong performance is achieved on the mixed dataset, the model's generalization across unseen projects and programming languages remains an open challenge. Future work will focus on developing lightweight training strategies—such as knowledge distillation and model pruning—to reduce computational costs. Additionally, incorporating unsupervised domain adaptation and incremental alignment mechanisms will be critical to support dynamic code evolution and enhance cross-domain robustness. These directions aim to improve the scalability, adaptability, and practical deployment of multimodal vulnerability detection systems in diverse software environments.
Available online , doi: 10.11999/JEIT250405
Abstract:
Objective The exponential growth in data traffic necessitates that cellular Internet of Things (IoT) systems achieve both ultra-high spectral efficiency and wide-area coverage to meet the stringent service requirements of vertical applications such as industrial automation and smart cities. Non-Orthogonal Multiple Access-based Coordinated Direct and Relay Transmission (NOMA-CDRT) method can enhance both spectral efficiency and coverage by leveraging power-domain multiplexing and cooperative relaying, making it a promising approach to address these challenges. However, existing NOMA-CDRT frameworks are primarily designed for cellular communications and do not effectively support spectrum sharing or the deep integration of cellular and IoT transmissions. To overcome these limitations, this study proposes a Mutualistic Backscatter NOMA-CDRT (MB-NOMA-CDRT) method. This approach facilitates spectrum sharing and mutualistic coexistence between cellular users and IoT devices, while improving the system’s Ergodic Sum Rate (ESR). Methods The proposed MB-NOMA-CDRT method integrates backscatter modulation and power-domain superposition coding to develop a bidirectional communication strategy that unifies information transmission and cooperative assistance, enabling spectrum sharing and mutualistic coexistence between cellular users and IoT devices. Specifically, the base station uses downlink NOMA to serve the cellular center user directly and the cellular edge user via a relaying user. Simultaneously, IoT devices utilize cellular radio frequency signals and backscatter modulation to transmit their data to the base station, thereby achieving spectrum sharing. The backscattered IoT signals act as multipath gains, contributing to improved cellular communication quality. To rigorously characterize the system performance, the squared generalized-K distribution and Meijer-G functions are adopted to derive closed-form expressions for the ESR under both perfect and imperfect Successive Interference Cancellation (SIC). Building on this analytical foundation, a power allocation optimization scheme is developed using an enhanced Particle Swarm Optimization (PSO) algorithm to maximize system ESR. Finally, extensive Monte Carlo simulations are conducted to verify the ESR gains of the proposed method, confirm the theoretical analysis, and demonstrate the efficacy of the optimization scheme. Results and Discussions The performance advantage of the proposed MB-NOMA-CDRT method is demonstrated through comparisons of ESR with conventional NOMA-CDRT and Orthogonal Multiple Access (OMA) schemes (Fig. 2 and Fig. 3 ). The theoretical ESR results closely match the simulation data, confirming the validity of the analytical derivations. Under both perfect and imperfect SIC, the proposed method consistently achieves the highest ESR. This improvement arises from spectrum sharing between cellular users and IoT devices, where the IoT link contributes multipath gain to the cellular link, thereby enhancing overall system performance. To investigate the influence of power allocation, simulation results illustrate the three-dimensional relationship between ESR and power allocation coefficients (Fig. 4 ). A maximum ESR is observed under specific coefficient combinations, indicating that optimized power allocation can significantly improve system throughput. Furthermore, the proposed optimization scheme demonstrates rapid convergence, with ESR values stabilizing within a few iterations (Fig. 5 ), supporting its computational efficiency. Finally, ESR performance is compared among the proposed optimization scheme, exhaustive search, and fixed power allocation strategies (Fig. 6 ). The proposed scheme consistently yields higher ESR across both perfect and imperfect SIC scenarios, demonstrating its superiority in enhancing spectral efficiency while maintaining low computational complexity. Conclusions This study proposes a MB-NOMA-CDRT method that enables spectrum sharing between IoT devices and cellular users while improving cellular communication quality through the backscatter-assisted reflection link. To evaluate system performance, closed-form expressions for the ESR are derived under both perfect and imperfect SIC. Building on this analytical foundation, a power allocation optimization scheme based on PSO is developed to maximize the system ESR. Simulation results demonstrate that the proposed method consistently outperforms conventional NOMA-CDRT and OMA schemes in terms of ESR, under both perfect and imperfect SIC conditions. The optimization scheme also exhibits favorable convergence behavior and effectively improves system performance. Given its advantages in spectral efficiency and computational efficiency, the proposed MB-NOMA-CDRT method is well suited to cellular IoT scenarios. Future work will focus on exploring the mathematical conditions necessary to fully characterize and exploit the mutualistic transmission mechanism.
Available online , doi: 10.11999/JEIT250342
Abstract:
Objective Conventional Heart Rate Variability (HRV) monitoring in aviation is limited by bulky wearable devices that require direct skin contact, are prone to electromagnetic interference during flight, and suffer from electrode displacement during high-G maneuvers. These constraints hinder continuous physiological monitoring, which is critical for flight safety. This study presents a non-contact monitoring approach integrated into pilot helmets, utilizing BallistoCardioGram (BCG) technology to detect cardiac mechanical activity via helmet-mounted inertial sensors. The objective is to establish a novel physiological monitoring paradigm that eliminates the need for skin–electrode interfaces while achieving measurement accuracy suitable for aviation operational standards. Methods Hardware ConfigurationA patented BCG sensing module is embedded within the occipital stabilization system of flight protective helmets. Miniaturized, high-sensitivity inertial sensors interface with proprietary signal conditioning circuits that execute a three-stage physiological signal refinement process. First, primary analog amplification scales microvolt-level inputs to measurable voltage ranges. Second, a fourth-order Butterworth bandpass filter (0.5–20 Hz) isolates cardiac mechanical signatures. Third, analog-to-digital conversion quantizes the signals at a 250 Hz sampling rate. Physical integration complies with military equipment standards for helmet structural integrity and ergonomic performance, ensuring full compatibility with existing flight gear without compromising protection or pilot comfort during extended missions.Computational Framework A multi-layer signal processing architecture is implemented to extract physiological features. Raw BCG signals undergo five-level discrete wavelet transformation using Daubechies-4 basis functions, effectively separating cardiac components from respiratory modulation and motion-induced artifacts. J-wave identification is achieved through dual-threshold detection: morphological amplitudes exceeding three times the local baseline standard deviation and temporal positioning within 200 ms sliding analysis windows. Extracted J–J intervals are treated as functional analogs of ElectroCardioGram (ECG)-derived R–R intervals. Time-domain HRV metrics are computed as follows: (1) Standard Deviation of NN intervals (SDNN), representing overall autonomic modulation; (2) Root Mean Square of Successive Differences (RMSSD), indicating parasympathetic activity; (3) Percentage of adjacent intervals differing by more than 50 ms (pNN50). Frequency-domain analysis applies Fourier transformation to quantify Low-Frequency (LF: 0.04–0.15 Hz) and High-Frequency (HF: 0.15–0.4 Hz) spectral powers. The LF/HF ratio is used to assess sympathetic–parasympathetic balance. The entire processing pipeline is optimized for real-time execution under in-flight operational conditions. Results and Discussions System validation is conducted under simulated flight conditions to evaluate physiological monitoring performance. Signal acquisition is found to be reliable across static, turbulent, and high-G scenarios, with consistent capture of BCG waveforms. Quantitative comparisons with synchronized ECG recordings show strong agreement between measurement modalities: (1) SDNN: 95.80%; (2) RMSSD: 94.08%; (3) LF/HF ratio: 92.86%. These results demonstrate that the system achieves physiological measurement equivalence to established clinical standards. Artifact suppression is effectively performed by the wavelet-based signal processing framework, which maintains waveform integrity under conditions of aircraft vibration and rapid gravitational transition—conditions where conventional ECG monitoring often fails. Among tested sensor placements, the occipital position exhibits the highest signal-to-noise ratio. Operational stability is maintained during continuous 6-hour monitoring sessions, with no observed signal degradation. This long-duration robustness indicates suitability for extended flight operations.Validation results indicate that the BCG-based approach addresses three primary limitations associated with ECG systems in aviation. The removal of electrode–skin contact mitigates the risk of contact dermatitis during prolonged wear. Non-contact sensing eliminates susceptibility to electromagnetic interference generated by radar and communication systems. Furthermore, mechanical coupling ensures signal continuity during abrupt gravitational changes, which typically displace ECG electrodes and cause signal dropout. The wavelet decomposition method is particularly effective in attenuating rotorcraft harmonic vibrations and turbulence-induced high-frequency noise. Autonomic nervous system modulation is reliably captured through pulse transit time variability, which aligns with neurocardiac regulation indices derived from ECG. Two operational considerations are identified. First, respiratory coupling under hyperventilation may introduce artifacts that require additional filtering. Second, extreme cervical flexion exceeding 45 degrees may degrade signal quality, indicating the potential benefit of redundant sensor configurations under such conditions. Conclusions This study establishes a functional, helmet-integrated BCG monitoring system capable of delivering medical-grade HRV metrics without compromising flight safety protocols. The technology represents a shift from contact-based to non-contact physiological monitoring in aviation settings. Future system development will incorporate: (1) Infrared eye-tracking modules to assess blink interval variability for objective fatigue evaluation; (2) Dry-contact electroencephalography sensors to quantify prefrontal cortex activity and assess cognitive workload; (3) Multimodal data fusion algorithms to generate unified indices of physiological strain. The integrated framework aims to enable real-time pilot state awareness during critical operations such as aerial combat maneuvers, hypoxia exposure, and emergency responses. Further technology maturation will prioritize operational validation across diverse aircraft platforms and environmental conditions. System implementation remains fully compliant with military equipment specifications and is positioned for future translation to commercial aviation and human factors research. Broader applications include astronaut physiological monitoring during spaceflight missions and enhanced safety systems in high-performance motorsports.
Available online , doi: 10.11999/JEIT250157
Abstract:
Objective The rapid advancement of machine learning has accelerated the development of artificial intelligence applications based on big data. Deep Neural Networks (DNNs) are now widely used in real-world systems, including autonomous driving and facial recognition. Despite their advantages, DNNs remain vulnerable to adversarial attacks, particularly in image recognition, which exposes significant security risks. Attackers can generate carefully crafted adversarial examples that appear visually indistinguishable from benign inputs but cause incorrect model predictions. In critical applications, such attacks may lead to system failures. Studying adversarial attack strategies is crucial for designing effective defenses and improving model robustness in practical deployments. Methods This paper proposes a black-box adversarial attack method termed Spectral Coefficient Attenuation (SCA), based on Spectral Coefficient Decay (SCD). SCA perturbs spectral coefficients during the iterative generation of adversarial examples by attenuating the amplitude of each frequency component. This attenuation introduces diverse perturbation patterns and reduces the dependency of adversarial examples on the source model, thereby improving their transferability across models. Results and Discussions This study generated adversarial examples using three naturally trained deep models based on Convolutional Neural Network (CNN) architectures and evaluated their attack success rates against several widely used convolutional image recognition models. Compared with MI-FGSM, the proposed method achieved average increases in attack success rates of 4.7%, 4.1%, and 4.9%, respectively. To further assess the effectiveness of the SCA algorithm, additional experiments were conducted on vision models based on Transformer architectures. In these settings, the SCA method yielded average success rate improvements of 4.6%, 4.5%, and 3.7% compared with MI-FGSM. Conclusions The proposed method attenuates the energy of individual spectral components during the iterative generation of adversarial examples in the frequency domain. This reduces reliance on specific features of the source model, mitigates the risk of overfitting, and enhances black-box transferability across models with different architectures. Extensive experiments on the ImageNet validation set confirm the effectiveness of the SCA method. Whether targeting CNN-based or Transformer-based models, the SCA algorithm consistently achieves high transferability and robust attack performance.
Available online , doi: 10.11999/JEIT250035
Abstract:
Objective Depression is a globally prevalent mental disorder that poses a serious threat to the physical and mental health of millions of individuals. Early screening and diagnosis are essential to reducing severe consequences such as self-harm and suicide. However, conventional questionnaire-based screening methods are limited by their dependence on the reliability of respondents’ answers, their difficulty in balancing efficiency with accuracy, and the uneven distribution of medical resources. New auxiliary screening approaches are therefore needed. Existing Artificial Intelligence (AI) methods for depression detection based on facial features primarily emphasize global expressions and often overlook subtle local cues such as eye features. Their performance also declines in scenarios where partial facial information is obscured, for instance by masks, and they raise privacy concerns. This study proposes a Global-Local Fusion Axial Network (GLFAN) for depression screening. By jointly extracting global facial and local eye features, this approach enhances screening accuracy and robustness under complex conditions. A corresponding dataset is constructed, and experimental evaluations are conducted to validate the method’s effectiveness. The model is deployed on edge devices to improve privacy protection while maintaining screening efficiency, offering a more objective, accurate, efficient, and secure depression screening solution that contributes to mitigating global mental health challenges. Methods To address the challenges of accuracy and efficiency in depression screening, this study proposes GLFAN. For long-duration consultation videos with partial occlusions such as masks, data preprocessing is performed using OpenFace 2.0 and facial keypoint algorithms, combined with peak detection, clustering, and centroid search strategies to segment the videos into short sequences capturing dynamic facial changes, thereby enhancing data validity. At the model level, GLFAN adopts a dual-branch parallel architecture to extract global facial and local eye features simultaneously. The global branch uses MTCNN for facial keypoint detection and enhances feature extraction under occlusion using an inverted bottleneck structure. The local branch detects eye regions via YOLO v7 and extracts eye movement features using a ResNet-18 network integrated with a convolutional attention module. Following dual-branch feature fusion, an integrated convolutional module optimizes the representation, and classification is performed using an axial attention network. Results and Discussions The performance of GLFAN is evaluated through comprehensive, multi-dimensional experiments. On the self-constructed depression dataset, high accuracy is achieved in binary classification tasks, and non-depression and severe depression categories are accurately distinguished in four-class classification. Under mask-occluded conditions, a precision of 0.72 and a precision of 0.690 are obtained for depression detection. Although these values are lower than the precision of 0.87 and precision of 0.840 observed under non-occluded conditions, reliable screening performance is maintained. Compared with other advanced methods, GLFAN achieves higher recall and F1 scores. On the public AVEC2013 and AVEC2014 datasets, the model achieves lower Mean Absolute Error (MAE) values and shows advantages in both short- and long-sequence video processing. Heatmap visualizations indicate that GLFAN dynamically adjusts its attention according to the degree of facial occlusion, demonstrating stronger adaptability than ResNet-50. Edge device tests further confirm that the average processing delay remains below 17.56 milliseconds per frame, and stable performance is maintained under low-bandwidth conditionsThe performance of GLFAN is evaluated through comprehensive, multi-dimensional experiments. On the self-constructed depression dataset, high accuracy is achieved in binary classification tasks, and non-depression and severe depression categories are accurately distinguished in four-class classification. Under mask-occluded conditions, a precision of 0.72 and a recall of 0.690 are obtained for depression detection. Although these values are lower than the precision of 0.87 and recall of 0.840 observed under non-occluded conditions, reliable screening performance is maintained. Compared with other advanced methods, GLFAN achieves higher recall and F1 scores. On the public AVEC2013 and AVEC2014 datasets, the model achieves lower Mean Absolute Error (MAE) values and shows advantages in both short- and long-sequence video processing. Heatmap visualizations indicate that GLFAN dynamically adjusts its attention according to the degree of facial occlusion, demonstrating stronger adaptability than ResNet-50. Edge device tests further confirm that the average processing delay remains below 17.56 frame/s, and stable performance is maintained under low-bandwidth conditions. Conclusions This study proposes a depression screening approach based on edge vision technology. A lightweight, end-to-end GLFAN is developed to address the limitations of existing screening methods. The model integrates global facial features extracted via MTCNN with local eye-region features captured by YOLO v7, followed by effective feature fusion and classification using an Axial Transformer module. By emphasizing local eye-region information, GLFAN enhances performance in occluded scenarios such as mask-wearing. Experimental validation using both self-constructed and public datasets demonstrates that GLFAN reduces missed detections and improves adaptability to short-duration video inputs compared with existing models. Grad-CAM visualizations further reveal that GLFAN prioritizes eye-region features under occluded conditions and shifts focus to global facial features when full facial information is available, confirming its context-specific adaptability. The model has been successfully deployed on edge devices, offering a lightweight, efficient, and privacy-conscious solution for real-time depression screening.
Available online , doi: 10.11999/JEIT250292
Abstract:
Objective As ML-KEM/Kyber is adopted as a post-quantum key encapsulation mechanism, securing its hardware implementations against Side-Channel Attacks (SCAs) has become critical. Although Kyber offers mathematically proven security, its physical implementations remain susceptible to timing-based side-channel leakage, particularly during Polynomial Point-Wise Multiplication (PWM), a core operation in decryption. Existing countermeasures, such as masking and static hiding, struggle to balance security, resource efficiency, and hardware feasibility. This study proposes a dynamic randomization strategy to disrupt execution timing patterns in PWM, thereby improving side-channel resistance in Kyber hardware designs. Methods A randomized pseudo-round hiding technique is developed to obfuscate the timing profile of PWM computations. The approach incorporates two key mechanisms: (1) dynamic insertion of redundant modular operations (e.g., dummy additions and multiplications), and (2) two-level pseudo-random scheduling based on Linear Feedback Shift Registers (LFSRs). These mechanisms randomize the execution order of PWM operations while reusing existing butterfly units to reduce hardware overhead. The design is implemented on a Xilinx Spartan-6 FPGA and evaluated using Correlation Power Analysis (CPA) and Test Vector Leakage Assessment (TVLA). Results and Discussions Experimental results demonstrate a substantial improvement in side-channel resistance. In unprotected implementations, attackers could recover Kyber’s long-term secret key using as few as 897 to 1,650 power traces. With the proposed countermeasure applied, no successful key recovery occurred even after 10,000 traces, representing more than a 100-fold increase in the number of traces required for key extraction. TVLA results (Fig. 6 ) confirm the suppression of leakage, with t-test values maintained near the threshold (|t| < 4.5). The resource overhead remains within acceptable bounds: the area-time product increases by 17.99%, requiring only 157 additional Look-Up Tables (LUTs) and 99 Flip-Flops (FFs) compared with the unprotected design. The proposed architecture outperforms existing masking and hiding schemes (Table 3 ), delivering stronger security with lower resource consumption. Conclusions This work presents an efficient and lightweight countermeasure against timing-based SCAs for Kyber hardware implementations. By dynamically randomizing PWM operations, the design significantly enhances side-channel security while maintaining practical resource usage. Future research will focus on optimizing pseudo-round scheduling to reduce latency, extending protection to Kyber’s Fujisaki–Okamoto (FO) transformation modules, and generalizing the method to other Number-Theoretic Transform (NTT)-based lattice cryptographic algorithms such as Dilithium. These developments support the secure and scalable deployment of post-quantum cryptographic systems.
Available online , doi: 10.11999/JEIT250198
Abstract:
Objective Side-Channel Analysis (SCA) presents a significant threat to the hardware implementation of cryptographic algorithms. Among various sources of side-channel leakage, power consumption is particularly vulnerable due to its ease of extraction and interpretation, making power analysis one of the most prevalent SCA techniques. To address this threat, masking has been widely adopted as a countermeasure in hardware security. Masking introduces randomness to disrupt the correlation between sensitive intermediate data and observable side-channel information, thereby enhancing resistance to SCA. However, existing masking approaches face notable limitations. Algorithm-level masking requires comprehensive knowledge of algorithmic structure and does not reliably strengthen hardware-level security. Masking applied at the Register Transfer Level (RTL) is prone to structural alterations during hardware synthesis and is constrained by the need for logic optimization, limiting scalability. Gate-level masking offers certain advantages, yet such approaches depend on precise localization of leakage and often incur unpredictable overhead after deployment. Furthermore, many masking schemes remain susceptible to higher-order SCA techniques. To overcome these limitations, there is an urgent need for gate-level masking strategies that provide robust security, maintain acceptable overhead, and support scalable deployment in practical hardware systems. Methods To address advances in SCA techniques and the limitations of existing masking schemes, this paper proposes a hybrid-order masking method. The approach is specifically designed for gate-level netlist circuits to provide fine-grained and precise protection. By considering the structural characteristics of encryption algorithm circuits, the method integrates masking structures of different orders according to circuit requirements, introduces randomness to sensitive variables, and substantially improves resistance to side-channel attacks. In parallel, the approach accounts for potential hardware overhead to maintain practical feasibility. Theoretical security is verified through statistical evaluation combined with established SCA techniques. An automated deployment framework is developed to facilitate rapid and efficient application of the masking scheme. The framework incorporates functional modules for circuit topology analysis, leakage identification, and masking deployment, supporting a complete workflow from circuit analysis to masking implementation. The security performance of the masked design is further assessed through correlation-based evaluation methods and simulation. Results and Discussions The automated masking deployment tool is applied to implement gate-level masking for Advanced Encryption Standard (AES) circuits. The security of the masked design is evaluated through first-order and higher-order power analysis in simulation. The correlation coefficient and Minimum Traces to Disclosure (MTD) parameter serve as the primary evaluation metrics, both widely used in side-channel security assessment. The MTD reflects the number of power traces required to extract the encryption key from the circuit. In first-order power analysis, the unmasked design exhibits a maximum correlation value of 0.49 for the correct key (Fig. 6(a) ), and the correlation curve for the correct key is clearly separated from those of incorrect keys. By contrast, the masked design reduces the correlation to approximately 0.02 (Fig. 6(b) ), with no evidence of successful key extraction. Based on the MTD parameter, the unmasked design requires 116 traces for key disclosure, whereas the masked design requires more than 200,000 traces, reflecting an improvement exceeding 1724 times (Fig. 7 ). Higher-order power analysis yields consistent results. The unmasked design demonstrates an MTD of 120 traces, indicating clear vulnerability, whereas the masked design maintains a maximum correlation near 0.02 (Fig. 8 ) and an MTD greater than 200,000 traces (Fig. 9 ), corresponding to a 1667 -fold improvement. In terms of hardware overhead, the masked design shows a 1.2% increase in area and a 41.1% reduction in maximum operating frequency relative to the unmasked circuit. Conclusions This study addresses the limitations of existing masking schemes by proposing a hybrid-order masking method that disrupts the conventional definition of protection order. The approach safeguards sensitive data during cryptographic algorithm operations and enhances resistance to SCA in gate-level hardware designs. An automated deployment tool is developed to efficiently integrate vulnerability identification and masking protection, supporting practical application by hardware designers. The proposed methodology is validated through correlation analysis across different orders. The results demonstrate that the method improves resistance to power analysis attacks by more than 1600 times and achieves significant security enhancement with minimal hardware overhead compared to existing masking techniques. This work advances the current knowledge of masking strategies and provides an effective approach for improving hardware-level security. Future research will focus on extending the method to broader application scenarios and enhancing performance through algorithmic improvements.
Available online , doi: 10.11999/JEIT250410
Abstract:
Objective To improve the performance of 3D NAND architecture, a series of horizontal and vertical miniaturization strategies have been proposed. While these designs increase storage density, they also introduce integration challenges. In particular, thermo-mechanical stress during fabrication has become a critical limitation on device yield and performance. This study establishes a high-precision process mechanics model of 3D NAND based on a local Representative Volume Element (RVE) finite element modeling framework, accounting for the multilayer stacked structure and various block architecture designs. By systematically investigating stress evolution during fabrication, the analysis identifies the root causes of stress non-uniformity and characterizes the dynamic distribution of mechanical stress under different miniaturization schemes. These findings have practical relevance for yield improvement and device reliability, addressing key challenges in advancing 3D NAND storage density. Methods This study constructs a high-precision, device-level finite element model of 3D NAND based on the theory of RVE. The simulation of thermal stress evolution throughout the manufacturing process uses the element birth/death technique in Abaqus. The baseline model features a representative 3D NAND structure comprising 8 Nitride/Oxide (N/O) bilayers, each 25 nm thick. Within a 40-nm-wide slit, 15 storage pillars, each with a diameter of 24 nm and spaced at 36 nm intervals, are arranged in a staggered configuration. To explore the effect of stacking layer number on stress evolution, modified models with 6 and 10 N/O layers are also developed. In addition, to examine the effect of different block architecture transitions, models incorporating 5 and 10 pillars per block are analyzed. The material properties used are consistent with those reported in previous studies, where both the calibration of material parameters and the modeling methodology are validated. Results and Discussions Process-dependent simulations were conducted to examine the evolution of stress distribution during key 3D NAND fabrication steps and to assess the effects of vertical stacking layers (Fig. 7 ) and block architecture designs (Fig. 8 ). The results show that metal volume fraction, the number of pillars in the array region, and the presence of oxide stairs are primary factors influencing stress distribution. A higher metal volume fraction markedly increases internal stress due to thermal expansion mismatch. Asymmetric metal layouts in the Word Line (WL) and Bit Line (BL) directions intensify stress anisotropy between these axes. Pillars in the array region help alleviate stress concentration by generating tensile zones during nitride/metal thermal deformation, thereby reducing the overall compressive stress. In contrast, oxide stairs constrain deformation along the WL direction, inhibiting stress relaxation and resulting in localized compressive regions. These combined mechanisms indicate that increasing the number of WL layers tends to enhance stress asymmetry, whereas block architectures with a larger number of pillars reduce the degree of stress non-uniformity. Conclusions Using a process mechanics model based on the RVE approach, this study explored stress evolution in 3D NAND fabrication. The effects of two major scaling strategies—vertical layer stacking and horizontal block architecture conversion—were systematically analyzed with respect to stress magnitude and directional asymmetry. The results show that asymmetric stress distribution originates during the step etching stage and peaks following WL and slot filling. As the number of vertical stacking layers increases, structural compressive stress intensifies, particularly in the WL and BL directions. Increasing the number of layers from 6 to 10 results in an 8.54 MPa rise in WL compressive stress and a 5.66 MPa rise in BL stress, with the WL–BL stress difference increasing from 20.76 MPa to 24.64 MPa. Larger-area block architectures effectively mitigate stress asymmetry. Compared with the 5-pillar configuration, the 15-pillar architecture reduces WL–BL stress asymmetry by 22.4%. The composite structure of oxide and tungsten, combined with the constraint effects of pillars and stepped oxide on sacrificial layer deformation, plays a central role in modulating stress levels and directional distribution in 3D NAND structures.
Available online , doi: 10.11999/JEIT250280
Abstract:
Objective Radar electronic warfare systems rely on Pulse Descriptor Words (PDWs) to represent radar signals, capturing key parameters such as Time of Arrival (TOA), Carrier Frequency (CF), Pulse Width (PW), and Pulse Amplitude (PA). However, in complex electromagnetic environments, the scarcity of PDW data limits the effectiveness of data-driven models in radar pattern recognition. Conventional augmentation methods (e.g., geometric transformations, SMOTE) fall short in addressing three core issues: (1) failure to capture temporal physical laws (e.g., gradual frequency shifts and pulse modulation patterns); (2) distributional inconsistencies (e.g., frequency band overflows and PW discontinuities); and (3) weak coupling between PDWs and modulation types, leading to reduced classification accuracy. This study proposes Time-CondGAN, a temporal-conditional generative adversarial network designed to generate physically consistent and modulation-specific PDW sequences, enhancing few-shot radar reconnaissance performance. Methods Time-CondGAN integrates three core innovations: (1) Multimodal Conditional Generation Framework: A label encoder maps discrete radar modulation types (e.g., VS, HRWS, TWS in Table 2 ) into 128-dimensional feature vectors. These vectors are temporally expanded and concatenated with latent noise to enable category-controllable generation. The generator architecture (Fig. 4 ) employs bidirectional Gated Recurrent Units (GRUs) to capture long-range temporal dependencies. (2) Multi-task Discriminator Design: The discriminator (Fig. 5 ) is designed for joint adversarial discrimination and signal classification. A shared bidirectional GRU with an attention mechanism extracts temporal features, while classification loss constrains the generator to maintain category-specific distributions. (3) Temporal-Statistical Joint Optimization: The training process incorporates multiple loss components: Supervisor Loss (Eq. 7): A bidirectional GRU-based supervisor enforces temporal consistency. Feature Matching Loss (Eq. 9): Encourages alignment between high-level features of real and synthetic signals. Adversarial and Classification Losses (Eqs. (8)–(9)): Promote distribution realism and accurate category separation. A two-stage training strategy is adopted to improve stability, consisting of pre-training (Fig. 2 ) followed by adversarial training (Fig. 3 ). Results and Discussions Time-CondGAN demonstrates strong performance across three core dimensions. (1) Physical plausibility is achieved through accurate modeling of radar signal dynamics. Compared with TimeGAN, Time-CondGAN reduces the Kullback-Leibler (KL) divergence by 28.25% on average. Specifically, the PW distribution error decreases by 50.20% (KL = 4.68), the TOA interval error decreases by 20.5% (KL = 0.636), and the CF deviation is reduced by 13.29% (KL = 7.93), confirming the suppression of non-physical signal discontinuities. (2) Downstream task enhancement highlights the model’s few-shot generation capability. With only 10 real samples, classification accuracy improves markedly: VGG16 accuracy increases by 37.2% (from 43.0% to 59.0%) and LSTM accuracy by 28.6% (from 49.0% to 63.0%), both substantially outperforming conventional data augmentation methods. (3) Ablation studies validate the contribution of key modules. Removing the conditional encoder increases the PW KL divergence by 107.4%. Excluding the supervisor loss degrades CF continuity by 76.2%, and omitting feature matching results in a 44.6% misalignment in amplitude distribution. Conclusions This study establishes Time-CondGAN as an effective solution for radar PDW generation under few-shot conditions, addressing three key limitations: temporal fragmentation is resolved through bidirectional GRU supervision, mode collapse is alleviated via multimodal conditioning, and modulation specificity is maintained by classification constraints. The proposed framework offers operational value, enabling over 35% improvement in recognition accuracy under low-intercept conditions. Future work will incorporate radar propagation physics to refine amplitude modeling (current KL = 8.51), adopt meta-learning approaches for real-time adaptation in dynamic battlefield environments, and expand the model to multi-radar cooperative scenarios to support heterogeneous electromagnetic contexts.
Available online , doi: 10.11999/JEIT250317
Abstract:
Objective The rapid advancement of technologies such as artificial intelligence and the Internet of Things has placed increasing strain on traditional centralized cloud computing architectures, which struggle to meet the communication and computational demands of large-scale data processing. Due to the physical separation between cloud servers and end-users, data transmission typically incurs considerable latency and energy consumption. Therefore, edge computing—by deploying computing and storage resources closer to users, has emerged as a viable paradigm for supporting data-intensive and latency-sensitive applications. However, effectively addressing the challenges of data-intensive services in edge computing environments, such as efficient edge node clustering and resource scheduling, remains a key issue. This study proposes a data scheduling optimization method for edge networks that integrates an improved Jaya algorithm with a cluster center selection strategy. Specifically, for data-intensive services, the method partitions edge nodes into clusters and identifies optimal cluster centers. Data are first aggregated at these centers before being transmitted to the cloud. By leveraging cluster-based aggregation, the method facilitates more efficient data scheduling and improved resource management in edge environments. Methods The proposed edge network data scheduling optimization method comprises two core components: a shortest-path selection algorithm based on an improved Jaya algorithm and an optimal cluster center selection algorithm. The scheduling framework accounts for both the shortest communication paths among edge nodes and the availability of network resources. The improved Jaya algorithm incorporates a cosine-based nonlinear decay function and a multi-stage search strategy to dynamically optimize inter-node paths. The nonlinear decay function modulates the variation of random factors across iterations, allowing adaptive adjustment of the algorithm’s exploration capacity. This mechanism helps prevent premature convergence and reduces the likelihood of becoming trapped in local optima during the later optimization stages. To further enhance performance, a multi-stage search strategy divides the optimization process into two phases: an exploration phase during early iterations, which prioritizes global search across the solution space, and an exploitation phase during later iterations, which refines solutions locally. This staged approach improves the trade-off between convergence speed and solution accuracy, increasing the algorithm’s robustness in complex edge network environments. Based on the optimized paths and available bandwidth, a criterion is established for selecting the initial cluster center. Subsequently, a selection scheme for additional cluster centers is formulated by evaluating inter-cluster center distances. Finally, a partitioning method assigns edge nodes to their respective clusters based on the optimized topology. Results and Discussions The simulation experiments comprise two parts: performance evaluation of the improved Jaya algorithm (Jaya*) and analysis of the cluster partitioning scheme. To assess convergence speed and optimization accuracy, three benchmark test functions are used to compare Jaya* with four existing algorithms: Simulated Annealing (SA), Genetic Algorithm (GA), Ant Colony Optimization (ACO), and the standard Jaya algorithm. Building on these results, two additional experiments—cluster center selection and cluster partitioning—are conducted to evaluate the feasibility and effectiveness of the proposed optimal cluster center selection algorithm for resource scheduling. A parameter sensitivity analysis using the multi-modal Rastrigin function is performed to investigate the effects of different population sizes and maximum iteration counts on optimization accuracy and stability (Table 2 and Table 3 ). The optimal configuration is determined to be \begin{document}$ {\text{po}}{{\text{p}}_{{\text{size}}}} = 50 $\end{document} \begin{document}$ {t_{\max }} = 500 $\end{document} Fig. 4 ), Rastrigin (Fig. 5 ), and Griewank (Fig. 6 ). The algorithm also demonstrates superior stability. Its convergence trajectory is characterized by a rapid initial decline followed by gradual stabilization in later stages. Based on these findings, the cluster center selection algorithm is applied to tactical edge networks of varying scales—25, 38, and 50 nodes (Fig. 7 ). The parameter mi is calculated (Fig. 8 ), and various numbers of cluster centers are set to complete center selection and cluster member assignment (Table 5 ). Evaluation using the Average Sum of Squared Errors (AvgSSE) under different cluster center counts reveals that the minimum AvgSSE for all three network sizes occurs when the number of cluster centers is 4 (Table 6 ), indicating that this configuration yields the optimal clustering outcome. Therefore, the proposed method effectively selects cluster centers and derives the optimal clustering configuration (Fig. 9 ), while maintaining low clustering error and enhancing the efficiency and accuracy of resource scheduling. Finally, in a 38-node edge network scenario with four cluster centers, a multi-algorithm cluster partitioning comparison is conducted (Table 7 ). The improved Jaya algorithm achieves the best AvgSSE result of 16.22, significantly outperforming the four baseline algorithms. These results demonstrate its superiority in convergence precision and global search capability. Conclusions To address data resource scheduling challenges in edge computing environments, this study proposes an edge network data scheduling optimization method that integrates an improved Jaya algorithm with a cluster center selection strategy. The combined approach achieves high clustering accuracy, robustness, and generalization performance. It effectively enhances path planning precision and central node selection, leading to improved data transmission performance and resource utilization in edge networks.
Available online , doi: 10.11999/JEIT250162
Abstract:
Objective Reconfigurable Intelligent Surface (RIS)-aided Spatial Modulation (SM) systems (RIS-SM) represent an advanced integration of two promising technologies, offering considerable potential to enhance spectral and energy efficiency in future Sixth-Generation (6G) networks. However, the passive nature of RIS poses a significant challenge to acquiring accurate Channel State Information (CSI), which is essential for conventional signal detection methods. Most traditional algorithms assume perfect CSI, an unrealistic assumption in practical deployments that constrains both performance and scalability. To overcome this limitation, this study proposes an enhanced K-means clustering detection algorithm that reframes the blind detection problem as a clustering task. By exploiting the statistical channel distribution properties inherent to RIS-SM systems, the proposed algorithm achieves efficient blind signal detection without prior CSI and with low computational complexity. These findings contribute to the optimization of RIS-SM system performance and support the development of robust blind detection strategies in complex wireless communication scenarios. Methods This study considers a typical RIS-SM architecture in which the RIS comprises multiple passive reflecting elements and the receiver is equipped with multiple antennas. The wireless channel is modeled as an equivalent channel derived from the unique propagation characteristics of the RIS-SM system. By exploiting the statistical distribution of the diagonal elements of this equivalent channel, an improved K-means clustering detection algorithm is proposed, eliminating the requirement for prior CSI. The algorithm’s performance is assessed through extensive simulations. The communication channel is modeled as a Rayleigh fading environment with Additive White Gaussian Noise (AWGN). Phase Shift Keying (PSK) and Quadrature Amplitude Modulation (QAM) schemes are adopted. Bit Error Rate (BER) is used as the primary performance metric to compare the proposed approach against conventional detection methods. Simulations are carried out on the MATLAB platform. Results demonstrate that the proposed algorithm significantly lowers computational complexity while achieving near-optimal detection accuracy, highlighting its suitability for practical deployment in RIS-SM systems. Results and Discussions Simulation results indicate that the proposed improved K-means clustering detection algorithm markedly enhances the performance of RIS-SM systems under unknown CSI conditions. As illustrated in Fig. 4 and Fig. 5 , the proposed method achieves BER performance that closely approaches that of ideal KMC (KMC(ideal)) and Maximum Likelihood (ML) detectors. It outperforms several benchmark algorithms, including traditional KMC, multi-initialization KMC (KMC(\begin{document}$ P $\end{document} \begin{document}$ P $\end{document} Fig. 6 demonstrates that the proposed algorithm converges more rapidly than other clustering-based methods, particularly under low SNR conditions, highlighting its robustness and efficiency in noisy environments. Table 1 provides additional evidence that the proposed method achieves a favorable balance between detection accuracy and computational cost, supporting its practical value for blind detection in RIS-SM systems. Conclusions This study proposes an improved K-means clustering detection algorithm for RIS-SM systems, reformulating the blind detection task as an unsupervised clustering problem. By exploiting the distribution properties of the diagonal elements of the equivalent channel, the algorithm enhances the initialization of clustering centroids, enabling efficient blind signal detection without prior CSI. Simulation results confirm that the proposed method achieves near-optimal detection performance across a wide range of SNR levels and system configurations. These findings offer meaningful contributions to both the theoretical development and practical deployment of RIS-SM systems. The proposed approach is particularly relevant for the design of low-complexity and high-efficiency detection schemes in next-generation wireless networks, including Beyond-5G (B5G) and 6G systems. This work also provides a foundation for future research on blind detection algorithms and their integration with emerging technologies such as RIS, contributing to the advancement of intelligent and adaptive wireless communication systems.
Available online , doi: 10.11999/JEIT250272
Abstract:
Objective The integration of heterogeneous computing resource clusters into modern Hyper-Converged Infrastructure (HCI) systems imposes stricter performance requirements in latency, bandwidth, throughput, and cross-domain transmission stability. Traditional HCI systems primarily rely on the Ethernet TCP/IP protocol, which exhibits inherent limitations, including low bandwidth efficiency, high latency, and limited throughput. Existing PCIe Switch products typically employ Non-Transparent Bridges (NTBs) for conventional dual-system connections or intra-server communication; however, they do not meet the performance demands of heterogeneous cross-domain transmission within HCI environments. To address this limitation, a novel Dual-Mode Non-Transparent Bridge Architecture (D-MNTBA) is proposed to support dual transmission modes. D-MNTBA combines a fast transmission mode via a bypass mechanism with a stable transmission mode derived from the Traditional Data Path Architecture (TDPA), thereby aligning with the data characteristics and cross-domain streaming demands of HCI systems. Hardware-level enhancements in address and ID translation schemes enable D-MNTBA to support more complex mappings while minimizing translation latency. These improvements increase system stability and effectively support the cross-domain transmission of heterogeneous data in HCI systems. Methods To overcome the limitations of traditional single-pass architectures and the bypass optimizations of the TDPA, the proposed D-MNTBA incorporates both a fast transmission path and a stable transmission path. This dual-mode design enables the NTB to leverage the data characteristics of HCI systems for telegram-based streaming, thereby reducing dependence on intermediate protocols and data format conversions. The stable transmission mode ensures reliable message delivery, while the fast transmission mode—enhanced through hardware-level optimizations in address and ID translation—supports high-real-time cross-domain communication. This combination improves overall transmission performance by reducing both latency and system overhead. To meet the low-latency demands of the bypass transmission path, the architecture implements hardware-level enhancements to the address and ID conversion modules. The address translation module is expanded with a larger lookup table, allowing for more complex and flexible mapping schemes. This enhancement enables efficient utilization of non-contiguous and fragmented address spaces without compromising performance. Simultaneously, the ID conversion module is optimized through multiple conversion strategies and streamlined logic, significantly reducing the time required for ID translation. Results and Discussions Address translation in the proposed D-MNTBA is validated through emulation within a constructed HCI environment. The simulation log for indirect address translation shows no errors or deadlocks, and successful hits are observed on BAR2/3. During dual-host disk access, packet header addresses and payload content remain consistent, with no packet loss detected (Fig. 14 ), indicating that indirect address translation is accurately executed under D-MNTBA. ID conversion performance is evaluated by comparing the proposed architecture with the TDPA implemented in the PEX8748 chip. The switch based on D-MNTBA exhibits significantly shorter ID conversion times. A maximum reduction of approximately 34.9% is recorded, with an ID conversion time of 71 ns for a 512-byte payload (Fig. 15 ). These findings suggest that the ID function mapping method adopted in D-MNTBA effectively reduces conversion latency and enhances system performance. Throughput stability is assessed under sustained heavy traffic with payloads ranging from 256 to 2048 bytes. The maximum throughputs of D-MNTBA, the Ethernet card, and PEX8748 are measured at 1.36 GB/s, 0.97 GB/s, and 0.9 GB/s, respectively (Fig. 16 ). Compared to PEX8748 and the Ethernet architecture, D-MNTBA improves throughput by approximately 51.1% and 40.2%, respectively, and shows the slowest degradation trend, reflecting superior stability in heterogeneous cross-domain transmission. Bandwidth comparison reveals that D-MNTBA outperforms TDPA and the Ethernet card, with bandwidth improvements of approximately 27.1% and 19.0%, respectively (Fig. 17 ). These results highlight the significant enhancement in cross-domain transmission performance achieved by the proposed architecture in heterogeneous environments. Conclusions This study proposes a Dual-Mode D-MNTBA to address the challenges of heterogeneous interconnection in HCI systems. By integrating a fast transmission path enabled by a bypass architecture with the stable transmission path of the TDPA, D-MNTBA accommodates the specific data characteristics of cross-domain transmission in heterogeneous environments and enables efficient message routing. D-MNTBA enhances transmission stability while improving system-wide performance, offering robust support for high-real-time cross-domain transmission in HCI. It also reduces latency and overhead, thereby improving overall transmission efficiency. Compared with existing transmission schemes, D-MNTBA achieves notable gains in performance, making it a suitable solution for the demands of heterogeneous domain interconnects in HCI systems. However, the architectural enhancements, particularly the bypass design and associated optimizations, increase logic resource utilization and power consumption. Future work should focus on refining hardware design, layout, and wiring strategies to reduce logic complexity and resource consumption without compromising performance.
Available online , doi: 10.11999/JEIT250302
Abstract:
Objective Object detection has advanced significantly under normal lighting conditions, supported by numerous high-accuracy, high-speed deep learning algorithms. However, in low-light environments, images exhibit reduced brightness, weak contrast, and severe noise interference, leading to blurred object edges and loss of color information, which substantially degrades detection accuracy. To address this challenge, this study proposes an end-to-end low-light object detection algorithm that balances detection accuracy with real-time performance. Specifically, an end-to-end network is designed to enhance feature quality and improve detection accuracy in real time under low-light conditions. Methods To improve object detection performance under low-light conditions while maintaining detection accuracy and real-time processing, this study proposes an end-to-end low-light image object detection method. Detection accuracy is enhanced through joint learning of image enhancement and feature adaptation, with the overall network structure shown in Fig. 1 . First, a data augmentation module synthesizes low-light images from normal-light images. The paired normal-light and low-light images are mixed using the MixUp function provided by YOLOv5 to generate the final low-light images. These synthesized images are input into the low-light image enhancement module. In parallel, the matched normal-light images are provided as supervision to train the image enhancement network. Subsequently, both the enhanced low-light images and the corresponding normal-light images are fed into the object detection module. After processing through the YOLOv5 backbone, a matching loss is computed to guide feature adaptation. Result and Discussions The experiments are conducted primarily on the Polar3000 and LLVIP datasets. Fig. 3 presents the detection results obtained using YOLOv5 with different image enhancement methods applied to the Polar3000 dataset. Most existing methods tend to misclassify overexposed regions as bright Unmanned Aerial Vehicles (UAVs). In contrast, the proposed method demonstrates accurate object detection in low-light conditions without misidentifying overexposed areas as UAVs (Fig. 3 ). Furthermore, the detection performance of the proposed method, termed MAET, is compared with that of a standalone YOLOv5 model. Quantitative experiments show that the proposed method outperforms both image-enhancement-first detection pipelines and recent low-light object detection methods across both experimental groups A and B, irrespective of low-light fine-tuning. On the LLVIP dataset, the proposed method achieves a detection accuracy of 91.7% (Table 1 ), while on the Polar3000 dataset, it achieves 92.3% (Table 2 ). The model also demonstrates superior generalization performance on the ExDark and DarkFace datasets (Tables 4 and 3 ). Additionally, compared to the baseline YOLOv5 model, the proposed method increases parameter size by only 2.5% while maintaining real-time detection speed (Table 5 ). Conclusions This study proposes a low-light object detection method based on joint learning of image enhancement and feature adaptation. The approach simultaneously optimizes image enhancement loss, feature matching loss, and object detection loss within an end-to-end framework. It improves image illumination, preserves fine details, and aligns the features of enhanced images with those acquired under normal lighting conditions, enabling high-precision object detection in low-light environments. Comparative experiments on the LLVIP and Polar3000 datasets demonstrate that the proposed method achieves improved detection accuracy while maintaining real-time performance. Furthermore, the method achieves the best generalization results on the ExDark and DarkFace datasets. Future work will explore low-light object detection based on multimodal data fusion of visible and infrared images to further enhance detection performance in extremely dark conditions.
Available online , doi: 10.11999/JEIT250366
Abstract:
Objective Kernel Address Space Layout Randomization (KASLR) remains a core defense against kernel-level exploits; however, its robustness is increasingly undermined by microarchitectural side-channel attacks that exploit specific processor instructions. Existing research has largely concentrated on isolated attack vectors, lacking a systematic evaluation of the entire x86 instruction set. This study addresses this limitation by developing an automated framework to identify and characterize KASLR-bypass instructions comprehensively, assess their attack efficacy across multiple Intel processor generations, and derive defensible instruction patterns to inform the reinforcement of current security mechanisms. Methods This study systematically addresses three core challenges in analyzing instruction-level mechanisms for bypassing KASLR. The first challenge is achieving comprehensive coverage of the x86 Instruction Set Architecture (ISA), which includes thousands of historical and modern instructions characterized by variable-length encoding and complex microarchitectural dependencies. To address this, the proposed framework combines static and dynamic analysis. Instruction semantics are extracted statically from Intel Software Developer Manuals and uops.info XML datasets. Dynamic profiling on Intel Core processors is used to verify instruction support across processor generations. Byte-level pattern matching is applied to accurately handle variable-length encodings. The second challenge concerns the generation of attack-compliant machine code that satisfies strict encoding requirements and bypasses compiler-level checks. This is achieved using a template-driven approach, which modifies a CLFLUSH-based attack prototype by replacing inline assembly instructions through pattern substitution. Memory operands are redirected to target addresses preloaded into the EDX register, with boundary values used to ensure operand validity. For nonstandard or undocumented instructions, self-modifying code techniques dynamically inject opcodes at runtime, thereby bypassing compiler restrictions and enabling broader instruction coverage. The third challenge focuses on evaluating attack effectiveness through accurate localization of kernel symbols. To this end, the framework applies a dual-verification strategy. RDTSC instructions are used to timestamp memory probes across 512 predefined address slots. Differential timing analysis identifies latency outliers (i.e., maximum and minimum values), indicating potential KASLR bypasses. Signal handlers suppress exceptions caused by access to privileged or unmapped memory regions, while debug symbol cross-referencing is used to confirm actual kernel address leakage. All generated code undergoes Monte Carlo simulation to reduce false positives and ensure statistical robustness. Results and Discussions Experiments are performed on Intel Core i7-11700K, i7-12700K, and i7-13700 processors (Table 1 ). In the Assembly-Level Instruction Analysis (Fig. 4 ), 699 assembly instructions are identified as effective KASLR bypass vectors on the i7-11700K. Variations in support for AVX512 instruction set extensions account for differences in the attack surface, with the number of effective instructions decreasing slightly to 542 on the i7-12700K and 547 on the i7-13700 , reflecting minor microarchitectural differences. In the Byte-Level Instruction Analysis (Table 2 ), 39 one-byte, 121 two-byte, and 24 three-byte opcodes are found to bypass KASLR without relying on predefined assembly semantics. These opcodes demonstrate consistent attack efficacy across all evaluated processors, indicating similar behavioral patterns across Intel architectures. Overall, the results—supported by (Fig. 4 , Table 2 , Table 3 )—demonstrate two principal findings: comprehensive coverage of the x86 ISA and cross-generation consistency of effective KASLR bypass instructions. Although the current study focuses on Intel processors, the findings raise open questions regarding the vulnerability of AMD processors that share the same ISA, as well as ARM-based platforms used in Android devices and Apple M series chips. Future work is intended to extend the framework to analyze KASLR bypass vectors on non-Intel architectures. Furthermore, an automated analysis framework is proposed to assess KASLR attack efficacy through differential analysis. To enhance detection across heterogeneous architectures and instruction sets, future efforts will incorporate data preprocessing techniques to improve the scalability and precision. Conclusions KASLR remains a critical defense against kernel memory exploitation; however, its resilience is increasingly challenged by instruction-dependent microarchitectural side-channel attacks. This study presents an automated framework that systematically identifies potential KASLR-bypass instructions, quantifies their attack effectiveness across multiple Intel processor generations, and derives actionable defense signatures to address emerging threats. The findings reveal a significantly underestimated attack surface: hundreds of x86 instructions, at both the assembly and byte levels, are capable of leaking sensitive address information. The broader implications of this work are threefold: (1) Defensive Improvement: The experimental results may be directly applied to enhance signature-based detection systems. (2) Hardware–Software Co-Design: The consistent vulnerability observed across Intel microarchitectures highlights the need to redesign timing isolation mechanisms at the hardware level. (3) Methodological Contribution: The proposed dual-analysis framework offers a generalizable approach for evaluating instruction-level attack surfaces, with applicability to other contexts such as cache-based side-channel attacks. Future research will extend this methodology to alternative architectures, including ARM and RISC-V, and explore the integration of machine learning techniques.
Available online , doi: 10.11999/JEIT250152
Abstract:
Objective Although existing resource management strategies can improve the performance of Multiple Target Tracking (MTT), they generally assume that targets are well separated. With the development of swarm intelligence, multiple maneuvering targets can adopt group merging and splitting tactics to enhance task efficiency. This often results in the presence of several closely spaced targets within a single tracking beam, making them difficult to distinguish. In such cases, networked radars must coordinate the allocation of signal bandwidth and pulse width to increase both the resolution of adjacent targets and overall MTT performance. However, previous studies have not accounted for the effect of signal resolution capability on MTT performance. When adjacent targets emerge in the surveillance region, resource allocation schemes derived from existing methods become insufficient. To address this limitation, this study proposes a joint Beam Selection and Multi-dimensional Resource Management (BSMRM) strategy. By jointly optimizing the transmit beam, power, signal bandwidth, and pulse width, the proposed approach markedly improves MTT performance for multiple groups of clustered maneuvering targets and enhances the resolution of adjacent targets within the surveillance area. Methods This study proposes a BSMRM strategy for netted radar systems to improve target resolution capability and MTT accuracy. First, the Bayesian Cramér-Rao Lower Bound (BCRLB) is derived under the Probabilistic Data Association (PDA) fusion rule and the Interacting Multiple Model-Extended Kalman Filter (IMM-EKF) framework. Resolution performance is quantified using the normalized magnitude of the ambiguity function for both observed and unobserved targets located within the beam. A utility function is then formulated using the logarithmic barrier method to quantify global performance. Multi-dimensional resource management is modeled as a constrained optimization problem, with the objective of maximizing global performance under system resource constraints. A three-stage solver is developed to address the optimization problem. Simulation results show that the proposed BSMRM strategy achieves comparable target resolution and MTT accuracy to state-of-the-art algorithms, while demonstrating superior efficiency in spectrum usage and power allocation. Results and Discussions As shown in (Table 1 ) and (Fig. 1 ), this study evaluates the effectiveness and robustness of the proposed BSMRM strategy in a complex scenario where four groups of swarm targets maneuver within the surveillance region of three radar nodes. The performance of the BSMRM strategy is assessed through four simulation experiments. Experiment 1 presents the allocation of transmission resources, including beam selection and power distribution. The results are shown in (Fig. 2 ), where color-coded regions represent normalized transmit power levels determined by the BSMRM strategy. Experiment 2 reports the allocation of waveform resources—specifically, signal bandwidth and pulse width. In this experiment, resolution thresholds corresponding to various target states are first established. The BSMRM strategy is then used to adjust the signal bandwidth and pulse width of each transmit beam to enable effective discrimination of swarm targets. Experiment 3 analyzes tracking performance through numerical simulations, comparing the proposed strategy with benchmark algorithms. A sequence of 60 tracking frames with a time interval of T = 2.5 s is simulated, with 300 Monte Carlo runs. Root Mean Square Error (RMSE) is used as the evaluation metric. (Fig. 4 ) displays the BCRLB and RMSE curves for each target group under the BSMRM strategy. The RMSE converges toward the corresponding BCRLBs, indicating that the proposed method meets tracking accuracy requirements across all target groups. When sufficient transmit power is available, the BSMRM strategy drives the accuracy to the desired thresholds, thereby maximizing utility. (Fig. 5 ) compares the normalized average power consumption of three strategies. (Figs. 6 and 7 ) show resolution performance curves for the BSMRM and JBPAWLS strategies, respectively. (Fig. 8 ) compares spectrum occupancy across two operational phases to assess spectral efficiency under resolution constraints. Experiment 4 evaluates the computational complexity of the BSMRM strategy. Results show that, with parallel computing, the strategy satisfies the real-time requirements of resource scheduling. Conclusions This study proposes a BSMRM strategy for MTT in a C-MIMO radar network. The strategy jointly optimizes beam selection, transmit power, signal bandwidth, and pulse length to improve both target resolvability and tracking accuracy. An efficient three-stage solver is developed to address the resulting optimization problem. Simulation results show that the proposed strategy achieves high-resolution MTT while reducing spectral occupancy. Under sufficient power conditions, tracking accuracy is comparable to that of state-of-the-art algorithms. In the same simulation environment, the average CPU runtime per frame is 2.8617 s, which is reduced to 0.3573 s with GPU-based parallel processing—meeting the real-time requirements for resource allocation. Moreover, the BSMRM strategy demonstrates flexibility and robustness under limited power constraints.
Available online , doi: 10.11999/JEIT250188
Abstract:
Significance Network security vulnerabilities arising from flaws in network protocol implementations cause substantial losses and adverse societal effects, exemplified by the Heartbleed vulnerability in OpenSSL (CVE-2014-0160). This flaw allows attackers to extract encryption keys from public servers, enabling decryption of traffic or unauthorized authentication on less secure systems. Approximately 500,000 internet servers are affected when the vulnerability is publicly disclosed. Against this backdrop of escalating network security risks, ensuring the security of network protocol software becomes a critical research area. Fuzzing, a software testing technique, emerges as one of the most widely used approaches for identifying vulnerabilities in network protocol implementations due to its ease of deployment and high efficiency. The core concept of fuzzing is to improve software security by generating and sending crafted test cases to the target program. Despite significant progress in this field, Network Protocol Fuzzing (NPF) still faces technical challenges. Currently, no systematic and up-to-date review of NPF research exists, limiting researchers’ ability to grasp recent advances. This paper conducts a comprehensive review of NPF techniques, aiming to provide researchers in the field of network protocol security with valuable references for tool selection and optimization. Progress Since the proposal of AFLNET in 2020, considerable progress occurs in the field of NPF, addressing key challenges such as protocol packet construction, protocol state awareness, and network communication efficiency optimization. Specifically, for protocol packet construction, researchers propose machine learning-based packet generation methods that integrate both generation and mutation strategies. Mutation operators and guidance techniques are designed to target specific protocol characteristics. In terms of protocol state awareness, state tracking capabilities are enhanced through state variable capture and state model construction. Furthermore, state fuzzing has been widely employed to detect state machine bugs. For protocol stack efficiency optimization, researchers improve testing efficiency by refining communication mechanisms and applying snapshot techniques. Conclusions To comprehensively summarize the research progress in NPF, this paper first clarifies the unique characteristics of network protocol software compared with other fuzzing targets. These characteristics include strict protocol message formats, asynchronous network interactions, and complex protocol state maintenance. A problem-oriented classification framework for NPF is proposed, structured around three core challenges: protocol packet construction, protocol state awareness, and protocol stack efficiency optimization. Based on this framework, research advancements in NPF over the past eight years are systematically reviewed, with a technical analysis of the capabilities, and limitations of existing approaches. This review highlights several key challenges in the field. For input construction, major limitations include weak validity of generated inputs, input space explosion, and restrictions imposed by encryption and authentication mechanisms. In terms of state awareness, the field faces insufficient protocol state space exploration and low levels of test intelligence and automation. Regarding performance optimization, technical challenges include slow network communication speed, limited scalability across different protocol implementations, and inadequate adaptability to complex network environments. This study provides both theoretical foundations and practical references to guide future research and technological development in the NPF domain. Prospects Future research in NPF can integrate emerging technologies such as Artificial Intelligence (AI) to enhance the intelligence and automation of testing processes. For example, combining AI methods with program analysis techniques may enable a deeper understanding of protocol behavior and more efficient generation of test packets. Developing state representations tailored to different protocol characteristics, implementing real-time protocol state mapping, and applying state prediction and reasoning based on LLM can further improve the efficiency and applicability of NPF tools. In addition, introducing technologies such as parallelization, distributed computing, modular test architectures, and integrated network simulation with virtualization can significantly enhance testing scalability and adaptability. Through the integration of emerging technologies and interdisciplinary research, NPF is expected to play an increasingly critical role in network protocol security, providing robust technical support for building secure and reliable network environments.
Available online , doi: 10.11999/JEIT250262
Abstract:
Objective With the advancement of Industry 4.0, the increasing demand for mission-critical and latency-sensitive applications is driving the evolution of Industrial Internet of Things (IIoT) networks. Mobile Edge Computing (MEC) has emerged as a key solution to alleviate the computational constraints of User Equipment (UE), thus enhancing IIoT system performance. However, ensuring high reliability and security remains a critical challenge in multi-access MEC networks. To support Ultra-Reliable and Low-Latency Communication (URLLC), short packet transmission is employed, introducing Finite BlockLength (FBL) effects that impacts communication performance. Additionally, queuing delays at the servers present a significant bottleneck in meeting latency requirement. While existing studies predominantly focus on secure transmission under the Infinite BlockLength (IBL) assumption, comprehensive investigations into Physical Layer Security (PLS) and reliability in the FBL regime remain scarce. To address this gap, this paper aims to jointly optimize the security and reliability of MEC networks. Specifically, an analytical expression for end-to-end Leakage Failure Probability (LFP) is derived to assess the security and reliability performance. Furthermore, an efficient two-phase time length allocation algorithm is proposed to enhance overall system performance. Methods This study examines the uplink URLLC scenario in a multi-access MEC network. First, leveraging FBL theory, the communication phase within frame structure is modeled, and the decoding error probabilities of both the server and the eavesdropper are characterized. Subsequently, Extreme Value Theory (EVT) is employed to model the delay violation probability in the computation phase. Based on these formulations, the end-to-end LFP is derived to comprehensively assess the system’s PLS and reliability. Given the stringent end-to-end latency constraints in URLLC, a fundamental trade-off between security and reliability arises. To investigate this trade-off, an optimization problem is formulated to minimize LFP while satisfying the latency constraint, with the time length of the communication and computation phases as the optimization variables. However, due to the presence of multiplicative non-convex Q-functions in the objective function, solving this optimization problem poses significant challenges. To overcome this, a local point expansion technique is employed to approximate the non-convex terms as summations, facilitating problem reformulation. Additionally, auxiliary variables are introduced to enable convex relaxation of the Q-functions, transforming the problem into a convex optimization framework. The reformulated problem is then efficiently solved using the Successive Convex Approximation (SCA) algorithm. In response to the issue of performance degradation in algorithm convergence when the task scale increases, an Accelerated-SCA (A-SCA) algorithm is introduced. By leveraging the problem structure, a closed-form expression for the time allocation strategy corresponding to the system's optimal reliability is derived, which improves the initial point selection mechanism. Finally, simulation results validate the accuracy, convergence, and adaptability of the proposed algorithm, while also revealing the trade-off between security and reliability. Results and Discussions The proposed FBL coding-based time allocation scheme is evaluated through numerical simulations to validate its effectiveness. A comparative analysis with the IBL coding-based scheme is conducted, demonstrating the performance gains achieved through the joint optimization of communication and computation phases, while highlighting the limitations of IBL coding. Furthermore, the quality of the sub-optimal solution obtained via the SCA algorithm is assessed by benchmarking against the exhaustive search method. Additionally, both constrained and unconstrained resource scenarios are considered to explore the trade-offs between security and reliability, as well as between time resource and LFP. First, (Fig. 2 ) analyzes the convergence behavior of the proposed SCA-based time allocation scheme, demonstrating that the sub-optimal solution obtained closely approximates the global optimum. Furthermore, by optimizing the initial point selection with the A-SCA algorithm, the convergence speed and scalability are significantly enhanced. (Fig. 3 ) evaluates the variation of LFP with the eavesdropper’s channel gain under different task data sizes, revealing the fundamental trade-off between security and reliability, along with the associated performance compensation mechanism. (Fig. 4 ) illustrates the LFP trend as a function of the server’s channel gain, comparing the proposed scheme with IBL coding-based scheme. The results indicate that even in scenarios with low secure channel capacity, the proposed scheme achieves a 21.4% performance improvement, thereby validating its superiority in joint optimization across both phases. (Fig. 5 ) investigates the impact of task workload on LFP, while (Fig. 6 ) explores an unconstrained resource scenario, analyzing the influence of transmit power on LFP and the corresponding service time requirements. Conclusions This study explores the joint optimization of security and reliability in multi-access MEC networks supporting URLLC. In the FBL regime, the decoding error probability is modeled in the communication phase, while the delay violation probability is characterized using EVT in the computation phase. Based on these models, the LFP is derived as a key metric to quantify the system’s end-to-end PLS and reliability. Given the stringent latency constraints, a two-phase time length allocation optimization problem is formulated to minimize LFP, balancing security and reliability. To address the problem’s non-convexity, this paper first decouples the coupled variables through local linearization and reconstructs the problem. Next, convex upper and lower bounds of the complex Q-function are derived, enabling convex relaxation of the objective function. Subsequently, the SCA algorithm is applied iteratively to obtain a sub-optimal solution for the original problem. To tackle the issue of deteriorating convergence performance and increased complexity as the task scale grows, an A-SCA algorithm is proposed, which optimizes the initial point selection to address this challenge. Finally, simulation results validate the convergence, accuracy, and scalability of the proposed algorithm, demonstrating its performance advantages through comparison with existing approaches. Additionally, the impact of key system parameters on performance is systematically analyzed. The proposed LFP metric exhibits significant extensibility, being applicable to collaborative optimization of physical layer security and network layer security in URLLC systems, reliable task offloading in MEC, and throughput optimization in MIMO systems. Furthermore, the solution framework for LFP optimization problem, including problem decoupling and reconstruction, introduction of auxiliary variables for Q-function convex relaxation, iterative solving via SCA, and optimized initial point selection, provides valuable insights for solving multi-variable non-convex optimization problems in the FBL regime.
Available online , doi: 10.11999/JEIT250146
Abstract:
Objective With the rapid advancement of information technology, mobile communication is transitioning from the fifth generation (5G) to the sixth generation (6G), with a central goal of evolving from the Internet of Things to the Internet of Intelligence. Integrated Sensing and Communication (ISAC) has emerged as a key technology for next-generation wireless systems. By jointly designing sensing and communication functionalities, ISAC substantially improves spectral efficiency and overall system performance, and is regarded as a core technology for future intelligent networks. However, conventional fixed antenna arrays are limited by insufficient spatial degrees of freedom, making them inadequate for meeting the stringent sensing and communication requirements in dynamic and complex environments. To address this challenge, Movable Antenna (MA) is proposed as a novel architecture. MA systems enable antenna elements to move within designated transmit and receive regions, allowing real-time adjustment of their positions according to instantaneous channel states and system demands. This study proposes an MA-empowered ISAC framework that dynamically reconfigures antenna positions to exploit the spatial characteristics of wireless channels, with the objective of minimizing transmit power. The proposed design contributes new insights into energy-efficient ISAC system development and offers theoretical and practical relevance for future wireless communication networks. Methods This study formulates a joint optimization problem that considers the discrete positions of MA elements, beamforming vectors, and sensing signal covariance matrices. To address the inherent coupling among optimization variables and the presence of binary discrete variables, a Discrete Binary Particle Swarm Optimization (BPSO) framework is adopted. The algorithm iteratively determines the discrete antenna positions through a fitness-based search. Based on the obtained positions, Semi-Definite Relaxation (SDR) and Successive Convex Approximation (SCA) techniques are applied to manage non-convex constraints and solve for the beamforming vectors and sensing covariance matrices. This approach yields suboptimal yet effective solutions in complex non-convex optimization scenarios, thereby enhancing system performance. In terms of system modeling, a Dual-Function Radar and Communication Base Station (DFRC BS) equipped with MA is considered. The DFRC BS transmits downlink ISAC signals, communicates with multiple single-antenna downlink users, and senses a radar target. Antenna elements are restricted to a discrete set of candidate positions, facilitating practical system deployment. The radar sensing channel is modeled as a Line-of-Sight (LoS) channel, whereas the communication channels follow a field-response-based model. The DFRC BS transmits narrowband ISAC signals through beamforming, which are used concurrently for radar target detection and downlink communication. Results and Discussions Simulation results demonstrate that the proposed MA-empowered ISAC system achieves superior performance in transmission power optimization compared with conventional fixed antenna array systems. Under the constraint of sensing Signal-to-Interference-plus-Noise Ratio (SINR), transmit power increases with more stringent sensing requirements. However, the MA-empowered ISAC system substantially lowers the required transmit power, with a maximum observed reduction of 101.1 W. Under the communication SINR constraint and fixed sensing requirements, transmit power also rises as communication demands grow. In this setting, the MA-empowered ISAC system again shows a clear advantage, reducing transmit power by up to 134.6 W compared with traditional systems. Furthermore, as the number of downlink users increases—while maintaining consistent sensing and communication requirements—transmit power increases accordingly. Even under these conditions, the MA-empowered system continues to outperform its fixed-array counterpart. Beamforming pattern simulations further confirm that the BPSO-based optimization framework achieves multi-beam alignment and provides a degree of interference suppression, highlighting its effectiveness in managing dual-function transmission within MA-enabled ISAC systems. Overall, the introduction of MA significantly enhances ISAC system performance in terms of energy efficiency and spatial adaptability. Conclusions This paper proposes a joint optimization framework based on Discrete BPSO for MA-empowered ISAC systems, which effectively reduces transmit power while maintaining sensing and communication performance. The optimization process begins by iteratively solving a fitness function to determine the discrete positions of the MA elements. SDR and SCA techniques are employed during this process to address non-convex constraints. Once the MA element positions are established, the associated beamforming vectors and sensing signal covariance matrices are computed or further optimized. By dynamically adjusting antenna positions, the system gains additional spatial degrees of freedom, enabling more efficient utilization of the spatial characteristics of wireless channels. This work provides a new approach for energy-efficient design in ISAC systems and offers meaningful guidance for the development of next-generation wireless networks. Future research will continue to explore advanced optimization algorithms for MA positioning and system performance enhancement, aiming to meet sensing and communication requirements in highly dynamic environments. Additionally, the applicability of MA in other wireless scenarios—such as vehicular networks and aerial communication platforms—will be studied to facilitate broader adoption of MA-based technologies.
Available online , doi: 10.11999/JEIT250053
Abstract:
Objective Logic testing using Automatic Test Equipment (ATE) is a critical step in integrated circuit (IC) manufacturing test to ensure chip quality. Enhancing logic test efficiency is essential to reducing digital IC testing costs. During testing, IC test data are typically stored in the main memory of the ATE user board and sequentially read to generate channel test waveforms. The time required to read test data directly affects test efficiency. Traditional Test Data Compression (TDC) approaches, which often require preprocessing such as X-bit filling, are suited only for scan testing and thus do not meet broader test engineering needs. Meanwhile, advances in Field-Programmable Gate Array (FPGA) technology have enabled the customization of high-speed Block RAM (BRAM) resources. This study proposes a test vector coding scheme based on component statistics, in which the Device Under Test (DUT) test vectors are encoded and corresponding component coding tables are generated and stored in the FPGA BRAM. A table lookup circuit is implemented to achieve synchronous, parallel output of all test vector components, effectively reducing the external data read time and improving logic test efficiency. Methods Each bit symbol in an IC test vector comprises four components: drive (DC), measurement (MC), high impedance (ZC), and residual value (RV). The proposed scheme performs statistical encoding of each component across all bit symbols in the DUT’s test vectors and generates shared DC, MC, and ZC coding tables. The encoding process includes: (1) scanning and extracting each vector from the DUT test project files; (2) determining the bit component values and residual values for all channels; (3) for each component, compiling and deduplicating all generated codes, reassigning deleted code references to reserved codes to form the final coding tables; and (4) determining the combined component addresses and residual values. Using a Xilinx Kintex-7 FPGA development board and the Vivado tool, three BRAM modules are configured, and a BRAM table lookup control circuit is designed (Fig. 4 ). Prior to testing, the component coding tables are downloaded to the FPGA BRAM, and the combined address and residual values of the three component codes for each test vector are stored in off-chip SDRAM. During operation, the lookup circuit uses the combined address to synchronously and in parallel output the three components, which—together with the residual value—drive the waveform generator to produce the channel test waveform. Results and Discussions The functionality of the BRAM-segmented synchronous table lookup circuit is verified through simulation. Three BRAM modules with 64-bit width and customized segment address depth are configured. The COE files of the component encoding tables are downloaded to the target BRAMs via a UART interface, using address generation control logic. The corresponding addresses are then applied to the lookup circuit. A complete simulation is conducted by integrating the segmented lookup module, data strobe module, address allocation module, and data transmission module, enabling validation of the BRAM data download, segmented table lookup, and I/O processes within the FPGA (Fig. 6 –Fig. 8 ). Results confirm that the synchronized parallel output from the lookup circuit matches the three component codes of the predefined test vectors (Fig. 9 –Fig. 13 ). The SDRAM read time is also analyzed. Under the same configuration parameters, the proposed encoding scheme reduces the read time of each test vector by 66.7% compared with a direct encoding storage scheme (Table 3 ), indicating a significant improvement in logic test efficiency. A qualitative comparison with traditional TDC schemes—including dictionary coding, Frequency-Directed Run-length (FDR) coding and run-length coding—is presented in Table 4 . The results indicate that the proposed scheme, which utilizes high-speed BRAM embedded in modern FPGAs, supports non-scan parallel logic testing with high decoding speed and low overhead, while fully satisfying the original test project requirements. Conclusions A test vector encoding and decoding scheme based on component statistics and BRAM-segmented synchronous table lookup is proposed and implemented. The segmented lookup circuit is designed, and its functional correctness is verified through simulation. Compared with direct encoding, the proposed scheme achieves a 66.7% reduction in logic test time. In contrast to traditional TDC approaches, it offers lower hardware overhead by leveraging embedded high-speed BRAM. The scheme supports ATE-based parallel non-scan logic testing and meets the original engineering design goals, providing a practical foundation for optimizing the logic test function module of the ATE user board.
Available online , doi: 10.11999/JEIT250377
Abstract:
Significance Three-Dimensional Integrated Circuits (3D ICs) have emerged as a key research direction in the post-Moore era due to their advantages in low latency and high integration density. As electronic devices demand higher performance and smaller form factors, 3D ICs offer a compelling solution by vertically stacking multiple chip layers to achieve enhanced integration. A core enabler of 3D IC technology is Through-Silicon Via (TSV) technology, which facilitates high-density vertical interconnects across layers. TSVs have contributed significantly to performance improvements in 3D ICs but also pose challenges in thermal management, power integrity, and signal integrity, all of which can affect device reliability and operational stability. Addressing these challenges is essential for the continued advancement of 3D IC systems. This review outlines recent research on TSV technology, with an emphasis on thermal, electrical, and signal integrity issues, as well as current strategies for mitigating these limitations. Progress This review systematically summarizes the progress in TSV technology, focusing on the following areas: Thermal Management: Thermal dissipation is a critical concern in 3D ICs due to elevated power densities resulting from multilayer stacking. While TSVs improve interconnect performance, they can also introduce vertical heat flow paths that lead to localized overheating and reduced reliability. To manage this, various thermal modeling approaches—such as Finite Element Analysis (FEA) and thermal stacking simulations—have been developed to predict temperature distributions and optimize thermal performance. These models inform the layout of TSVs and guide the incorporation of Thermal TSVs (TTSVs) to enhance heat dissipation. Researchers have also explored the use of high-thermal-conductivity materials, such as carbon nanotubes and graphene, to improve thermal pathways. Optimizing TSV density and employing multi-layer thermal redistribution techniques have further advanced thermal management, contributing to better device performance and longer operational lifetimes. Power Integrity: Power integrity is a major design constraint in 3D ICs, given the complex power delivery networks required in stacked architectures. TSVs, acting as vertical power conduits, can introduce issues such as voltage drops, electromigration, and power noise. Several approaches have been proposed to address these issues. Layout optimization—particularly through uniform TSV distribution and the integration of Backside Power Delivery Networks (BPDNs)—helps reduce power delivery path lengths and mitigate voltage loss. Dynamic Voltage And Frequency Scaling (DVFS) is also employed to adapt power usage under varying workloads, particularly in high-performance computing environments. Additional methods include the use of decoupling capacitors (DECAPs) and Fully Integrated Voltage Regulators (FIVRs), which help suppress power noise and maintain stability across multiple voltage domains. Signal Integrity: TSV-based interconnects must maintain signal integrity at increasingly high frequencies, but parasitic inductance and capacitance inherent to TSVs can degrade signal quality through reflection, crosstalk, and delay mismatch. These effects become especially pronounced in high-density, high-speed interconnect architectures. To address this, electromagnetic shielding—using grounded TSVs and metallic isolation structures—has been shown to reduce crosstalk and enhance signal fidelity. The use of low-dielectric constant (low-k) materials further minimizes parasitic capacitance and improves signal propagation speed. Differential TSV designs and advanced interconnect architectures have also been proposed to reduce interference and enhance signal integrity. These improvements are essential for achieving reliable high-speed data transmission in storage and processing applications. Conclusions While TSV technology has advanced substantially in addressing the thermal, power, and signal integrity challenges of 3D ICs, several limitations persist. These include scalability constraints, power delivery reliability under high-density integration, and diminished signal transmission quality at high frequencies. These challenges highlight the need for continued innovation in TSV design and integration to meet the demands of next-generation 3D IC systems. Several promising research directions are emerging. First, there is a growing need for higher-precision multiphysics coupling models. As 3D ICs progress toward large-scale heterogeneous integration, high-speed data communication, and extreme energy efficiency, more accurate modeling of the thermal, electrical, and signal interactions associated with TSVs is required. This calls for enhanced integration of multiphysics simulations into the Electronic Design Automation (EDA) workflow to enable co-simulation across electrical, thermal, and signal domains. Second, co-optimization of BPDNs and nano-TSVs (nTSVs) is becoming increasingly important. As chip dimensions decrease and stacking complexity grows, traditional front-side power delivery approaches no longer meet the required power densities. Improved BPDN strategies, in conjunction with nTSV integration, will support higher stacking capability and improved energy efficiency. Third, the exploration of new materials and TSV array structures offers additional opportunities. Carbon-based nanomaterials, used as TSV fillers or liners, can alleviate thermal expansion mismatch and improve resistance to electromigration. Incorporating air gaps or low-k dielectrics as insulating liners can reduce parasitic capacitance and enhance high-speed signal performance. Meanwhile, novel TSV array architectures can increase interconnect density and improve redundancy and fault tolerance. Finally, the adoption of AI-driven TSV optimization holds considerable promise. TSV layout design currently depends heavily on manual heuristics. The application of artificial intelligence to automate TSV placement and power network distribution can significantly reduce design time and accelerate the transition toward more intelligent 3D integration design paradigms.
Available online , doi: 10.11999/JEIT250251
Abstract:
Objective With the advancement of Urban Air Mobility (UAM), the rapid growth in aircraft numbers under such scenarios requires improved time slot allocation algorithms for the Universal Access Transceiver 2 (UAT2) data link to enhance surveillance capacity. This study analyzes the original time slot allocation algorithm for UAT2, identifying limitations related to downlink message time slot management. An improved allocation algorithm based on a state bitmap with a random drift mechanism is proposed considering message characteristics. Additionally, three transmission schemes to expand the number of time slots are proposed, and a surveillance capacity calculation model is established. The performance of each transmission scheme under different slot allocation strategies is simulated and evaluated. The research addresses the challenge of insufficient surveillance capacity in UAT2 data link under high-density UAM scenarios and provides an optimized approach for time slot allocation and surveillance performance improvement. Methods The study begins with an analysis of the original UAT2 time slot allocation algorithm, which is limited in high-density aircraft environments due to its pseudo-random mechanism based on geographic coordinates. The proposed algorithm introduces a state bitmap, implemented as a bit vector table where each bit indicates whether the corresponding time slot is occupied. When an aircraft selects a time slot, it first generates a pseudo-random number using the algorithm specified in DO-282C MOPS. The state bitmap is then checked: if the corresponding bit is 0, the time slot is selected; if 1, a piecewise random drift mechanism adjusts the slot selection, as shown in Formula (17). The drift mechanism segments the time slots to distribute selections more evenly and reduce collision probability. The algorithm also applies a slot retention period T, allowing an aircraft to occupy the same time slot for T consecutive UAT frames before reselecting, as defined by Formulas (19)–(21). To further expand time slot availability, three transmission schemes are proposed: Multi-ary Continuous Phase Frequency Shift Keying (MCPFSK) with modulation orders M = 4 and 8, constant modulation index with increased symbol rate, and constant carrier frequency difference with reduced modulation index. The available number of time slots for each scheme is calculated using Formula (26). A surveillance capacity model incorporating bit error rate and collision probability is established, as expressed by Formulas (27)–(30). Results and Discussions Simulation results demonstrate that the improved algorithm substantially outperforms both the original algorithm and the fixed time-window dynamic slot allocation algorithm. Under the original transmission scheme, the improved algorithm reduces slot collision probability by 16.78% and increases slot utilization by 16.12% compared to the original algorithm (Fig. 6 , Fig. 7 ). Relative to the algorithm described in [Ref. 19], the collision probability decreases by 10.80%, and slot utilization increases by 10.48%. For the expanded time slot schemes, when maximum surveillance capacity is reached, the improved algorithm reduces collision probability by 16.14% and increases slot utilization by 16.13% relative to the original algorithm (Table 3 ). Among these schemes, the 8CPFSK expansion achieves the highest surveillance capacity of 3913 , with a slot utilization rate of 79.37% (Fig. 13 ). Real-time performance testing indicates that even in high-density scenarios, the improved algorithm maintains scheduling times within 120 ms, meeting the real-time operational requirements of UAT2 (Fig. 11 ). Bit Error Rate (BER) simulations reveal that the MCPFSK scheme provides superior anti-interference performance, whereas the constant carrier frequency difference scheme exhibits the highest BER (Fig. 12 ). Conclusions A slot allocation algorithm for the UAT2 data link based on state bitmaps and a random drift mechanism is proposed in this study. Compared to the original algorithm, the proposed method reduces slot collision probability by 16.78% and improves slot utilization by 16.12% under the original transmission scheme. When compared to the fixed time-window dynamic slot allocation algorithm described in [Ref. 19], collision probability decreases by 10.80%, and slot utilization increases by 10.48%. Three transmission schemes designed to expand slot availability are also proposed. Simulation results show that as the number of available slots increases, the performance advantage of the improved algorithm becomes more pronounced. Across all transmission schemes, when maximum surveillance capacity is reached, the improved algorithm reduces slot collision probability by approximately 16% and increases slot utilization by approximately 17%. In addition, a surveillance capacity calculation model for the UAT2 data link is established. Quantitative simulation results based on slot collision probability and BER performance confirm that the effective surveillance capacity of the improved algorithm is significantly higher than that of both the original algorithm and the fixed time-window dynamic slot allocation algorithm. It is also demonstrated that the proposed algorithm achieves optimal surveillance performance when all aircraft are equipped with both transmission and reception capabilities. Future research will focus on optimizing slot allocation algorithms for scenarios where aircraft possess only transmission capability.
Available online , doi: 10.11999/JEIT250151
Abstract:
Objective The rapid advancement of information technology has driven significant transformation in the medical domain. As a cornerstone of medical informatization, Electronic Health Records (EHRs) play a critical role in improving healthcare service efficiency and supporting medical research. Effective use of patient EHRs can enhance diagnostic and treatment processes and offer reliable data support for disease prevention and novel drug discovery. However, conventional EHR systems face several challenges, including data silos, secure sharing complexity, and heightened privacy risks. Data silos hinder the seamless exchange and integration of EHRs across institutions, limiting the potential for collaborative medical practices. A central challenge in secure data sharing lies in ensuring data interoperability without compromising patient privacy—a problem of urgent concern in modern healthcare systems. Moreover, privacy breaches not only jeopardize patient welfare but also damage the credibility and trustworthiness of healthcare institutions. To address these issues, this paper proposes a distributed multi-keyword fuzzy sorting search scheme based on a Keywords Balanced Binary (KBB) index tree. The scheme leverages the decentralized, tamper-proof, and traceable features of blockchain technology to create a secure and efficient framework for EHR sharing. By eliminating data silos, the blockchain facilitates cross-institutional interoperability, while smart contracts maintain strict privacy protections throughout the data sharing process. Methods The scheme first applies a K-means clustering algorithm to categorize EHRs, followed by hierarchical encrypted storage via the Interplanetary File System (IPFS). This dual-layer approach ensures distributed data management while protecting user privacy and enhancing storage robustness and fault tolerance. To improve search performance, the Porter stemming algorithm standardizes query keywords, reducing ambiguity from semantic variations and enabling consistent semantic matching. A KBB index tree is then constructed over the clustered EHRs to support fuzzy keyword matching and high retrieval precision. This structure incorporates adaptive sorting to reduce search latency. Access control is enforced using smart contracts, which implement fine-grained, role-based authentication to ensure that only authorized users can retrieve EHRs, thereby minimizing the risk of data leaks. During query processing, ranked searches are conducted within the KBB index tree. Once matching encrypted EHRs are located, data retrieval is performed via IPFS. Blockchain-based hashing ensures the integrity and immutability of the retrieved data, protecting it from tampering or corruption. Finally, users decrypt the data with private keys to access the original EHR content, completing the secure retrieval process. Results and Discussions Simulation experiments demonstrate that the proposed scheme offers superior implementation efficiency compared to related methods in terms of both time and storage overhead. The index tree construction time is shorter than that reported in[Ref. 7] and[Ref. 8], with an efficiency improvement of 80%–85% (Fig. 3 ). Although the trap generation time is longer than in[Ref. 7] and[Ref. 15] (Fig. 4 ), this increase stems from the scheme’s support for multiuser search, whereas[Ref. 7] only supports single-user search. The combined search time for indexing and trap generation is lower than in[Ref. 7],[Ref. 8], and[Ref. 15], with search efficiency improved by 50.5% and 75.8%, respectively (Fig. 5 ). The ciphertext generation and decryption times are also markedly better than those in the comparative literature, with improvements of 33.3% and 60%, respectively (Fig. 6 , Fig. 7 ). Furthermore, the storage costs for keys and ciphertext in this scheme are lower than those of the other methods (Fig. 8 , Fig. 9 ). Conclusions The proposed scheme substantially improves multi-keyword search efficiency, enabling users to rapidly locate target information within large-scale EHR datasets while enhancing the accuracy of search results. The fuzzy search functionality allows users to retrieve data even when the exact form of the keywords is unknown, increasing the flexibility and applicability of the search process. The encryption algorithm has been rigorously tested in experimental analyses, demonstrating that it maintains semantic security under the known ciphertext model, thereby ensuring EHR confidentiality. In addition, the algorithm performs well in terms of implementation efficiency, meeting the practical needs of EHR applications in medical contexts while maintaining strong security guarantees. By combining high-precision multi-keyword indexing with robust privacy protection, this scheme offers a scalable and secure framework for EHR sharing that meets the interoperability and confidentiality requirements of modern healthcare systems.
Available online , doi: 10.11999/JEIT250437
Abstract:
Objective The State of Charge (SOC) is a critical indicator for evaluating the remaining capacity and health status of lithium-ion batteries, which are widely deployed in electric vehicles, portable electronics, and energy storage systems. Accurate SOC estimation is essential for maintaining safe operation, extending battery life, and optimizing energy utilization. However, practical SOC estimation is complicated by measurement uncertainties and disturbances, particularly Unknown But Bounded (UBB) noise arising from sensor errors, environmental fluctuations, and battery aging. Conventional filtering algorithms, such as Kalman filters, often depend on probabilistic noise assumptions and tend to perform poorly when actual noise characteristics deviate from Gaussian distributions. This study addresses these limitations by proposing a Particle-Swarm-Confinement-based Zonotopic Space Filtering (PSC-ZSF) algorithm to enhance estimation robustness and reduce conservatism, with specific emphasis on high-dimensional dynamic systems such as lithium-ion battery SOC estimation. Methods The PSC-ZSF algorithm combines the robustness of set-membership filtering with the global optimization capabilities of Particle Swarm Optimization (PSO), integrating geometric uncertainty representation with heuristic search strategies. A zonotopic feasible state set is first constructed by propagating system model predictions and refining them with measurement updates, thereby representing the bounded uncertainty in system states. A swarm of particles is then randomly initialized within this zonotopic space to explore potential state estimates. Particle movement follows PSO-based velocity and position updates, leveraging both individual experience and swarm intelligence to identify optimal state estimates. Fitness functions quantify the consistency between candidate states and observed measurements, guiding particle convergence toward more plausible regions. To maintain algorithm stability, a boundary detection mechanism identifies particles that exceed the zonotopic feasible region. Out-of-bound particles are projected back into the feasible set by solving a quadratic programming problem that minimizes positional distortion while preserving spatial characteristics. Additionally, a dynamic contraction strategy adaptively tightens the zonotopic boundaries by scaling the normal vectors of the defining hyperplanes, effectively shrinking the search space as the particle swarm converges. This contraction improves estimation precision and reduces conservatism without incurring excessive computational overhead. The approach utilizes Minkowski sum properties intrinsic to zonotopes and utilizes efficient geometric computations to balance accuracy and efficiency. For experimental validation, the PSC-ZSF algorithm is applied to SOC estimation of lithium-ion batteries modeled by a discrete-time equivalent circuit that incorporates polarization resistance and capacitance effects. Real-world data are collected from a 18650 lithium-ion battery undergoing constant current discharge at room temperature. The system model considers UBB process and measurement noise, with parameters calibrated through empirical measurements. The performance of the proposed method is benchmarked against Ellipsoidal Set-Membership Filtering (ESMF) and Zonotopic Set-Membership Filtering (ZSMF) methods by comparing feasible state set volumes and the tightness of estimated boundaries. Results and Discussions The proposed PSC-ZSF algorithm demonstrates reliable confinement of particle swarms within the zonotopic feasible region throughout iterative optimization, effectively preventing particle divergence and improving estimation stability and reliability (Fig. 1 ). Comparative analysis indicates that PSC-ZSF consistently achieves significantly smaller feasible state set volumes at each time step compared to ESMF and ZSMF methods, reflecting reduced estimation redundancy and improved compactness (Fig. 3 ). The ESMF method guarantees that the true state remains enclosed; however, it produces overly conservative ellipsoidal bounds, especially under conditions of rapid system dynamics, which compromises estimation informativeness and responsiveness. The ZSMF method improves upon this by employing zonotopic bounds but still yields relatively broad estimation regions due to fixed zonotope geometries and cautious boundary updates. In contrast, PSC-ZSF adaptively refines the zonotopic boundaries based on real-time particle swarm distributions, leading to consistently tighter, more accurate boundaries that closely track the true SOC and polarization voltage trajectories (Figs. 4 and 5 ). This adaptive boundary contraction strategy enhances estimation precision while preserving robustness. Moreover, computational complexity analysis shows that although particle projection and boundary scaling introduce additional per-iteration operations, the accelerated convergence of PSC-ZSF reduces overall iteration requirements. This trade-off ensures computational feasibility for real-time SOC estimation in battery management systems. Conclusions This study proposes a Particle-Swarm-Confinement-Based Zonotopic Space Filtering (PSC-ZSF) algorithm that integrates set-membership filtering with PSO to address state estimation under unknown but bounded noise. The PSC-ZSF algorithm ensures that particle swarms remain confined within a zonotopic feasible region through optimal projection and dynamically contracts the zonotope boundaries via hyperplane scaling. This approach improves estimation accuracy and reduces conservatism. Application to lithium-ion battery SOC estimation confirms the approach’s superiority over conventional approaches, providing more precise and stable state boundaries while maintaining computational efficiency suitable for real-time applications. Future work will focus on extending the PSC-ZSF algorithm to complex dynamic systems such as autonomous vehicle navigation and smart grid state estimation to further assess scalability and practical applicability.
Available online , doi: 10.11999/JEIT250407
Abstract:
The Mixture-of-Experts (MoE) framework has become a pivotal approach for enhancing the knowledge capacity and inference efficiency of Large Language Models (LLMs). Conventional methods for scaling dense LLMs have reached significant limitations in training and inference due to computational and memory constraints. MoE addresses these challenges by distributing knowledge representation across specialized expert sub-networks, enabling parameter expansion while maintaining efficiency through sparse expert activation during inference. However, the dynamic nature of expert activation introduces substantial challenges in resource management and scheduling, necessitating targeted optimization at both the system and architectural levels. This survey focuses on the deployment of MoE-based LLMs. It first reviews the definitions and developmental trajectory of MoE, followed by an in-depth analysis of current system-level optimization strategies and architectural innovations tailored to MoE. The paper concludes by summarizing key findings and proposing prospective optimization techniques for MoE-based LLMs. Significance The MoE mechanism offers a promising solution to the computational and memory limitations of dense LLMs. By distributing knowledge representation across specialized expert sub-networks, MoE facilitates model scaling without incurring prohibitive computational costs. This architecture alleviates the bottlenecks associated with training and inference in traditional dense models, marking a notable advance in LLM research. Nonetheless, the dynamic expert activation patterns inherent to MoE introduce new challenges in resource scheduling and management. Overcoming these challenges requires targeted system- and architecture-level optimizations to fully harness the potential of MoE-based LLMs. Progress Recent advancements in MoE-based LLMs have led to the development of various optimization strategies. At the system level, approaches such as automatic parallelism, communication–computation pipelining, and communication operator fusion have been adopted to reduce communication overhead. Memory management has been improved through expert prefetching, caching mechanisms, and queue scheduling policies. To address computational load imbalance, both offline scheduling methods and runtime expert allocation strategies have been proposed, including designs that leverage heterogeneous CPU–GPU architectures. In terms of hardware architecture, innovations include dynamic adaptation to expert activation patterns, techniques to overcome bandwidth limitations, and near-memory computing schemes that improve deployment efficiency. In parallel, the open-source community has developed supporting tools and frameworks that facilitate the practical deployment and optimization of MoE-based models. Conclusions This survey presents a comprehensive review of system and architectural optimization techniques for MoE-based LLMs. It highlights the importance of reconciling parameter scalability with computational efficiency through the MoE framework. The dynamic nature of expert activation poses significant challenges in scheduling and resource management, which this survey systematically addresses. By evaluating current optimization techniques across both system and hardware layers, the paper offers key insights into the state of the field. It also proposes directions for future work, providing a reference for researchers and practitioners seeking to improve the performance and scalability of MoE-based models. The findings emphasize the need for continued innovation across algorithm development, system engineering, and architectural design to fully realize the potential of MoE in real-world applications. Prospects Future research on MoE-based LLMs is expected to advance the integration of algorithm design, system optimization, and hardware co-design. Key research directions include resolving load imbalance and maximizing resource utilization through adaptive expert scheduling algorithms, refining system frameworks to support dynamic sparse computation more effectively, and exploring hardware paradigms such as near-memory computing and hierarchical memory architectures. These developments aim to deliver more efficient and scalable MoE model deployments by fostering deeper synergy between software and hardware components.
Available online , doi: 10.11999/JEIT250306
Abstract:
Objective With the rapid development of sixth-generation mobile communication, Extra-Large Reconfigurable Intelligent Surfaces (XL-RIS) have attracted significant attention due to their potential to enhance spectral efficiency, expand coverage, and reduce energy consumption. However, conventional channel estimation methods, primarily based on Far-Field (FF) or near-field (NF) models, face limitations in addressing the hybrid far-NF environment that arises from the coexistence of NF spherical waves and FF planar waves in XL-RIS deployments. These limitations restrict the intelligent control capability of RIS technology due to inaccurate channel modeling and reduced estimation accuracy. To address these challenges, this paper constructs a hybrid-field channel model for XL-RIS and proposes a robust channel estimation method to resolve parameter estimation challenges under coupled FF and NF characteristics, thereby improving channel estimation accuracy in complex propagation scenarios. Methods For channel estimation in XL-RIS-aided communication systems, several key challenges must be addressed, including the modeling of hybrid far-NF cascaded channels, separation of FF and NF channel components, and individual parameter estimation. To capture the hybrid-field effects of XL-RIS, a hybrid-field cascaded channel model is constructed. The RIS-to-User Equipment (UE) channel is modeled as a hybrid far-NF channel, whereas the Base Station (BS)-to-RIS channel is characterized under the FF assumption. A unified representation of FF and NF models is established by introducing equivalent cascaded angles for the angle of departure and angle of arrival on the RIS side. The XL-RIS hybrid-field cascaded channel is parameterized through BS arrival angles, RIS-UE cascaded angles, and distances. To reduce the computational complexity of joint parameter estimation, a Two-Stage Hybrid-Field (TS-HF) channel estimation scheme is proposed. In the first stage, the BS arrival angle is estimated using the MUltiple SIgnal Classification (MUSIC) algorithm. In the second stage, a Hybrid-Field forward spatial smoothing Rank-reduced MUSIC (HF-RM) algorithm is proposed to estimate the parameters of the RIS-UE hybrid-field channel. The received signals are pre-processed using a forward spatial smoothing technique to mitigate multipath coherence effects. Subsequently, the Rank-reduced MUSIC (RM) algorithm is applied to separately estimate the FF and NF angle parameters, as well as the NF distance parameter. During this stage, a power spectrum comparison scheme is designed to distinguish FF and NF angles based on power spectral characteristics, thereby providing high-precision angular information to support NF distance estimation. Finally, channel attenuation is estimated using the least squares method. To validate the effectiveness of the proposed hybrid-field channel estimation scheme, comparative analyses are conducted against FF, NF, and the proposed TS-HF-RM schemes. The FF estimation approximates the hybrid-field channel using a FF channel model and estimates FF angle parameters with the MUSIC algorithm, referred to as the TS-FF-M scheme. The NF estimation applies a NF channel model to characterize the hybrid channel and estimates angle and distance parameters using the RM algorithm, referred to as the TS-NF-RM scheme. To further evaluate the estimation performance, additional benchmark schemes are considered, including the Two-Stage Near-Field Orthogonal Matching Pursuit (TS-NOMP) scheme, the Two-Stage Hybrid Orthogonal Matching Pursuit with Prior (TS-HOMP-P) scheme that requires prior knowledge of FF and NF quantities, and the Two-Stage Hybrid Orthogonal Matching Pursuit with No Prior (TS-HOMP-NP) scheme that operates without requiring such prior information. Results and Discussions Compared with the TS-FF-M and TS-NF-RM schemes, the proposed TS-HF-RM approach achieves effective separation and accurate estimation of both FF and NF components by jointly modeling the hybrid-field channel. The method consistently demonstrates superior estimation accuracy across a wide range of Signal-to-Noise Ratio (SNR) conditions (Fig. 4 ). These results confirm both the necessity of hybrid-field channel modeling and the effectiveness of the proposed estimation scheme. Experimental findings show that the TS-HF-RM approach significantly improves channel estimation performance in XL-RIS-assisted communication systems. Further comparative analysis reveals that the TS-HF-RM scheme outperforms TS-NOMP and TS-HOMP-P by mitigating power leakage effects and overcoming limitations associated with unknown path numbers through distinct processing of FF and NF components. Without requiring prior knowledge of the propagation environment, the proposed method achieves lower Normalized Mean Square Error (NMSE) while demonstrating improved robustness and estimation precision (Fig. 5 ). Although TS-HOMP-NP also operates without prior field information, the TS-HF-RM scheme provides superior parameter resolution, attributed to its subspace decomposition principle. Additionally, both the TS-HF-RM and TS-HOMP-P schemes exhibit improved performance as the number of pilot signals increases. However, TS-HF-RM consistently outperforms TS-HOMP-P under low-SNR conditions (0 dB). At high SNR (10 dB) with a limited number of pilot signals (<280), TS-HOMP-P temporarily achieves better performance due to its higher sensitivity to SNR. Nevertheless, the proposed TS-HF-RM approach demonstrates greater stability and adaptability under low-SNR and resource-constrained conditions (Fig. 6 ). Conclusions This study addresses the challenge of hybrid-field channel estimation for XL-RIS by constructing a hybrid-field cascaded channel model and proposing a two-stage estimation scheme. The HF-RM algorithm is specifically designed for accurate hybrid component estimation in the second stage. Theoretical analysis and simulation results demonstrate the following: (1) The hybrid-field model reduces inaccuracies associated with traditional single-field assumptions, providing a theoretical foundation for reliable parameter estimation in complex propagation environments; (2) The proposed TS-HF-RM algorithm enables high-resolution parameter estimation with effective separation of FF and NF components, achieving lower NMSE compared to hybrid-field OMP-based methods.
Available online , doi: 10.11999/JEIT250340
Abstract:
Objective Ensuring the safety and stability of train operations is essential in the advancement of railway intelligence. The growing maturity of Wireless Sensor Network (WSN) technology offers an efficient, reliable, low-cost, and easily deployable approach to monitoring railway operating conditions. However, in complex and dynamic maintenance environments, WSNs encounter several challenges, including weak signal coverage at monitoring sites, limited accessibility for tasks such as sensor node battery replacement, and the generation of large volumes of monitoring data. To address these issues, this study proposes a multi-Unmanned Aerial Vehicle (UAV)-assisted method for data collection and computation offloading in railway WSNs. This approach enhances overall system energy efficiency and data freshness, offering a more effective and robust solution for railway safety monitoring. Methods An intelligent data collection and computation offloading system is constructed for multi-UAV-assisted railway WSNs. UAV flight constraints within railway safety protection zones are considered, and wireless sensing services are prioritized to ensure preferential transmission for safety-critical tasks. To balance energy consumption and data freshness, the system optimization objective is defined as the weighted sum of UAV energy consumption, WSN energy consumption, and the Age of Information (AoI). A joint optimization algorithm based on Multi-Agent Soft Actor-Critic (MASAC) is proposed, which balances exploration and exploitation through entropy regularization and adaptive temperature parameters. This approach enables efficient joint optimization of UAV trajectories and computation offloading strategies. Results and Discussions (1) Compared with the Multi-Agent Deep Deterministic Policy Gradient (MADDPG), MASAC-Greedy, and MASAC-AOU algorithms, the MASAC-based scheme converges more rapidly and demonstrates greater stability (Fig. 4 ), ultimately achieving the highest reward. In contrast, MADDPG exhibits slower learning and less stable performance. (2) The comparison of multi-UAV flight trajectories under different algorithms shows that the proposed MASAC algorithm enables effective collaboration among UAVs, with each responsible for monitoring distinct regions while strictly adhering to railway safety protection zone constraints (Fig. 5 ). (3) The MASAC algorithm yields the best objective function value across all evaluated algorithms (Fig. 6 ). (4) As the number of sensors and the AoI weight increase, UAV energy consumption rises for all algorithms; however, the MASAC algorithm consistently maintains the lowest energy consumption (Fig. 7 ). (5) In terms of sensor node energy consumption, MADDPG achieves the lowest value, but at the expense of information freshness (Fig. 8 ). (6) Regarding average AoI performance, the MASAC algorithm performs best across a range of sensor densities and AoI weight settings, with the greatest improvements observed under higher AoI weight conditions (Fig. 9 ). (7) The AoI performance comparison by sensor type (Table 2 ) confirms that the system effectively supports priority-based data collection services. Conclusions This study proposes a MASAC-based intelligent data collection and computation offloading scheme for railway WSNs supported by multiple UAVs, addressing critical challenges such as limited WSN battery life and the high real-time computational demands of complex railway environments. The proposed algorithm jointly optimizes UAV flight trajectories and computation offloading strategies by integrating considerations of UAV and WSN energy consumption, data freshness, sensing service priorities, and railway safety protection zone constraints. The optimization objective is to minimize the weighted sum of average UAV energy consumption, average WSN energy consumption, and average WSN AoI. Simulation results demonstrate that the proposed scheme outperforms baseline algorithms across multiple performance metrics. Specifically, it achieves faster convergence, efficient multi-UAV collaboration that avoids resource redundancy and spatial overlap, and superior results in UAV energy consumption, sensor node energy consumption, and average AoI.
Available online , doi: 10.11999/JEIT250394
Abstract:
Objective Sequences with favorable correlation properties are widely applied in radar and communication systems. Sequence sets with zero or low correlation characteristics enhance radar resolution, target detection, imaging quality, and information acquisition, while also improving the omnidirectional transmission capability of massive multiple-input multiple-output (MIMO) systems. Designing aperiodic Zero Correlation Zone (ZCZ) sequence sets with excellent correlation performance is therefore critical for both wireless communication and radar applications. For example, aperiodic Z-Complementary Set (ZCS) sequence sets are often used in omnidirectional precoding for MIMO systems, whereas aperiodic ZCZ sequence sets are employed in integrated MIMO radar-communication systems. These ZCZ sequence sets are thus valuable across a range of system applications. However, most prior studies rely on analytical construction methods, which impose constraints on parameters such as sequence length and the number of sequences, thereby limiting design flexibility and practical applicability. This study proposes a numerical optimization approach for designing ZCS and aperiodic ZCZ sequence sets with improved correlation properties and greater parametric flexibility. The method minimizes the Complementary Peak Sidelobe Level (CPSL) and Weighted Peak Sidelobe Level (WPSL) using Newton’s method to achieve superior sequence performance. Methods This study proposes an optimization-based design method using Newton’s method to construct both aperiodic ZCS sequence sets and aperiodic ZCZ sequence sets with low sidelobe levels and flexible parameters. The optimization objective is first formulated using the CPSL and WPSL. The problem is then reformulated as an equivalent system of nonlinear equations, which is solved using Newton’s method. To reduce computation time, partial derivatives are approximated using numerical differentiation techniques. A loop iteration strategy is employed to address multiple constraints during the optimization process. To ensure algorithmic convergence, Armijo’s rule is used for step size selection, promoting stable descent of the objective function along the defined search direction. Results and Discussions The aperiodic ZCS sequence set is constructed using Newton’s method. As the number of sequences increases, the CPSL progressively decreases, falling below –300 dB when \begin{document}$M \geqslant 2$\end{document} Fig. 1 ). The performance of ZCS sequences generated by both methods is evaluated under different ZCZ conditions. While both approaches achieve low CPSL, Newton’s method yields aidelobe levels closer to the ideal value (Fig. 2 ). Convergence behavior is assessed using CPSL and the number of iterations. The improved ITROX algorithm typically requires around 20000 iterations to converge, with increasing iterations as ZCZ size grows. In contrast, Newton’s method achieves rapid convergence within approximately 10 iterations (Figs. 3 and 4 ). The aperiodic ZCZ sequence set constructed using Newton’s method exhibits autocorrelation and cross-correlation peak sidelobe levels below –300 dB within the ZCZ. Moreover, Newton’s method achieves the lowest WPSL, offering the best overall performance among all tested methods (Fig. 5 ). The smooth convergence curves further confirm the algorithm’s stability when applied to aperiodic ZCZ sequence construction (Fig. 6 ). Conclusions This study proposes an optimization-based algorithm for designing aperiodic ZCS and aperiodic ZCZ sequence sets using Newton’s method, aiming to address the limitations of fixed parameters and high peak sidelobe levels found in existing approaches. Two optimization problems are formulated by minimizing the WPSL and CPSL, respectively. To simplify computation, the optimization tasks are converted into systems of nonlinear equations, which are solved using Newton’s method. The Jacobian matrix is computed via numerical differentiation to reduce computational cost. A loop iteration strategy is introduced to meet multiple constraints in the construction of aperiodic ZCZ sequences. Simulation results confirm that the proposed method yields sequence sets with excellent correlation properties and flexible parameter configurations. By tuning the weighting coefficients, low sidelobe levels can be achieved in specific regions of interest, accommodating different application requirements. The combination of flexible design parameters and favorable correlation performance makes the proposed sequences suitable for a wider range of practical scenarios.
Available online , doi: 10.11999/JEIT250057
Abstract:
Objective To address the key challenges of client model heterogeneity, data distribution heterogeneity, and text noise in medical dialogue federated learning, this paper proposes a trustworthiness-based, noise-resistant heterogeneous medical dialogue federated learning method, termed FedRH. FedRH enhances robustness by improving the objective function, aggregation strategy, and local update process, among other components, based on credibility evaluation. Methods Model training is divided into a local training stage and a heterogeneous federated learning stage. During local training, text noise is mitigated using a symmetric cross-entropy loss function, which reduces the risk of overfitting to noisy text. In the heterogeneous federated learning stage, an adaptive aggregation mechanism incorporates clean, noisy, and heterogeneous client texts by evaluating their quality. Local parameter updates consider both local and global parameters simultaneously, enabling continuous adaptive updates that improve resistance to both random and structured (syntax/semantic) noise and model heterogeneity. The main contributions are threefold: (1) A local noise-resistant training strategy that uses symmetric cross-entropy loss to prevent overfitting to noisy text during local training; (2) A heterogeneous federated learning approach based on client trustworthiness, which evaluates each client’s text quality and learning effectiveness to compute trust scores. These scores are used to adaptively weight clients during model aggregation, thereby reducing the influence of low-quality data while accounting for text heterogeneity; (3) A local continuous adaptive aggregation mechanism, which allows the local model to integrate fine-grained global model information. This approach reduces the adverse effects of global model bias caused by heterogeneous and noisy text on local updates. Results and Discussions The effectiveness of the proposed model is systematically validated through extensive, multi-dimensional experiments. The results indicate that FedRH achieves substantial improvements over existing methods in noisy and heterogeneous federated learning scenarios (Table 2 , Table 3 ). The study also presents training process curves for both heterogeneous models (Figure 3 ) and isomorphic models (Figure 6 ), supplemented by parameter sensitivity analysis, ablation experiments, and a case study. Conclusions The proposed FedRH framework significantly enhances the robustness of federated learning for medical dialogue tasks in the presence of heterogeneous and noisy text. The main conclusions are as follows: (1) Compared to baseline methods, FedRH achieves superior performance in client-side models under heterogeneous and noisy text conditions. It demonstrates improvements across multiple metrics, including precision, recall, and factual consistency, and converges more rapidly during training. (2) Ablation experiments confirm that both the symmetric cross-entropy-based local training strategy and the credibility-weighted heterogeneous aggregation approach contribute to performance gains.
Available online , doi: 10.11999/JEIT250291
Abstract:
Objective The deployment of Deep Neural Networks (DNNs) for inference tasks in industrial intelligence applications is constrained by the complexity of Directed Acyclic Graph (DAG) structures and dynamic resource limitations, making it challenging to simultaneously optimize both latency and accuracy. Existing methods are generally restricted to chain-structured DNNs and lack adaptive mechanisms to accommodate network variability and heterogeneous computational resources. To address these limitations, this paper proposes a Dynamic Adaptive Partitioning framework based on a Deep Early Exit mechanism (DAPDEE), designed to achieve low-latency, high-accuracy inference through edge-end collaborative computing. The significance of this work lies in its potential to provide a generalizable solution suitable for diverse network conditions and computing environments. Methods The proposed DAPDEE framework incorporates several technical innovations: First, it abstracts both chain and complex DNN architectures into a unified DAG representation, establishing a general topological foundation for partition optimization. Second, it employs offline optimization of early exit classifiers using a multi-task learning approach, requiring only the loading of pre-trained model parameters during deployment. Combined with real-time indicators, such as network bandwidth and terminal computational load, this enables dynamic selection of optimal exit points and partitioning strategies. Finally, an inverse search mechanism is applied to jointly optimize latency and accuracy, aiming to minimize single-frame end-to-end delay under light workloads and to maximize system throughput under heavy workloads. Through these strategies, the framework enables efficient inference suitable for time-sensitive scenarios, including smart manufacturing and autonomous driving. Results and Discussions Experimental results demonstrate that the DAPDEE framework substantially improves performance compared to conventional Device-Only methods under varying network conditions. Specifically, under CAT1, 3G, and 4G networks, DAPDEE achieves latency reductions of up to 7.7% under heavy loads and 7.5% under light loads, with throughput improvements reaching up to 9.9 times. Notably, the accuracy loss remains consistently below 1.2% (Fig. 6 , Fig. 7 ), confirming the framework’s ability to maintain reliable inference performance. These results verify the effectiveness of DAPDEE in adapting to dynamic network environments and heterogeneous computational loads. For instance, when the bandwidth is fixed at 1.1 Mbps (3G), the optimal partition strategy adjusts in response to varying latency constraints, revealing a positive correlation between relaxed latency requirements and deeper exit points (Fig. 6 ). Conversely, with fixed latency constraints and increasing bandwidth, the partition point progressively shifts toward the terminal device, reflecting enhanced resource utilization on the end side (Fig. 7 ). Furthermore, practical deployments on a PC and a Raspberry Pi-based intelligent vehicle validate the theoretical performance gains, as demonstrated by the applied partitioning strategies (Algorithm 1, Algorithm 2). Conclusions In summary, the proposed DAPDEE framework effectively addresses the challenge of balancing inference efficiency and accuracy in edge-end collaborative scenarios involving complex DAG-structured DNNs. By integrating early exit mechanisms with dynamic partitioning strategies and multidimensional load evaluation, DAPDEE exhibits strong adaptability and robustness under diverse network conditions and resource constraints. These findings advance the current state of DNN partitioning methodologies and offer practical insights for optimizing cloud-edge-terminal architectures and reinforcement learning-based adaptive mechanisms. Nonetheless, areas for further improvement remain. These include incorporating multi-task concurrency, refining the energy consumption model, and enhancing real-time partitioning efficiency for complex DAG topologies. Future research will focus on extending the framework to support multi-task collaborative optimization and reducing the computational complexity of online partitioning algorithms for DAG-structured DNNs.
Available online , doi: 10.11999/JEIT250274
Abstract:
This study considers a scenario in which an Unmanned Aerial Vehicle (UAV) equipped with a Reconfigurable Intelligent Surface (RIS) cooperates with a fixed RIS to enhance communication with a mobile User Equipment (UE) vehicle. A joint optimization problem is formulated to maximize the UE’s communication rate by controlling the UAV’s flight trajectory and the phase shifts of both RISs. Given the system complexity and environmental dynamics, a solution is proposed that integrates a Deep Deterministic Policy Gradient (DDPG) algorithm with phase-shift alignment to optimize continuous UAV trajectories and RIS configurations. Simulation results confirm that the proposed method achieves stable reward convergence within 1,000 training episodes. Compared with benchmark approaches, the algorithm improves communication rates by at least 3 dB over random trajectory and phase-shift strategies in dual-RIS deployments. The study further presents optimal UAV trajectories under varying base station and RIS placements and evaluates algorithm performance across different vehicle speeds. Objective This study investigates a vehicular communication scenario in which a UAV-mounted RIS cooperates with a fixed RIS to assist a mobile UE device. A joint optimization framework is established to maximize UE communication rates during movement by simultaneously optimizing the UAV trajectory and the phase shifts of both RISs. To address system complexity and environmental dynamics, a DDPG algorithm is employed for continuous trajectory control, while a low-complexity phase-shift alignment method configures the RISs. Simulation results show that the proposed algorithm achieves stable reward convergence within 1,000 training episodes and improves communication rates by at least 3 dB compared with randomized trajectory and phase-shift baselines. It also outperforms alternative reinforcement learning approaches, including Twin Delayed Deep Deterministic Policy Gradient (TD3) and Soft Actor-Critic (SAC). Optimal UAV trajectories are derived for various base station and RIS deployment scenarios, with additional simulations confirming robustness across a range of vehicle speeds. Methods This study establishes a Multiple-Input Single-Output (MISO) system in which a UAV-mounted RIS cooperates with a fixed RIS to support mobile vehicular communication, with the objective of maximizing user information rates. To address the complexity of continuous trajectory control under dynamic environmental conditions, a DDPG-based algorithm is developed. The phase shifts of RIS elements are optimized using a low-complexity alignment method. A reward function based on the achievable information rates of vehicular users is designed to guide the agent’s actions and facilitate policy learning. The proposed framework enhances adaptability by dynamically optimizing UAV trajectories and RIS configurations under time-varying channel conditions. Results and Discussions (1) The convergence behavior of the DDPG algorithm is verified in Fig. 3, where the reward values progressively converge as the number of training episodes increases. (2) Fig. 4 shows the effect of varying the number of RIS elements on system performance, indicating that additional elements lead to a steady increase in reward values, confirming the channel gain enhancement provided by RIS deployment. (3) As shown in Fig. 5, the DDPG algorithm outperforms baseline methods and demonstrates greater adaptability to target scenarios; concurrently, optimized RIS phase shifts yield significantly higher rewards than random configurations, validating the proposed phase-alignment strategy. (4) Figs. 6–7 highlight notable variations in UAV trajectories and system performance across different base station and RIS deployments, demonstrating the adaptability of the trajectory optimization strategy. Fig. 8 further compares performance across scenarios with optimized UAV trajectories, highlighting the algorithm’s versatility. (5) System performance under different UE mobility speeds is evaluated in Fig. 9, showing a performance decline at higher speeds, indicating strong efficacy in low-speed environments but reduced effectiveness under high-speed conditions. These results collectively illustrate the operational strengths and limitations of the proposed framework in dynamic vehicular communication systems. Conclusions This paper investigates a vehicular communication scenario assisted by both fixed and UAV-mounted mobile RISs, aiming to maximize UE information rates under dynamic mobility conditions. A joint optimization framework is developed, combining dual-RIS phase shift alignment based on channel state information with UAV trajectory planning using a DDPG algorithm. The proposed method features a low-complexity design that addresses both network architecture and RIS configuration challenges. Extensive simulations under varying vehicular speeds, RIS element counts, and base station deployments demonstrate the algorithm’s superiority over SAC, TD3, and randomized phase shift strategies. Results further highlight the framework’s adaptability to heterogeneous base station–RIS topologies and reveal performance degradation at higher vehicle speeds, indicating the need for future research into real-time adaptive mechanisms.
Available online , doi: 10.11999/JEIT250240
Abstract:
Objective Bauxite is a critical non-metallic mineral resource used in aluminum production, ceramic manufacturing, and refractory material processing. As global demand for aluminum and its derivatives continues to rise, improving the efficiency of bauxite resource utilization is essential. Accurate determination of quality parameters supports the reduction of waste from low-grade ores during smelting and improves overall process optimization. However, traditional chemical analyses are time-consuming, costly, complex, and subject to human error. Existing rapid testing methods, often based on machine learning, typically predict individual quality indicators and overlook correlations among multiple parameters. Deep learning, particularly multi-task learning, offers a solution to this limitation. Near-InfraRed (NIR) spectroscopy, a real-time, non-destructive analytical technique, is especially suited for assessing mineral quality. This study proposes a multi-indicator collaborative detection model—Gate-Depthwise Pointwise Network (G-DPN)—based on NIR spectroscopy to enable the simultaneous prediction of multiple bauxite quality parameters. The proposed approach addresses the limitations of conventional methods and supports efficient, accurate, and cost-effective real-time quality monitoring in industrial settings. Methods To accurately model the nonlinear relationships between NIR spectral features and bauxite quality parameters while leveraging inter-parameter correlations, this study proposes a dedicated representation model, G-DPN. The model incorporates large-kernel DepthWise Convolution (DWConv) to extract long-range dependencies within individual spectral channels, and PointWise Convolution (PWConv) to enable inter-channel feature fusion. A Spatial Squeeze-and-Excitation (sSE) mechanism is introduced to enhance spatial feature weighting, and residual connections support the integration of deep features. To further improve task differentiation, a Custom Gate Control (CGC) module is added to separate shared and task-specific features. Orthogonal constraints are applied within this module to reduce feature redundancy. Gate-controlled fusion enables each branch to focus on extracting task-relevant information while preserving shared representations. Additionally, quality parameter labels are normalized to address scale heterogeneity, allowing the model to establish a stable nonlinear mapping between spectral inputs and multiple output parameters. Results and Discussions This study applies large convolution kernels in DWConv to capture long-range dependencies within individual spectral channels (Fig. 3 ). Compared with conventional small-sized kernels (e.g., 3×3), which increase the receptive field but exhibit limited focus on critical spectral regions, large kernels enable more concentrated activation in key bands, thereby enhancing model sensitivity (Fig. 4 ). Empirical results confirm that the use of large kernels improves prediction accuracy (Table 6 ). Furthermore, compared to Transformer-based models, DWConv with large kernels achieves comparable accuracy with fewer parameters, offering computational efficiency. The CGC module effectively disentangles shared and task-specific features while applying orthogonal constraints to reduce redundancy. Its dynamic fusion mechanism enables adaptive feature sharing across tasks without compromising task-specific learning, thereby mitigating task interference and accounting for sample correlations (Fig. 6 ). Relative to conventional multi-task learning frameworks, the CGC-based architecture demonstrates superior performance in multi-parameter prediction (Table 6 ). Conclusions This study proposes a deep learning approach that integrates large-kernel DWConv and a CGC module for multi-parameter prediction of bauxite quality using NIR spectroscopy. DWConv captures long-range dependencies within spectral channels, while the CGC module leverages inter-parameter correlations to enhance feature sharing and reduce task interference. This design mitigates the effects of spectral peak overlap and establishes a robust nonlinear mapping between spectral features and quality parameters. Experiments on 424 bauxite samples show that the proposed G-DPN model achieves \begin{document}${R^2}$\end{document} 0.9226 , 0.9377 , and 0.9683 for aluminum, silicon, and iron content, respectively—outperforming conventional machine learning and existing deep learning methods. These results highlight the potential of combining NIR spectroscopy with G-DPN for accurate, efficient, and scalable mineral quality analysis, contributing to the sustainable utilization of bauxite resources.
Available online , doi: 10.11999/JEIT250130
Abstract:
Various types of noise in HyperSpectral Images (HSI) can severely degrade subsequent analysis. To address this problem, this study proposes a denoising framework based on Low-Rank Tensor Decomposition and Kronecker product Graph Laplacian Regularization (LRTDKGLR). Spatial and spectral graphs are constructed using Graph Signal Processing (GSP) and fused into a joint spatial-spectral product graph through the Kronecker product. Tucker decomposition is applied to this product graph to extract a unified low-dimensional representation, capturing the global spatial and spectral structures. A Kronecker Graph Laplacian Regularization (KGLR) term is introduced to enforce piecewise smoothness across both spatial and spectral dimensions, enhancing inter-band coherence. The denoising problem is formulated as an optimization task that integrates low-rank decomposition and graph-based regularization, solved efficiently using an Augmented Lagrangian Multiplier (ALM) approach. Experimental results on simulated and real HSI datasets demonstrate that LRTDKGLR achieves superior performance in edge preservation and noise suppression compared with existing HSI denoising methods. Objective Traditional denoising approaches often fail to simultaneously preserve spatial details and spectral fidelity due to the high dimensionality and complex spectral characteristics of HSI data. This study aims to develop a method that effectively suppresses mixed noise, such as Gaussian and stripe noise, while preserving critical spatial features and edge structures. The proposed approach leverages LRTDKGLR to enhance inter-dimensional correlations between spatial and spectral domains, ensuring improved noise reduction and detail preservation. Additionally, this research investigates an efficient ALM-based optimization strategy to address the HSI denoising problem, providing a more robust solution for noise reduction in high-dimensional, contaminated environments. Methods The proposed LRTDKGLR algorithm performs HSI denoising by effectively modeling spatial-spectral correlations. Separate spatial and spectral graphs are constructed and integrated through the Kronecker product to form a unified product graph representation. This joint graph considers both pixel intensity and the values of neighboring pixels across spatial and spectral dimensions, enabling enhanced denoising through spatial–spectral correlation modeling. Tucker decomposition is applied to extract a low-rank representation that captures global spatial-spectral relationships within the data. This decomposition facilitates effective modeling of the inherent structure of HSI while supporting the denoising process. The KGLR term models smoothness across both spatial and spectral domains, preserving essential spatial details and spectral continuity. The denoising task is formulated as an optimization problem that integrates low-rank tensor decomposition and KGLR. This problem is efficiently solved using the ALM method. The proposed approach achieves a balance between noise suppression and detail preservation, providing an effective solution for HSI denoising in high-dimensional, noisy conditions. Results and Discussions The proposed LRTDKGLR algorithm effectively exploits the inherent spatial and spectral correlations in HSI data. By incorporating a low-rank constraint and leveraging the similarity between adjacent spectral bands, the model enhances its capacity to capture inter-band spectral dependencies. Fig. 2 illustrates the denoising performance of various algorithms under Scenario 3, which combines Gaussian and impulse noise, applied to the 106th band of the Washington DC Mall dataset. A magnified view of a local region is also provided. The LRTV, LRTDTV, and LRTDGTV algorithms remove most of the noise but introduce over-smoothing, resulting in the loss of important edge structures. The NGmeet algorithm performs less effectively due to insufficient utilization of spatial neighborhood relationships. Although the LRMR, GLF, and TSLRLN algorithms reduce part of the noise, residual artifacts persist and over-smoothing remains evident. In contrast, the proposed LRTDKGLR algorithm demonstrates substantially improved denoising performance, supported by both visual comparisons and quantitative metrics. Fig. 3 presents the PSNR and SSIM values across multiple spectral bands under Scenario 3. The proposed method achieves higher performance in both metrics across most bands, indicating enhanced noise suppression and improved preservation of structural details. Numerical results summarized in Table 2 further confirm the effectiveness of the proposed approach, which consistently outperforms competing algorithms under identical conditions, providing superior denoising performance. Additionally, Table 3 shows that LRTDKGLR exceeds two representative deep learning-based methods, HSID-CNN and HSI-SDeCNN, across different noise levels. These findings demonstrate the robustness of the proposed method in the presence of Gaussian noise. Compared with deep learning-based approaches, LRTDKGLR offers practical advantages, including no requirement for pre-training, ease of deployment, and higher computational efficiency, which collectively improve its applicability to real-world HSI denoising tasks. Conclusions This study proposes an HSI denoising algorithm, LRTDKGLR, which integrates low-rank prior knowledge with a product graph model. The algorithm models HSI data as a product graph using GSP theory and applies Tucker decomposition to extract a core tensor and factor matrices, effectively capturing global spatial and spectral correlations. Simultaneously, KGLR is employed to model piecewise smoothness in both spatial and spectral dimensions, enhancing the representation of inter-dimensional relationships within the data. The denoising task is formulated as an optimization problem that combines low-rank tensor decomposition with KGLR constraints and is efficiently solved using the ALM method. Experimental results on simulated and real-world datasets demonstrate that the proposed LRTDKGLR algorithm achieves superior noise suppression while preserving structural details, validating its effectiveness for HSI denoising.
Available online , doi: 10.11999/JEIT250181
Abstract:
Objective With the advancement of Sixth-Generation (6G) communication technologies, the demand for highly reliable and secure transmission in high-speed mobile scenarios has grown significantly. Orthogonal Time Frequency Space (OTFS) modulation has emerged as a promising solution due to its superior transmission reliability in high-mobility environments. However, research on the security aspects of OTFS systems remains limited. To address this challenge, this study proposes a Three-Dimensional (3D) constellation encryption scheme for OTFS communication links. The objective is to enhance the security of OTFS systems while preserving communication performance by designing a novel 3D constellation structure and implementing physical-layer dynamic encryption based on a Coupled Map Lattice (CML) spatiotemporal chaotic system. This research provides a secure and efficient transmission strategy for future wireless communication systems. Methods The integration of 3D constellation encryption with OTFS modulation enhances the security of OTFS systems. First, a novel 3D constellation is designed, where 16 constellation points are uniformly distributed on the surface of a sphere centered at the origin. By optimizing the spatial distribution of constellation points, the minimum Euclidean Distance (MED) is increased and the average transmission power is reduced, thereby improving Bit Error Rate (BER) performance. Second, a dynamic encryption scheme for the 3D constellation over the OTFS link is proposed. In this scheme, pseudo-random sequences are generated using the CML system, quantized into 16-bit binary sequences, and employed to control both the selection of mapping rules and the rotational encryption of the 3D constellation. The encryption process operates as follows: first, the mapping rules are dynamically selected based on the quantized chaotic sequences; second, the rotation angles of the constellation points around the X, Y, and Z axes are determined by the same chaotic sequences. This dual encryption mechanism enhances the system’s security while maintaining reliable communication performance. Results and Discussions The performance of the proposed scheme is evaluated through extensive simulations. The results show that the optimized 3D constellation achieves a 22% improvement in MED compared with traditional 2D 16-quadrature amplitude modulation (16QAM). Compared with existing 3D constellations, the proposed design increases the MED by 5%, reduces average transmission power by 11%, and improves the Constellation Figure of Merit (CMF) by 10% (Table 2 , Table 3 ). Superior communication performance is also demonstrated, with a BER improvement of approximately 0.6 dB over existing methods (Fig. 5 , Fig. 6 ). In terms of security, the encryption scheme provides a key space of 10120, effectively resisting brute-force attacks. Key sensitivity tests confirm that even minor changes to the initial key result in completely different decrypted images (Fig. 7 ), verifying the robustness of the encryption mechanism. The encrypted images exhibit uniform histogram distributions (Fig. 8 ) and correlation coefficients near zero (Table 6 ), indicating strong resistance to statistical attacks. Additionally, the scheme maintains reliable performance under noisy conditions, with decrypted images preserving high quality even at low Signal-to-Noise Ratios (SNR) (Fig. 9 ). Conclusions This study combines OTFS communication links with 3D constellation encryption to realize physical-layer security for OTFS systems, enhancing both communication performance and transmission security. The proposed 3D constellation improves the MED by 5%, reduces average power by 11%, and increases the CMF by 10%, thereby enhancing BER performance. The dual dynamic encryption mechanism based on a CML system offers strong security. Simulation results show that the proposed scheme achieves a favorable balance between communication performance and security. BER performance improves by approximately 0.6 dB, while the large key space, high key sensitivity, strong resistance to statistical attacks, and good robustness collectively ensure enhanced security. The combination of OTFS modulation and 3D constellation encryption not only improves spectrum resource utilization but also strengthens channel confidentiality, enhancing resilience to interference and potential attacks. This scheme improves transmission security without compromising communication performance, offering broad application prospects in fields such as the Internet of Things, unmanned aerial vehicles, satellite communication, and ocean communication. The proposed approach is expected to provide more secure and reliable transmission solutions for future wireless communication systems.
Available online , doi: 10.11999/JEIT250077
Abstract:
Objective Space-air-ground networks represent a fundamental evolution in wireless communication infrastructure by extending conventional terrestrial networks into airspace and outer space through the integration of satellites, unmanned aerial vehicles, and ground-based nodes. These networks have become a cornerstone technology for future sixth-generation wireless communications, providing wide-area coverage and flexible networking capabilities that overcome the limitations of geographically constrained terrestrial systems. However, image transmission over space-air-ground networks faces considerable challenges due to inherent bandwidth constraints, severe channel impairments, and highly dynamic propagation environments. Traditional Separate Source-Channel Coding (SSCC) methods, although theoretically sound, exhibit poor performance under these adverse conditions, particularly near information-theoretic limits. The rapid expansion of multimedia applications and service demands requires new approaches to information extraction and transmission that meet ultra-reliable low-latency communication requirements. Conventional image coding algorithms, such as JPEG and JPEG2000, experience significant performance degradation in satellite communication systems due to channel impairments. These limitations highlight the need for advanced semantic communication frameworks that move beyond conventional bit-level transmission and prioritize the preservation of semantic content integrity under complex wireless conditions. Methods A resilient semantic communication framework is proposed for image transmission in space-air-ground networks, based on enhanced information bottleneck theory. The key innovation is the development of an augmented rate-distortion function that jointly optimizes system capacity, pixel-level reconstruction fidelity, semantic feature preservation, and perceptual quality. The framework combines deep learning with information-theoretic principles to ensure reliable performance under varying channel conditions. A Gumbel-Softmax approach is integrated with variable rate networks to enable dynamic rate adaptation in response to fluctuating channel states. The system employs a weighted multi-asymmetric Gaussian distribution model to characterize the probability density functions of heterogeneous semantic features, providing accurate entropy estimation in the latent space. The architecture incorporates attention mechanisms and residual learning structures to enhance feature extraction and semantic preservation. A reconfigurable neural network architecture is introduced, featuring adaptive module selection driven by real-time signal-to-noise ratio assessments and service quality requirements. The encoder subsystem consists of semantic extractor networks that identify and isolate critical image features, joint source-channel encoders that perform integrated compression and error protection, and adaptive networks that generate binary mask vectors for intelligent symbol selection. The semantic extractor combines convolutional neural networks with fully connected layers to capture hierarchical feature representations. The joint source-channel coding architecture integrates residual convolution blocks, attention feature blocks, and residual transpose convolution blocks to optimize rate-distortion performance. The adaptive network produces dynamic masks through Gumbel-Softmax sampling, controlling the transmission of semantic symbols based on their relevance and channel state. A two-stage training strategy is implemented. First, end-to-end optimization of the joint source-channel encoders and decoders is performed using mean squared error loss. This is followed by full system training based on a composite loss function that jointly considers transmission rate, pixel-level distortion, semantic distortion, and perceptual quality. Results and Discussions Comprehensive experimental validation is conducted using the CIFAR-10, CIFAR-100, and Kodak24 datasets to assess the effectiveness of the proposed framework. Performance is evaluated using multiple metrics, including Peak Signal-to-Noise Ratio (PSNR) for objective image quality assessment and USC metric for overall system efficiency. Comparative analysis with conventional JPEG combined with LDPC and QAM schemes shows substantial performance gains, particularly under low Signal-to-Noise Ratio (SNR) conditions (Fig. 3 , Fig. 4 ). The proposed resilient semantic communication framework consistently outperforms conventional methods across different compression ratios, demonstrating robust resistance to channel impairments and effectively mitigating the cliff effect observed in traditional SSCC systems. When compared with advanced deep learning-based approaches such as ADJSCC and DeepJSCC-V, the proposed method achieves significant improvements in both PSNR and transmission efficiency (Fig. 5 , Fig. 6 ). Efficiency evaluation using USC metrics shows that the proposed framework achieves higher utility values across various compression settings, with performance advantages becoming more evident as SNR decreases (Fig. 7 ). Further analysis of different network configurations demonstrates the adaptability of the architecture in balancing computational complexity and transmission performance (Fig. 8 , Fig. 9 ). Configurations with five network units consistently provide higher PSNR values compared to three- and four-unit designs. However, four-unit configurations achieve optimal efficiency under high SNR conditions, indicating effective resource allocation in response to varying channel states. Visual quality assessment using the Kodak dataset confirms improved reconstruction performance with reduced channel bandwidth requirements, supporting the practical feasibility of the proposed approach (Fig. 10 ). Computational complexity analysis shows that the five-unit configuration maintains complexity comparable to existing benchmarks, while three- and four-unit designs significantly reduce computational demands, supporting deployment on resource-constrained platforms (Table 4 ). These experimental results demonstrate that the proposed framework provides superior reconstruction quality, transmission efficiency, and adaptive capability across diverse and challenging wireless environments. Conclusions This study presents a resilient semantic communication framework that addresses key challenges in image transmission for space–air–ground networks. Experimental validation confirms that the proposed method achieves substantial improvements over conventional approaches in reconstruction quality, transmission efficiency, and adaptability.
Available online , doi: 10.11999/JEIT250221
Abstract:
Objective Unmanned Aerial Vehicles (UAVs) are widely applied in areas such as traffic monitoring, wireless coverage, and precision agriculture due to their high mobility and deployment flexibility. In air–ground communication scenarios requiring flexible deployment, UAV mobility can be leveraged to counteract external malicious jamming. Further, the collaborative operation of multiple UAVs enables improved system performance. However, the broadcast nature of wireless communication renders multiple UAV communication systems vulnerable to jamming attacks that disrupt legitimate communication services. Addressing this challenge, this study proposes a Signal-to-Interference-plus-Noise Ratio (SINR) adaptive Symbol-Level Precoding (SLP) and position joint optimization strategy for anti-jamming communication in multi-UAV systems. The approach fully exploits UAV mobility to enhance communication robustness under different user requirements. By integrating Coordinated Multi-Point (CoMP) transmission with SLP in a Multi-User Multiple-Input Single-Output (MU-MISO) system, the strategy improves interference utilization, enhances system energy efficiency, and reduces computational complexity. Methods An SINR adaptive SLP and position joint anti-jamming optimization strategy for multiple UAVs is proposed by integrating CoMP and SLP technologies. To address the challenges of three-dimensional operational space and the overlap of nodes assigned to multiple sets, a ground-to-air multi-node matching mechanism based on three-dimensional K-means++ collaborative set partitioning is designed. To reduce the computational complexity of the joint optimization process, an iterative optimization algorithm based on particle reconstruction is developed. This algorithm simultaneously solves for both the UAV precoding matrix and spatial positions with low computational overhead. Additionally, an SINR adaptive SLP approach is introduced to enable optimized power allocation for multiple UAVs, considering the varying power characteristics of jamming and noise experienced by users. Simulation results demonstrate that the integration of CoMP and SLP technologies effectively enhances the communication performance of jammed users, while stable communication performance is maintained for ordinary users. Results and Discussions In the proposed UAV anti-jamming communication strategy, the SINR of jammed users is improved without compromising the normal communication performance of ordinary users. In the simulation results, UAV positions are marked with five-pointed stars (Figs. 6 and 7 ), UAV coverage areas are represented by circles, and users are indicated by “*”. A comparison of SINR variations under four schemes (Fig. 8 ) shows that the received SINR of jammed users increases by approximately 12～13 dB, while the SINR of ordinary users remains above the required threshold. When different SINR thresholds are applied, the received SINR of each user type varies accordingly (Fig. 9 ). By setting appropriate thresholds based on actual scenario requirements, different energy allocation effects can be achieved. Following optimization, the Bit Error Rate (BER) of jammed users is significantly reduced (Fig. 10 ). The constellation diagrams comparing the received signals under two precoding schemes (Fig. 11 ) indicate that the proposed SINR adaptive SLP strategy for multiple UAVs effectively improves the SINR of jammed users, while maintaining the communication quality of ordinary users. Moreover, the fitness evolution curve of the iterative optimization algorithm based on particle reconstruction (Fig. 12 ) shows that the algorithm approaches the global optimal solution at an early stage of iteration. Conclusions To address the challenge of anti-jamming communication for multi-user services supported by multiple UAVs, this study integrates CoMP transmission with SLP technology and proposes an SINR adaptive SLP and position joint optimization strategy for multi-UAV anti-jamming communication. The strategy is implemented in two stages. First, to solve the clustering problem in three-dimensional space and allow nodes to belong to multiple groups, a ground-to-air multi-node matching mechanism based on three-dimensional K-means++ collaborative set partitioning is designed. Second, an SINR adaptive SLP method is proposed to optimize UAV power allocation based on the SINR requirements of different user types. To reduce the computational complexity of jointly optimizing the precoding matrix and UAV positions, an iterative optimization algorithm based on particle reconstruction is developed. Simulation results demonstrate that the proposed strategy, by combining CoMP and SLP, effectively improves the communication performance of jammed users while maintaining reliable communication for ordinary users.
Available online , doi: 10.11999/JEIT250242
Abstract:
The Integration of Sensing, Communication and Computing (ISCC) combined with Artificial Intelligence(AI) algorithms has emerged as a critical enabler of Sixth-Generation (6G) networks due to its high spectral efficiency and low hardware cost. AI-powered ISCC systems, which combine sensing, communication, computing, and intelligent algorithms, support fast data processing, real-time resource allocation, and adaptive decision-making in complex and dynamic environments. These systems are increasingly applied in intelligent vehicular networks—including Unmanned Aerial Vehicles (UAVs) and autonomous driving—as well as in radar, positioning, tracking, and beamforming. This overview outlines the development and advantages of AI-enabled ISCC systems, focusing on performance benefits, application potential, evaluation metrics, and enabling technologies. It concludes by discussing future research directions. Future 6G networks are expected to evolve beyond data transmission to form an integrated platform that unifies sensing, communication, computing, and intelligence, enabling pervasive AI services. Significance AI-powered ISCC marks a transformative shift in wireless communication, enabling more efficient spectrum utilization, reduced hardware cost, and improved adaptability in complex environments. This integration is central to the development of 6G networks, which aim to deliver intelligent and efficient services across applications such as autonomous vehicles, UAVs, and smart cities. The significance of this research lies in its potential to reshape the management and optimization of communication, sensing, and computing resources, advancing the realization of a ubiquitously connected and intelligent infrastructure. Progress Recent advances in AI—particularly in machine learning, deep learning, and reinforcement learning—have substantially improved the performance of ISCC systems. These methods enable real-time data processing, intelligent resource management, and adaptive decision-making, which are critical for future 6G requirements. Notable progress includes AI-driven waveform design, beamforming, channel estimation, and dynamic spectrum allocation, all of which enhance ISCC efficiency and reliability. Additionally, the integration of edge computing and federated learning has mitigated challenges related to latency, data privacy, and scalability, facilitating broader deployment of AI-enabled ISCC systems. Conclusions Research on AI-powered ISCC systems highlights the benefits of integrating AI with sensing, communication, and computing. AI algorithms improve resource efficiency, sensing precision, and real-time adaptability, making ISCC systems well suited for dynamic and complex environments. The adoption of lightweight models and distributed learning has broadened applicability to resource-limited platforms such as drones and IoT sensors. Overall, AI-enabled ISCC systems advance the realization of 6G networks, where sensing, communication, and computing are unified to support intelligent and ubiquitous services. Prospects The advancement of AI-powered ISCC systems depends on addressing key challenges, including data quality, model complexity, security, and real-time performance. Future research should focus on developing robust AI models capable of generalizing across diverse wireless environments. Progress in lightweight AI and edge computing will be critical for deployment in resource-constrained devices. The integration of multi-modal data and the design of secure, privacy-preserving algorithms will be essential to ensure system reliability and safety. As 6G networks evolve, AI-powered ISCC systems are expected to underpin intelligent, efficient, and secure communication infrastructures, reshaping human-technology interaction in the digital era.
Available online , doi: 10.11999/JEIT250033
Abstract:
Objective The human hand is a highly dexterous organ essential for performing complex tasks. However, dysfunction due to trauma, congenital anomalies, or disease substantially impairs daily activities. Restoring hand function remains a major challenge in rehabilitation medicine. Virtual Reality (VR) technology presents a promising approach for functional recovery by enabling hand pose reconstruction from surface ElectroMyoGraphy (sEMG) signals, thereby facilitating neural plasticity and motor relearning. Current sEMG-based hand pose estimation methods are limited by low accuracy and coarse joint resolution. This study proposes a new method to estimate the motion of 15 hand joints using eight-channel sEMG signals, offering a potential improvement in rehabilitation outcomes and quality of life for individuals with hand impairment. Methods The proposed method, termed All Hand joints Posture Estimation (AHPE), incorporates a continuous denoising network that combines sparse attention and multi-channel attention mechanisms to extract spatiotemporal features from sEMG signals. A dual-decoder architecture estimates both noisy hand poses and the corresponding correction ranges. These outputs are subsequently refined using a Bidirectional Long Short-Term Memory (BiLSTM) network to improve pose accuracy. Model training employs a composite loss function that integrates Mean Squared Error (MSE) and Kullback-Leibler (KL) divergence to enhance joint angle estimation and capture inter-joint dependencies. Performance is evaluated using the NinaproDB8 and NinaproDB5 datasets, which provide sEMG and hand pose data for single-finger and multi-finger movements, respectively. Results and Discussions The AHPE model outperforms existing methods—including CNN-Transformer, DKFN, CNN-LSTM, TEMPOnet, and RPC-Net—in estimating hand poses from multi-channel sEMG signals. In within-subject validation (Table 1 ), AHPE achieves a Root Mean Squared Error (RMSE) of 2.86, a coefficient of determination (R2) of 0.92, and a Mean Absolute Deviation (MAD) of 1.79° for MetaCarPophalangeal (MCP) joint rotation angle estimation. In between-subject validation (Table 2 ), the model maintains high accuracy with an RMSE of 3.72, an R2 of 0.88, and an MAD of 2.36°, demonstrating strong generalization. The model’s capacity to estimate complex hand gestures is further confirmed using the NinaproDB5 dataset. Estimated hand poses are visualized with the Mano Torch hand model (Fig. 4 , Fig. 5 ). The average R2 values for finger joint extension estimation are 0.72 (thumb), 0.692 (index), 0.696 (middle), 0.689 (ring), and 0.696 (little finger). Corresponding RMSE values are 10.217°, 10.257°, 10.290°, 10.293°, and 10.303°, respectively. A grid error map (Fig. 6 ) highlights prediction accuracy, with red regions indicating higher errors. Conclusions The AHPE model offers an effective approach for estimating hand poses from sEMG signals, addressing key challenges such as signal noise, high dimensionality, and inter-individual variability. By integrating mixed attention mechanisms with a dual-decoder architecture, the model enhances both accuracy and robustness in multi-joint hand pose estimation. Results confirm the model’s capacity to reconstruct detailed hand kinematics, supporting its potential for applications in hand function rehabilitation and human-machine interaction. Future work will aim to improve robustness under real-world conditions, including sensor noise and environmental variation.
Available online , doi: 10.11999/JEIT250182
Abstract:
Objective Research on node centrality in rail transit networks is essential for ensuring operational safety. Identifying critical stations enables the development of preventive strategies and mitigates the effects of station failures. Existing studies highlight two key determinants of station importance: static topology and dynamic passenger flow. However, most current approaches treat these factors separately, leading to biased estimations of node importance. To address this limitation, this study proposes a novel node centrality measure that integrates static topology and dynamic passenger flow. The method combines topology-based centrality—derived from PageRank and a modified K-shell algorithm—with passenger centrality, which is based on station inflow and outflow volumes. A reinforcement mechanism ensures that passenger centrality consistently amplifies topology-based centrality, balancing the influence of both components. Using cascade failure simulations and real-world data from the Shanghai Metro, the proposed method reliably identifies key stations. These findings offer practical guidance for the design and maintenance of robust metro systems, enhancing their resilience to cascading failures and improving overall safety and stability. Methods The proposed method integrates static topology and dynamic passenger flow to evaluate the centrality of urban rail transit stations, addressing the limitations of existing approaches in identifying key stations. It consists of three components: static topology centrality, dynamic passenger flow centrality, and an integration strategy. (1) Static topology centrality is computed using a combination of PageRank and an improved K-core method. This hybrid approach captures both connectivity and node importance based on iterative removal order, mitigating the loss of resolution caused by the long-tail degree distribution typical in transit networks. (2) Dynamic passenger flow centrality assigns separate weights to inbound and outbound flows to account for congestion effects and directional asymmetry—factors often overlooked in previous models. The weights are derived from average boarding and alighting times and adjusted for flow variations across morning peak, evening peak, and off-peak periods. (3) Integration strategy: An exponential function combines the two centrality measures, ensuring that passenger flow consistently amplifies topology-derived importance. This design improves sensitivity to dynamic changes while preserving structural significance. The integrated centrality metric enhances network resilience by supporting targeted protection of critical stations, based on both static and dynamic characteristics. Results and Discussions This study investigates the vulnerability of Shanghai’s urban rail transit network by simulating cascading failures and identifying key stations. Using dynamic passenger flow data from three representative weekdays across 14 subway lines—comprising 289 stations and 335 edges—a load-capacity model is applied to assess node importance based on each station’s effect on network stability during cascading failure events. The results (Fig. 1 , Fig. 2 , Fig. 3 ) demonstrate that the proposed method consistently and effectively identifies key stations, outperforming five benchmark approaches. When assessing passenger flow loss, passenger flow centrality alone proves more informative than static topology centrality alone (Fig. 3 ). Moreover, the influence of passenger flow centrality is more pronounced during morning and evening peak periods, highlighting the role of temporal dynamics in station vulnerability. These findings highlight the importance of incorporating dynamic passenger flow data into vulnerability assessments to better capture real-world operational risks. The ablation study (Table 1 ) confirms that the integrated centrality—combining static topology and dynamic flow—offers superior performance over single-factor methods. Prioritizing the protection of stations identified by this approach can substantially improve the network’s resilience to cascading failures and enhance overall system safety. Conclusions This study investigates station centrality in urban rail transit networks and analyzes the cascading failure effects triggered by key node disruptions using a load-capacity model. The proposed method enhances the ranking of station importance by jointly capturing network structure and usage patterns, offering practical value for the design and maintenance of safe and resilient metro systems.Experiments on the Shanghai Metro network show that the method effectively identifies critical stations, with improvements observed in network average efficiency, connectivity, and reduced passenger flow loss. The results indicate the following: (1) Accurate identification of key stations requires the integration of both static topology and dynamic passenger flow; relying on either alone limits precision. (2) Failures at key stations can induce substantial cascading failures, highlighting the need to prioritize their protection to improve system resilience. (3) Future research should focus on developing more effective strategies for integrating static and dynamic centrality measures to extend applicability across different urban transit networks.
Available online , doi: 10.11999/JEIT250352
Abstract:
This study presents a breakthrough in addressing NP-complete problems using a newly developed Electronic Probe Computer (EPC60). The system employs a hybrid serial–parallel computational model and performs large-scale parallel operations through seven probe operators. In benchmark tests on 3-coloring problems in graphs with 2,000 vertices, EPC60 achieves 100% accuracy, outperforming the mainstream solver Gurobi, which succeeds in only 6% of cases. Computation time is reduced from 15 days to 54 seconds. The system demonstrates high scalability and offers a general-purpose solution for complex optimization problems in areas such as supply chain management, finance, and telecommunications. Objective NP-complete problems pose a fundamental challenge in computer science. As problem size increases, the required computational effort grows exponentially, making it infeasible for traditional electronic computers to provide timely solutions. Alternative computational models have been proposed, with biological approaches—particularly DNA computing—demonstrating notable theoretical advances. However, DNA computing systems continue to face major limitations in practical implementation. Methods Computational Model: EPC is based on a non-Turing computational model in which data are multidimensional and processed in parallel. Its database comprises four types of graphs, and the probe library includes seven operators, each designed for specific graph operations. By executing parallel probe operations, EPC efficiently addresses NP-complete problems.Structural Features:EPC consists of four subsystems: a conversion system, input system, computation system, and output system. The conversion system transforms the target problem into a graph coloring problem; the input system allocates tasks to the computation system; the computation system performs parallel operations via probe computation cards; and the output system maps the solution back to the original problem format.EPC60 features a three-tier hierarchical hardware architecture comprising a control layer, optical routing layer, and probe computation layer. The control layer manages data conversion, format transformation, and task scheduling. The optical routing layer supports high-throughput data transmission, while the probe computation layer conducts large-scale parallel operations using probe computation cards. Results and Discussions EPC60 successfully solved 100 instances of the 3-coloring problem for graphs with 2,000 vertices, achieving a 100% success rate. In comparison, the mainstream solver Gurobi succeeded in only 6% of cases. Additionally, EPC60 rapidly solved two 3-coloring problems for graphs with 1,500 and 2,000 vertices, which Gurobi failed to resolve after 15 days of continuous computation on a high-performance workstation.Using an open-source dataset, we identified 1,000 3-colorable graphs with 1,000 vertices and 100 3-colorable graphs with 2,000 vertices. These correspond to theoretical complexities of O(1.3289n) for both cases. The test results are summarized in Table 1.Currently, EPC60 can directly solve 3-coloring problems for graphs with up to n vertices, with theoretical complexity of at least O(1.3289n).On April 15, 2023, a scientific and technological achievement appraisal meeting organized by the Chinese Institute of Electronics was held at Beijing Technology and Business University. A panel of ten senior experts conducted a comprehensive technical evaluation and Q&A session. The committee reached the following unanimous conclusions:1. The probe computer represents an original breakthrough in computational models.2. The system architecture design demonstrates significant innovation.3. The technical complexity reaches internationally leading levels.4. It provides a novel approach to solving NP-complete problems.Experts at the appraisal meeting stated, “This is a major breakthrough in computational science achieved by our country, with not only theoretical value but also broad application prospects.” In cybersecurity, EPC60 has also demonstrated remarkable potential. Supported by the National Key R&D Program of China (2019YFA0706400), Professor Xu Jin’s team developed an automated binary vulnerability mining system based on a function call graph model. Evaluation of the system using the Modbus Slave software showed over 95% vulnerability coverage, far exceeding the 75 vulnerabilities detected by conventional depth-first search algorithms. The system also discovered a previously unknown flaw, the “Unauthorized Access Vulnerability in Changyuan Shenrui PRS-7910 Data Gateway” (CNVD-2020-31406), highlighting EPC60’s efficacy in cybersecurity applications.The high efficiency of EPC60 derives from its unique computational model and hardware architecture. Given that all NP-complete problems can be polynomially reduced to one another, EPC60 provides a general-purpose solution framework. It is therefore expected to be applicable in a wide range of domains, including supply chain management, financial services, telecommunications, energy, and manufacturing. Conclusions The successful development of EPC offers a novel approach to solving NP-complete problems. As technological capabilities continue to evolve, EPC is expected to demonstrate strong computational performance across a broader range of application domains. Its distinctive computational model and hardware architecture also provide important insights for the design of next-generation computing systems.
Available online , doi: 10.11999/JEIT250208
Abstract:
Objective Globalization has driven growing demand for ubiquitous communication. However, traditional terrestrial networks face limitations in areas with poor infrastructure, such as deserts, oceans, and airspace. Satellite communication, with its flexibility, wide frequency coverage, and high capacity, offers a viable alternative for these environments. Yet, due to the open nature of satellite channels and long-distance transmission, signals remain vulnerable to interception, posing serious security challenges. Conventional wireless security measures, including physical-layer techniques and encryption, are limited by assumptions about computational hardness and the statistical structure of intercepted ciphertexts. Covert communication aims to reduce the probability of signal detection by eavesdroppers, providing an alternative layer of security. In Low Earth Orbit (LEO) satellite systems, high mobility leads to dynamic channel variations and misalignment of transmission beams, further complicating covert communication. To mitigate these challenges, Integrated Sensing And Communication (ISAC) technology can be embedded in satellite systems. By detecting the approximate location of potential eavesdroppers and directing radar beams to degrade their detection capability, ISAC improves communication covertness. This study proposes a covert communication strategy tailored for LEO satellite ISAC systems, offering enhanced security in satellite-based infrastructure. Methods This paper investigates a covert communication scheme in LEO satellite ISAC systems. First, the system model of the LEO satellite ISAC system is proposed, and the covertness constraints within the system are analyzed. Based on this, an optimization problem is formulated with the objective of maximizing the total covert communication rate for multiple users, subject to constraints including satellite power limits, radar power limits, sensing performance thresholds, and covertness requirements. This optimization problem is non-convex and highly coupled in variables, making it intractable to solve directly. To address this, relaxation variables are introduced to simplify the objective function into a solvable form. Subsequently, an alternating optimization algorithm is employed to decompose the original problem into two subproblems. One subproblem is transformed into an equivalent convex problem using methods like SemiDefinite Relaxation (SDR) and Successive Convex Approximation (SCA), which is then solved iteratively. The obtained solution from this subproblem is then used to solve the other subproblem. Once the solutions to both subproblems are determined, the original problem is effectively solved. Results and Discussions This paper validates the performance of the proposed covert communication transmission scheme through numerical simulations. To demonstrate the effectiveness of the proposed scheme, a comparison with a system lacking ISAC technology is introduced. First, the convergence of the proposed algorithm is verified (Fig. 2 ). The algorithm achieves rapid convergence under different resource allocation configurations in the system (converging at the 7th iteration). Additionally, higher covertness requirements lead to lower covert communication rates, as stricter covertness constraints reduce the allowable satellite transmit power. Increasing radar power causes a slight decline in the covert rate because Bob is subjected to minor interference from the radar beam. However, since the primary radar beam is focused on Eve, the interference level remains limited. Second, a higher number of satellite antennas improves the system’s covert communication rate (Fig. 3 ). This is attributed to the increased spatial dimensions available for optimizing signal transmission and reception. More antennas enable additional independent signal paths, enhancing transmission performance and flexibility. When the satellite is equipped with 81 antennas and the covertness requirement is 0.1, the total covert rate reaches 17.18 bit/(s·Hz). Compared to the system without ISAC technology, the proposed system demonstrates superior resistance to detection (Fig. 4 ). The radar beam introduces interference to eavesdroppers, and higher radar power degrades the eavesdropper’s detection performance. Finally, increasing the satellite transmit power improves the covert communication rate (Fig. 5 ). In the system without ISAC, the satellite power cannot be arbitrarily increased due to covertness constraints. However, the ISAC-enabled system leverages radar integration to grant the satellite greater flexibility in power allocation, thereby enhancing the covert rate. Notably, raising the lower bound of sensing performance slightly reduces the covert rate, as higher sensing demands require increased radar power, which introduces additional interference to Bob’s signal reception. Conclusions This paper investigates a covert communication transmission scheme in an LEO satellite-enabled ISAC system. An optimization problem is formulated to maximize the sum of multi-user covert communication rates, subject to constraints including covertness requirements, minimum sensing performance, radar power budget, and satellite power budget. The alternating optimization algorithm and SCA algorithm are jointly employed to design the radar and satellite beamforming, as well as the radar receiver filter. Simulation results demonstrate that, compared to a system without radar beam interference, the proposed system with radar beam interference significantly reduces the detectability of communication between Alice and Bob. Furthermore, the integration of radar enhances the satellite’s flexibility to increase transmit power, thereby improving the overall covert communication rate of the system.
Available online , doi: 10.11999/JEIT250093
Abstract:
Objective The ElectroEncephaloGram (EEG)-based Neurofeedback Regulation (ENR) system is designed for real-time modulation of dysregulated stress responses to reduce symptoms of Post-Traumatic Stress Disorder (PTSD) and anxiety. This study evaluates the system’s effectiveness and applicability using a series of neurofeedback paradigms tailored for both PTSD patients and healthy participants. Methods Employing real-time EEG monitoring and feedback, the ENR system targets the regulation of alpha wave activity, to alleviate mental health symptoms associated with dysregulated stress responses. The system integrates MATLAB and Unity3D to support a complete workflow for EEG data acquisition, processing, storage, and visual feedback. Experimental validation includes both PTSD patients and healthy participants to assess the system’s effects on neuroplasticity and emotional regulation. Primary assessment indices include changes in alpha wave dynamics and self-reported reductions in stress and anxiety. Results and Discussions Compared with conventional therapeutic methods, the ENR system shows significant potential in reducing symptoms of PTSD and anxiety. During functionality tests, the system effectively captures and regulates alpha wave activity, enabling real-time and efficient neurofeedback. Dynamic adjustment of feedback thresholds and task paradigms allows participants to improve stress responses and emotional states following training. Quantitative data indicate clear enhancements in EEG pattern modulation, while qualitative assessments reflect improvements in participants’ self-reported stress and anxiety levels. Conclusion This study presents an effective and practical EEG-based neurofeedback regulation system that proves applicable and beneficial for both individuals with PTSD and healthy participants. The successful implementation of the system provides a new technological approach for mental health interventions and supports ongoing personalized neuroregulation strategies. Future research should explore broader applications of the system across neurological conditions to fully assess its efficacy and scalability.
Available online , doi: 10.11999/JEIT250180
Abstract:
This paper proposes a novel double-trench Silicon Carbide (SiC) MOSFET that integrates a Schottky diode structure to improve reverse recovery and switching characteristics. In the proposed design, the conventional right-side trench channel is replaced by a Schottky diode, and a split-gate structure is connected to the source. The Schottky diode suppresses body diode conduction and eliminates the bipolar degradation effect. The split gate reduces the coupling area between the gate and drain, thereby lowering the feedback capacitance and gate charge. In addition, when the split gate is connected to a high potential, it attracts electrons to form an accumulation layer near the source, which increases electron density. During reverse conduction, the current flows through the Schottky diode, while the split gate enhances electron concentration and thus current density. The split-gate structure also shields the gate from the drain, reducing the Gate–Drain Charge (QGD) and improving switching performance. Objective Conventional Double-Trench MOSFETs (DT-MOS) typically require an external anti-parallel diode to function as a freewheeling diode in converter and inverter systems. This necessitates additional module area and increases parasitic capacitance and inductance. Utilizing the body diode as a freewheeling diode could reduce cost and save space. However, this approach presents two major challenges. First, due to the wide bandgap of SiC, the turn-on voltage of the intrinsic body diode rises significantly (approaching 3 V), which increases switching loss. This paper presents a new DT-MOS, referred to as SDT-MOS, with an integrated Schottky diode, demonstrated using TCAD SENTAURUS. In the proposed structure, the conventional right-side channel is replaced with a Schottky junction, and a source-connected split gate is embedded in the gate oxide. The SDT-MOS achieves low power consumption and reduced reverse recovery current. Methods Sentaurus TCAD is used to simulate and analyze the electrical performance of the proposed structure and its conventional counterpart. The simulation includes key physical models, such as mobility saturation under high electric fields, Auger recombination, Okuto–Crowell impact ionization, bandgap narrowing, and incomplete ionization. To improve simulation accuracy and align the results with experimental data, interface traps and fixed charges at the SiC/SiO2 interface are also considered. Results and Discussions The Miller capacitance (Crss or CGD) extracted at Vds of 400 V is 29 pF/cm2 for the SDT-MOS, representing a 61% reduction compared to the DT-MOS, which has a CGD of 74 pF/cm2. This reduction is primarily attributed to the integrated split-gate structure, which decreases the capacitive coupling between the gate and drain electrodes (Fig. 7 ). The total switching loss (Eon + Eoff) of the SDT-MOS is 1.58 mJ/cm2 , which is 59.3% lower than that of the DT-MOS (3.88 mJ/cm2 ), due to the improved switching characteristics enabled by the split gate (Fig. 10 ). In addition, the peak reverse recovery current (IRRM) and reverse recovery charge (QRR) of the SDT-MOS are 165 A/cm2 and 1.39 μC/cm2, representing reductions of 31.3% and 54%, respectively, compared to the DT-MOS (Fig. 11 ). Conclusions A novel double-trench SiC MOSFET (SDT-MOS) with an integrated Schottky diode has been numerically investigated. In this structure, the right-side channel of a conventional DT-MOS is replaced with a Schottky diode, and a split gate is connected to the source. This configuration results in improved switching and reverse recovery performance. With appropriate optimization of key design parameters, the SDT-MOS retains the fundamental characteristics of a standard MOSFET. Compared with the conventional DT-MOS, the proposed device suppresses body diode conduction, mitigates bipolar degradation, and achieves a 64.9% reduction in QGD. Switching loss is reduced by 59.3%, and QRR is reduced by 54%. These enhancements make the SDT-MOS a strong candidate for high-efficiency, high–power density applications.
Available online , doi: 10.11999/JEIT221203
Abstract:
To overcome the limitation of the Federated Learning (FL) when the data and model of each client are all heterogenous and improve the accuracy, a personalized Federated learning algorithm with Collation game and Knowledge distillation (pFedCK) is proposed. Firstly, each client uploads its soft-predict on public dataset and download the most correlative of the k soft-predict. Then, this method apply the shapley value from collation game to measure the multi-wise influences among clients and quantify their marginal contribution to others on personalized learning performance. Lastly, each client identify it’s optimal coalition and then distill the knowledge to local model and train on private dataset. The results show that compared with the state-of-the-art algorithm, this approach can achieve superior personalized accuracy and can improve by about 10%.
To overcome the limitation of the Federated Learning (FL) when the data and model of each client are all heterogenous and improve the accuracy, a personalized Federated learning algorithm with Collation game and Knowledge distillation (pFedCK) is proposed. Firstly, each client uploads its soft-predict on public dataset and download the most correlative of the k soft-predict. Then, this method apply the shapley value from collation game to measure the multi-wise influences among clients and quantify their marginal contribution to others on personalized learning performance. Lastly, each client identify it’s optimal coalition and then distill the knowledge to local model and train on private dataset. The results show that compared with the state-of-the-art algorithm, this approach can achieve superior personalized accuracy and can improve by about 10%.
Available online , doi: 10.11999/JEIT210265
Abstract:
The application of Frequency Diverse Array and Multiple Input Multiple Output (FDA-MIMO) radar to achieve range-angle estimation of target has attracted more and more attention. The FDA can simultaneously obtain the degree of freedom of transmitting beam pattern in angle and range. However, its performance is degraded due to the periodicity and time-varying of the beam pattern. Therefore, an improved Estimating Signal Parameter via Rotational Invariance Techniques (ESPRIT) algorithm to estimate the target’s parameters based on a new waveform synthesis model of the Time Modulation and Range Compensation FDA-MIMO (TMRC-FDA-MIMO) radar is proposed. Finally, the proposed method is compared with identical frequency increment FDA-MIMO radar system, logarithmically increased frequency offset FDA-MIMO radar system and MUltiple SIgnal Classification (MUSIC) algorithm through the Cramer Rao lower bound and root mean square error of range and angle estimation, and the excellent performance of the proposed method is verified.
The application of Frequency Diverse Array and Multiple Input Multiple Output (FDA-MIMO) radar to achieve range-angle estimation of target has attracted more and more attention. The FDA can simultaneously obtain the degree of freedom of transmitting beam pattern in angle and range. However, its performance is degraded due to the periodicity and time-varying of the beam pattern. Therefore, an improved Estimating Signal Parameter via Rotational Invariance Techniques (ESPRIT) algorithm to estimate the target’s parameters based on a new waveform synthesis model of the Time Modulation and Range Compensation FDA-MIMO (TMRC-FDA-MIMO) radar is proposed. Finally, the proposed method is compared with identical frequency increment FDA-MIMO radar system, logarithmically increased frequency offset FDA-MIMO radar system and MUltiple SIgnal Classification (MUSIC) algorithm through the Cramer Rao lower bound and root mean square error of range and angle estimation, and the excellent performance of the proposed method is verified.
Available online , doi: 10.11999/JEIT201066
Abstract:
To solve the problem of Group Repetition Interval (GRI) selection in the construction of the enhanced LORAN (eLORAN) system supplementary transmission station, a screening algorithm based on cross interference rate is proposed mainly from the mathematical point of view. Firstly, this method considers the requirement of second information, and on this basis, conducts a first screening by comparing the mutual Cross Rate Interference (CRI) with the adjacent Loran-C stations in the neighboring countries. Secondly, a second screening is conducted through permutation and pairwise comparison. Finally, the optimal GRI combination scheme is given by considering the requirements of data rate and system specification. Then, in view of the high-precision timing requirements for the new eLORAN system, an optimized selection is made in multiple optimal combinations. The analysis results show that the average interference rate of the optimal combination scheme obtained by this algorithm is comparable to that between the current navigation chains and can take into account the timing requirements, which can provide referential suggestions and theoretical basis for the construction of high-precision ground-based timing system.
To solve the problem of Group Repetition Interval (GRI) selection in the construction of the enhanced LORAN (eLORAN) system supplementary transmission station, a screening algorithm based on cross interference rate is proposed mainly from the mathematical point of view. Firstly, this method considers the requirement of second information, and on this basis, conducts a first screening by comparing the mutual Cross Rate Interference (CRI) with the adjacent Loran-C stations in the neighboring countries. Secondly, a second screening is conducted through permutation and pairwise comparison. Finally, the optimal GRI combination scheme is given by considering the requirements of data rate and system specification. Then, in view of the high-precision timing requirements for the new eLORAN system, an optimized selection is made in multiple optimal combinations. The analysis results show that the average interference rate of the optimal combination scheme obtained by this algorithm is comparable to that between the current navigation chains and can take into account the timing requirements, which can provide referential suggestions and theoretical basis for the construction of high-precision ground-based timing system.
