Wire Length Driven Tension Refine Based Macro Placer

ZHU Yanzhen; YAN Haopeng; CAI Shuting; GAO Peng

doi:10.11999/JEIT241079

Volume 47 Issue 7

Jul. 2025

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Article Navigation > Journal of Electronics & Information Technology > 2025 > 47(7): 2396-2404

ZHU Yanzhen, YAN Haopeng, CAI Shuting, GAO Peng. Wire Length Driven Tension Refine Based Macro Placer[J]. Journal of Electronics & Information Technology, 2025, 47(7): 2396-2404. doi: 10.11999/JEIT241079

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ZHU Yanzhen, YAN Haopeng, CAI Shuting, GAO Peng. Wire Length Driven Tension Refine Based Macro Placer[J]. Journal of Electronics & Information Technology, 2025, 47(7): 2396-2404. doi: 10.11999/JEIT241079

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Wire Length Driven Tension Refine Based Macro Placer

doi: 10.11999/JEIT241079 cstr: 32379.14.JEIT241079

School of Integrated Circuits, Guangdong University of Technology, Guangzhou 510006, China

Funds: Guangdong S&T Programme (2022B0701180001)

Received Date: 2024-12-06
Rev Recd Date: 2025-03-29

Available Online: 2025-04-11

Publish Date: 2025-07-22

Abstract

Abstract

Objective With the introduction of reuse methodologies in integrated circuit design, the utilization of macro cells in Very Large Scale Integration (VLSI) has significantly increased. However, the considerable size difference between macro cells and standard cells presents a significant challenge for circuit placers. This study proposes a novel macro placer, WIMPlace, based on tension fine-tuning and wirelength-driven approaches. The aim is to address issues such as density imbalance and degradation of solution quality observed in existing mixed-size placers, thereby providing a more effective solution for VLSI design. Methods The proposed method in this paper consists of four stages: preprocessing, pre-placement, macro cell fine-tuning, and macro legalization. Initially, a weight-based partitioning approach is employed to group standard cells with macro into supersets, addressing density issues during the initial placement (Section 3.1). In the pre-placement stage, the DREAMPlace 2.0 tool is used for placing standard cells, and the initial positions of macro cells are determined based on the locations of these clusters (Section 3.2). A local tension model, inspired by the principle of surface tension in liquids, is then adopted to fine-tune the positions of macros, ensuring that connections between standard cells and macros are as compact as possible (Section 3.3, Fig. 2). Finally, a constraint graph-based macro legalization strategy is applied to prevent overlaps between macros (Section 3.4, Fig. 3). Results and Discussions Experimental results demonstrate that the WIMPlace achieves exceptional performance on the MMS benchmark, outperforming other advanced mixed-size placers, such as ePlace-MS and DREAMPlace 4.0. Specifically, in 15 out of 16 cases, it achieved the shortest wirelength, with average reductions of 4.31% and 2.39%, respectively (Section 4, Table 2). Additionally, WIMPlace exhibits excellent solution stability, particularly showing a linear increase in runtime as the number of cells increases (Section 4, Fig. 4), indicating that the algorithm not only optimizes wirelength effectively but also demonstrates high computational efficiency. Notably, in the newblue3 case, despite the macro cells occupying a significant portion of the chip area, WIMPlace still demonstrated strong adaptability. Conclusions In summary, WIMPlace, as proposed in this paper, is an efficient macro cell placer that achieves gradual fine-tuning optimization of macro cells by combining gradient field movements based on a surface tension analogy and employing preprocessing techniques to balance macros with their associated standard cells. Compared to existing mixed-size placers, WIMPlace demonstrates superior performance across multiple key metrics, particularly in wirelength optimization. Future work could focus on integrating additional design objectives, such as timing, congestion, and thermal management, to enhance the applicability and flexibility of WIMPlace. This study provides new perspectives and technical approaches for VLSI design.
- Very Large Scale Integration(VLSI),
- Floorplan,
- Macro placement,
- Mixed-size placement,
- Iterative placement

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References(20)

References

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