一种模拟电路自动综合中的数据阵列描述方法

高雪莲; 石寅

一种模拟电路自动综合中的数据阵列描述方法

高雪莲,
石寅

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- 被引次数: 0
出版历程
- 收稿日期: 2004-11-25
- 修回日期: 2005-06-07
- 刊出日期: 2006-07-19

A Data Array Description Method in Automatic Synthesis of Analog Circuit

摘要

摘要: 该文提出模拟电路的数据阵列描述方法及其与描述方法协同工作的电路生成规则。其中，数据阵列表述融入了成功的设计经验，并且能够有效地解决多端器件的电路连接问题；电路生成规则确保在不出现无效电路结构的前提下，生成高质量的运放电路结构。这种新的生成式电路设计方法克服了选择式拓扑设计方法依赖设计者经验和生成式拓扑设计方法难以利用电路设计成功经验的局限。从若干经典子电路结构开始运放电路自动生成，保证了生成电路拓扑的质量。论文以运放电路为例，利用该数据阵列描述方法和电路生成规则，实验生成两个性能特点不同的运放电路，并对电路参数进行合理确定和电路仿真。
- 模拟电路;自动综合;数据阵列描述方法
Abstract: This paper presents an analog circuit data array description method and circuit-constructing rules that coordinately work with description language. With the prerequisite of no invalid circuit structure, circuit-constructing rules create high quality op-amp circuit structure. This new technique, starting from classic sub-circuit model, automatically creating op-amp circuit, guarantees the quality of circuit construction. Results are reported to validate the effectiveness of this approach for construction-design automation of op-amp circuit.

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参考文献(1)

Goh C, li Y. GA automated design and synthesis of analog circuitswith practical constraints, 2001. Proceedings of the 2001Congress on Evolutionary Computation, Seoul, Korea, 27-30 May,2001, Vol. 1: 170 . 177 .[2]Papa G, Silc J. Automatic large-scale integrated circuit synthesisusing allocation-based scheduling algorithm, Microprocessorsand Microsystems, 2002, 26(3): 139 . 147.[3]Koh H Y, Sequin C H, Gray P R. OPASYN：A compiler forCMOS operational amplifiers[J].IEEE Trans. on Computer-AidedDesign of Integrated Circuits and Systems.1990, 9(2):113-[4]Gupta S K, Hasan M M. KANSYS: A CAD tool for analog circuitsynthesis. 9th International Conference on VLSI Design,Bangalore, India, Jan. 1996: 333 . 334.[5]El-Turky F, Perry E E. BLADES: An artificial intelligenceapproach to analog circuit design[J].IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems.1989, 8(6):680-[6]Makris C A, et al.. CHIPAIED: A new approach to analogueintegrated circuit design. IEE Colloquium on Analogue VLSI,London,UK,10 May, 1990: 1/1 . 111.[7]Lohn J D, Colombano S P. A circuit representation technique forautomated circuit design. IEEE Trans. on EvolutionaryComputation, 1999, 3(3): 205 . 219.[8]Prakobwaitayakit K, Fujii N. A neural network approach to circuittopology generator. The 2000 IEEE Asia-Pacific Conference onCircuits and Systems, Tianjin, China, 4-6 Dec., 2000: 93 . 96.

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