高性能并行比特变换运动估计硬件架构设计
doi: 10.3724/SP.J.1146.2010.00636
An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation
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摘要: 为了满足便携式实时全高清视频的处理要求，该文基于1维源像素线性阵列，提出一种新的多宏块并行比特变换运动估计结构，克服以往2维阵列消耗资源较多且延时大的不足。该文结构易于并行扩展且更为节约资源，进一步还针对脉动胞元和数据存储器这两个系统瓶颈进行优化设计。FPGA实现结果表明，与同类设计相比，该文设计在面积和速度上均有改善，LUTs资源节约43%，DFFs资源节约25%，BRAMs数目节约75%，性能提升32%。Abstract: In order to meet the processing requirements of portable real-time full HD video compression, this paper proposes a novel macroblock-level parallel architecture based on 1-D source pixels based linear array, which overcomes the problem of massive amount of resources and large delay caused by 2-D arrays used in literatures. The proposed architecture is easy to extend and area-economical. Furthermore, towards the system bottlenecks, systolic cell and data memory organization, optimized structure are presented. Compared with the traditional architecture, the proposed architecture can achieve the improvements of speed and area at the same time. FPGA implementation results show that, LUTs is reduced by 43%, DFFs is reduced by 25%, BRAMs is reduced by 75%, and performance is increased by 32%.
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Key words:
- Motion estimation /
- One-bit transform /
- Hardware architecture /
- Parallel processing /
- Systolic arrays
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