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物理不可克隆函数-多位并行异或运算一体化设计技术

李刚 周俊杰 汪鹏君 张茂林 郭宇锋

李刚, 周俊杰, 汪鹏君, 张茂林, 郭宇锋. 物理不可克隆函数-多位并行异或运算一体化设计技术[J]. 电子与信息学报. doi: 10.11999/JEIT240300
引用本文: 李刚, 周俊杰, 汪鹏君, 张茂林, 郭宇锋. 物理不可克隆函数-多位并行异或运算一体化设计技术[J]. 电子与信息学报. doi: 10.11999/JEIT240300
LI Gang, ZHOU Junjie, WANG Pengjun, ZHANG Maolin, GUO Yufeng. Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240300
Citation: LI Gang, ZHOU Junjie, WANG Pengjun, ZHANG Maolin, GUO Yufeng. Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT240300

物理不可克隆函数-多位并行异或运算一体化设计技术

doi: 10.11999/JEIT240300
基金项目: 国家自然科学基金(62374117, 62234008),浙江省自然科学基金(LY22F040004),中国博士后科学基金(2023M731776),温州市基础性科研项目(G20240015)
详细信息
    作者简介:

    李刚:男,副教授,研究方向为集成电路设计、硬件安全

    周俊杰:男,硕士生,研究方向为物理不可克隆函数设计

    汪鹏君:男,教授,研究方向为集成电路设计、信息安全等技术及其相关理论

    张茂林:男,讲师,研究方向为超宽禁带半导体材料、器件和功率集成

    郭宇锋:男,教授,研究方向为新型功率器件、功率和射频集成电路与集成系统

    通讯作者:

    郭宇锋 yfguo@njupt.edu.cn

  • 中图分类号: TN4;TP43

Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations

Funds: The National Natural Science Foundation of China (62234008, 62374117), Zhejiang Provincial Natural Science Foundation of China (LY22F040004), China Postdoctoral Science Foundation (2023M731776), Wenzhou Basic Scientific Research Projects (G20240015)
  • 摘要: 物理不可克隆函数(PUF)和异或(XOR)运算在信息安全领域均发挥着重要作用。为突破PUF与逻辑运算之间的功能壁垒,通过对PUF工作机理和差分串联电压开关逻辑(DCVSL)的研究,该文提出一种基于DCVSL异或门级联单元随机工艺偏差的PUF和多位并行异或运算电路一体化设计方案。通过在DCVSL异或门差分输出端增加预充电管并在对地端设置管控门,可实现PUF特征信息提取、异或/同或(XOR/XNOR)运算和功率控制3种工作模式自由切换。此外,针对PUF响应稳定性问题,提出极端工作点和黄金工作点共同参与标记的不稳定位混合筛选技术。基于TSMC 65 nm工艺,对输入位宽为10位的电路进行全定制版图设计,面积为38.76 μm2。实验结果表明,PUF模式下,可产生1 024位输出响应,混合筛选后可获得超过512位稳定的密钥,且具有良好的随机性和唯一性;运算模式下,可同时实现10位并行异或和同或运算,功耗和延时分别为2.67 μW和593.52 ps。功控模式下,待机功耗仅70.5 nW。所提方法为突破PUF“功能墙”提供了一种新的设计思路。
  • 图  1  传统APUF电路结构

    图  2  基于CMOS和DCVSL的3输入异或门

    图  3  PUF与逻辑运算融合设计电路结构

    图  4  多模式工作状态

    图  5  偏差预选

    图  6  复合筛选示意图与流程图

    图  7  PUF全定制版图

    图  8  逻辑运算仿真波形

    图  9  PUF响应的随机性

    图  10  PUF响应的唯一性和稳定性

    图  11  PUF原始误码率和筛选后的误码率

    图  12  不同筛选方式的筛选效率

    1  标记实际不稳定位

     standard_response = PUF_at (SV, ST), unstable_bits = 0
     for each voltage∈ [LV, ···, SV, ···, HV] do
      for each temperature ∈ [LT, ···, ST, ···, HT] do
       if measured_response[i] != standard_response[i]
        unstable_bits[i] = 1
        end if
       end for
     end for
    下载: 导出CSV

    2  筛选不稳定位

     Filter_bits=1;
     for each (voltage, temperature)∈ [(SV,ST), (LV,LT),
     (LV,HT), (HV,LT), (HV,HT)] do
      for i from 1 to 2n do
       if left_response[i] != right_response [i]
        filter[i] = 1;
        end if
       end for
     end for
     for i from 1 to 2n do
      if filter[i] ==0 and unstable_bits==1
       Filter_bits++
       break
      end if
     end for
    下载: 导出CSV

    表  1  与相关文献性能对比

    VLSI’20[16] TCASI’22[17] JSSC’22[13] ISCAS’23[18] 本文
    工艺尺寸(nm) 65 65 28 65 65
    比特特征尺寸(F2) 215 1125 8.95
    电压范围(V) 1.0~1.4 0.5~1.0 0.75~1.05 0.7~1.5 1.0~1.4
    温度范围(°C) –40~125 –10~80 –25~100 0~120 –40~85
    原始误码率(%) 2.12* 3.00 3.78 5.025* 3.82
    随机性(%) 49.30 50.11 50.59 49.87
    唯一性 0.500 0 0.494 7 0.5030 0.499 8 0.502 8
    逻辑运算
    功率控制
    不稳定位筛选
    *最大误码率
    下载: 导出CSV
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出版历程
  • 收稿日期:  2024-04-19
  • 修回日期:  2024-08-22
  • 网络出版日期:  2024-08-30

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