SDL PUF: A High Reliability Self-Adaption Deviation Locking PUF
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摘要: 物理不可克隆函数(Physical Unclonable Function, PUF)作为一种新的硬件安全原语，通过提取工艺偏差产生唯一的响应序列为计算系统提供可信根。然而现有基于现场可编辑门阵列(Field Programmable Gate Array, FPGA)的PUF难以在较宽的温度和电压范围内实现高可靠性。该文提出一种基于自定时环(Self-Timed Ring，STR)的自适应偏差锁定PUF(Self-adaption Deviation Locking PUF, SDL PUF)，首先利用STR延迟引起的振荡频率差产生PUF响应；然后通过在初始化阶段自适应配置，有效扩大STR环内的事件到达时间偏差，从而显著提高PUF的可靠性；最后进一步提出一种对比混淆策略，通过提取工艺偏差自动生成随机比特配置并混淆比较器，以抵抗侧信道攻击。在Xilinx Virtex-6 FPGA上实验结果表明， SDL PUF在0～80°C的温度范围和0.85～1.15V的电压范围内误码率为0， 唯一性和均匀性分别为49.29%和49.84%。Abstract: As a novel hardware security primitive, Physical Unclonable Function (PUF) extracts process deviations to generate a unique response sequence, providing a root of trust for computing systems. However, existing PUFs based on Field Programmable Gate Arrays (FPGAs) cannot maintain high reliability over a wide range of temperatures and voltages. In this work, we propose a Self-Timed Ring (STR) based Self-adaption Deviation Locking PUF (SDL PUF). Firstly, the PUF response is generated utilizing the oscillation frequency difference caused by the STR delay. Secondly, the adaptive configuration in the initialization stage can effectively expand the deviation of the event arrival time in the STR, substantially enhancing the reliability of PUF. Finally, a comparator obfuscation strategy is proposed, automatically configuring the comparator by extracting the process deviation to resist the side-channel attack. The proposed structure is implemented on a Xilinx Virtex-6 FPGA. Experimental results show that the proposed SDL PUF achieves 0 bit error rate in the temperature range of 0°C～80°C and the voltage range of 0.85～1.15V, and ensures 49.29% uniqueness and 49.84% uniformity while maintaining high reliability.
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Key words:
- Physical unclonable function /
- Self-timed ring /
- FPGA /
- Reliability
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