A Fault-Tolerant Design of Spaceborne Onboard Neural Network
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摘要: 为了满足高可靠星载在轨实时舰船目标检测的应用需求，该文针对基于神经网络的合成孔径雷达(SAR)舰船检测提出了一种容错加固设计方法。该方法以轻量级网络MobilenetV2为检测模型框架，对模型在现场可编程逻辑阵列(FPGA)的加速处理进行实现，基于空间单粒子翻转(SEU)对网络的错误模型进行分析，将并行化加速设计思想与高可靠三模冗余(TMR)思想进行融合，优化设计了基于动态重配置的部分三模容错架构。该容错架构通过多个粗粒度计算单元进行多图像同时处理，多单元表决进行单粒子翻转自检与恢复，经实际图像回放测试，FPGA实现的帧率能有效满足在轨实时处理需求。通过模拟单粒子翻转进行容错性能测试，相对原型网络该容错设计方法在资源消耗仅增加不到20%的情况下，抗单粒子翻转检测精度提升了8%以上，相较传统容错设计方式更适合星载在轨应用。Abstract: In order to meet the application requirements of high reliability on-orbit real-time ship target detection, a fault-tolerant reinforcement design for ship target detection based on neural network in Synthetic Aperture Radar (SAR) is proposed. The tiny network MobilenetV2 is used for detection model, which implements the pipeline process in the Field Programmable Gate Array (FPGA). The influence of Single Event Upset (SEU) model on the FPGA is analyzed, which combines the idea of parallelization acceleration and high reliability Triple Module Redundancy (TMR). In this way a partial triple redundancy architecture based on dynamic reconfiguration is designed. The fault-tolerant architecture employs multiple coarse-grained compute units to process multiple images at the same time and uses multi-unit voting to perform single-event flip self-inspection and recovery. The frame rate meets the real-time processing requirements after the real image playback test. By simulating single event upset test, this fault-tolerant design method can improve the detection accuracy of anti-single particle flip by more than 8% when the resource consumption is only increased by less than 20%, which is more suitable for on-orbit applications than the traditional fault-tolerant design method.
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表 1 加固设计前后资源对比
资源名称 加固前 加固后(TMR) 加固后(本文) Slice LUTs 270,897 721,584 302,240 DSP 1887 5661 1887 BRAM(36k) 965 2142 1153 
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表 4 Block单元各层结果出错统计
检测点 Block1 Block2 Block3 PW卷积1 5367 4615 7516 DW卷积 1565 2434 3193 PW卷积2 371 1120 849
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