Design of an Process In-Memory Full Adder Based on Voltage-Controlled Spin Orbit Torque Magnetic Random Access Memory
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摘要: 随着互补金属氧化物半导体技术的特征尺寸的不断缩小，其面临的静态功耗问题缩越来越突出。自旋磁随机存储器(MRAM)由于其非易失性、高速读写能力、高集成密度和CMOS兼容性等良好特性，受到了学术界的广泛关注和研究。该文采用电压调控的自旋轨道矩随机存储器设计了一个存内计算可重构逻辑阵列，能够实现全部布尔逻辑功能和高度并行计算。在此基础上设计了存内计算全加器并在40 nm工艺下进行了仿真验证。结果表明，与当前先进研究相比，该文提出的全加器具有更高的并行度，能够实现更快的计算速度(约1.11 ns/bit)和更低的计算功耗(约5.07 fJ/bit)。Abstract: With the feature size of complementary metal oxide semiconductor technology decreasing, the problem of static power consumption becomes more and more serious. Spin Magnetic Random Access Memory (MRAM) has been widely studied because of its nonvolatile, high-speed read-write ability, high integration density and CMOS compatibility. In this paper, a reconfigurable memory logic array is designed using a novel Voltage-Controlled Spin-Orbit Torque(VC-SOT) random access memory. It can implement all of Boolean Logic functions and highly parallel computing. On this basis, an in-memory computing Full Adder (FA) is designed and simulated in 40 nm process. The results show that the proposed full adder has higher parallelism, faster computation speed (～1.11 ns/bit) and lower computation power consumption (～5.07 fJ/bit).
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Key words:
- Full adder /
- Process In-Memory /
- Spin orbital torque /
- Magnetic tunnel junction /
- Reconfigurable
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表 1 VC-SOT MTJ模型的参数和变量
参数 描述 默认值 tOX (nm) 氧化层高度 1.50～2.50 tFL (nm) 自由层厚度 1.10 l,w,d (nm) 重金属尺寸 100, 100, 3 α 磁阻尼常数 0.02 TMR(0) 零偏置电压下的隧穿磁电阻比率 100％ 
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