波动动态差分逻辑RISC-V CPU芯核的功耗抑制技术研究

崔小乐; 李修远; 李浩; 张兴

doi:10.11999/JEIT230211

波动动态差分逻辑RISC-V CPU芯核的功耗抑制技术研究

doi: 10.11999/JEIT230211

崔小乐^{1, 2},
李修远¹,
李浩^{1, 2},
张兴^{1, 2, ,}

1.
北京大学深圳研究生院集成微系统重点实验室深圳 518055
2.
鹏城实验室深圳 518055

基金项目: 深圳学科布局项目(JCYJ20220818100814033)，深圳孔雀团队项目(KQTD20200820113105004)，广东省重点科技研发计划项目(2019B010155002)

详细信息

作者简介:
崔小乐：男，教授，研究方向为集成电路的可测性、可靠性和安全性

李修远：男，硕士生，研究方向为高安全RISC-V处理器设计

李浩：男，硕士生，研究方向为低功耗RISC-V处理器设计

张兴：男，教授，研究方向为集成电路的新器件、新结构、新工艺

通讯作者:
张兴　zhx@pku.edu.cn

中图分类号: TN918; TP332.2
计量
- 文章访问数: 322
- HTML全文浏览量: 356
- PDF下载量: 45
- 被引次数: 0
出版历程
- 收稿日期: 2023-04-23
- 修回日期: 2023-08-23
- 录用日期: 2023-08-24
- 网络出版日期: 2023-08-24
- 刊出日期: 2023-09-27

The Power Suppression Techniques for the DPA-resistant RISC-V CPU Core Based on WDDL

CUI Xiaole^{1, 2},
LI Xiuyuan¹,
LI Hao^{1, 2},
ZHANG Xing^{1, 2
, ,}

1.
Key Laboratory of Integrated Micro-systems, Peking University Shenzhen Graduate School, Shenzhen 518055, China
2.
Peng Cheng Laboratory, Shenzhen 518055, China

Funds: The Subject Layout Program of Shenzhen (JCYJ20220818100814033), The Peacock Plan of Shenzhen (KQTD20200820113105004), The Key-Area Research and Development Program of Guangdong Province (2019B010155002)

摘要

摘要: 差分功耗分析(DPA)攻击不仅威胁加密硬件，对加密软件的安全性也构成严重挑战。将波动动态差分逻辑(WDDL)技术应用在RISC-V指令集的处理器芯核上可减少功耗信息的泄露。但是，WDDL技术会给电路引入巨大的功耗开销。该文针对基于WDDL的RISC-V处理器芯核提出两种功耗抑制方法。虽然随机预充电使能技术与指令无关，而预充电使能指令技术需要扩充指令集，但这两种方法都是属于轻量级的设计改进。仿真结果表明，采用了随机预充电使能技术和预充电使能指令技术的Rocket 芯核的电路功耗分别是原始的WDDL Rocekt 芯核功耗的42%和36.4%。
- 差分功耗分析 /
- RISC-V 芯核 /
- 波动动态差分逻辑 /
- 功耗信息泄露 /
- 功耗抑制
Abstract: Differential Power Analysis (DPA) is a serious threat to cryptographic hardware and software. The RISC-V processor core based on Wave Dynamic Differential Logic (WDDL) is implemented to mitigate the power leakage. However, the WDDL technique results in a dramatic increase in circuit power. For WDDL-based RISC-V CPU cores, two power suppression techniques are proposed in the paper. Both of them are lightweight solutions. The simulation results show that the circuit power of the DPA-resistant Rocket core with the random precharge enabling technique and the precharge enabling instruction technique can be reduced to 42% and 36.4% of that of the original WDDL based counterpart, respectively.
- Differential Power Analysis (DPA) /
- RISC-V core /
- Wava Dynamic Differential Logic (WDDL) /
- Power leakage /
- Power suppression

HTML全文

图 1 标准CMOS电路与WDDL电路单元对比

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图 2 密码程序的汇编指令比例分析

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图 3 sw-Rocket芯核的面积开销

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图 4 随机预充电使能发生器电路结构示意图

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图 5 PRNG电路示意图

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图 6 预充电逻辑单元电路结构

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图 7 预充电使能指令通过CSR Reg_enPre控制预充电

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图 8 功能仿真及功耗分析流程

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图 9 AES-128程序运行在不同的Rocket芯核上ALU模块部分功耗迹线

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表 1 不同程序的功耗比较(mW)

	sc-Rocket		sw-Rocket
	Rocket	ALU	Rocket	ALU
Helloworld	1.55	0.04	5.60(×3.6)	4.09(×102.3)
DES	2.16	0.13	6.14(×2.8)	4.12(×31.6)
AES	1.94	0.11	5.93(×3.1)	4.11(×37.4)
RSA	1.72	0.05	5.77(×3.4)	4.09(×81.8)

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表 2 随机预充电发生器的面积和功耗开销

N_C	P_C	面积(μm²)			功耗(μW)
N_C	P_C	Divider	PRNG	Generator	Generator
8	2	33.1	270.4	346.7	26.6
8	6	33.1	354.6	436.7	27.7
16	5	46.4	271.0	372.2	31.3
	8	46.4	400.0	517.3	31.4
	16	46.4	451.8	579.2	31.7
32	5	58.7	272.0	398.2	35.8
	10	58.7	453.2	597.6	35.6
	16	58.7	453.6	604.8	35.7
	30	58.7	465.5	615.9	36.3
64	6	71.6	356.8	519.8	40.6
	8	71.6	402.5	571.0	40.6
	16	71.6	457.2	632.9	40.8
	30	71.6	466.9	642.6	40.9
	64	71.6	520.6	709.6	41.0

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表 3 不同Rocket核心的面积开销(μm²)

	sc-Rocket	sw-Rocket	rw-Rocket	iw-Rocket
Rocket	74644.2	85620.6	86020.9	86252.8
ALU	4063.0	15039.4	15439.7	15010.9
CSRFile	15794.3	15794.3	15794.3	16426.1

下载: 导出CSV

表 4 不同Rocket核心运行AES-128程序的功耗开销(mW)

	sw-Rocket	rw-Rocket	iw-Rocket
Rocket	5.93	2.49	2.16
ALU	4.11	0.67	0.33
CSRFile	0.24	0.24	0.26

下载: 导出CSV

参考文献(21)

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