基于与异或非图的混合粒度可重构密码运算单元设计

戴紫彬; 张宗仁; 刘燕江; 周朝旭; 蒋丹萍

doi:10.11999/JEIT230021

基于与异或非图的混合粒度可重构密码运算单元设计

doi: 10.11999/JEIT230021

戴紫彬¹,
张宗仁^{1, 2, ,},
刘燕江¹,
周朝旭¹,
蒋丹萍¹

1.
解放军信息工程大学郑州 450000
2.
31642部队临沧 677000

基金项目: 核高基国家科技重大专项(2018ZX01027101-004)

详细信息

作者简介:
戴紫彬：男，博士、教授、博士生导师，研究方向为信息安全、体系结构等

张宗仁：男，硕士生，研究方向为安全专用芯片设计、可重构计算

刘燕江：男，博士，研究方向为安全专用芯片设计、侧信道攻击等

周朝旭：男，博士生，研究方向为安全专用芯片设计、可重构计算

蒋丹萍：女，博士生，研究方向为信息安全、安全专用芯片设计、可重构计算

通讯作者:
张宗仁　zzr20200901@163.com

中图分类号: TN492; TP309.7
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- 被引次数: 0
出版历程
- 收稿日期: 2023-01-16
- 修回日期: 2023-04-13
- 网络出版日期: 2023-04-27
- 刊出日期: 2023-09-27

Design of Hybrid-granularity Multifunctional Computing Unit Based on And-Xor-Inv Graph

1.
School of Cryptography, Information Engineering University, Zhengzhou 450000, China
2.
Unit 31642 of PLA, Lincang 677000, China

Funds: National Science and Technology Major Project of China (2018ZX01027101-004)

摘要

摘要: 粗粒度可重构密码逻辑阵列(CGRCA)难以兼容细粒度序列密码算法，且在编码环节功能单元容易出现竞争冲突，进而导致阵列的资源利用率低和延迟大等问题。为此，利用与-异或-非图(AXIG)双逻辑表达的优势，该文提出一种混合粒度的可重构的多功能密码运算单元，并在晶体管级进行了实现验证，可兼容现有序列密码算法中非线性布尔函数，在延迟和面积-延迟积(ADP)方面均有提升。设计了可重构与、异或、与非(RAXN)逻辑元件，可同时重构“And, Xor, Nand”等逻辑功能，并提出了RAXN的晶体管级实现方法和版图结构；提出了基于RAXN的功能扩展方法，实现了全加器功能、与/异或3输入逻辑功能以及乘法部分积生成功能，并作为基本功能单元(RAXN_U)；结合动态配置和动态调度的思想，利用阵列中互联资源和RAXN_U，设计一种可同时实现32 bit加法、8 bit乘法、CF(2⁸)有限域乘法，以及包括S盒在内的复杂非线性布尔函数的混合粒度多功能密码运算单元(RHMCA)。在CMOS 40 nm工艺进行后端定制化设计，实验结果表明，该文提出的多功能单元较传统的实现方法，延迟最好情况优化1.27 ns，面积-延迟积(ADP)值最大提升44.8%。
- 密码运算单元 /
- 多功能可重构 /
- 混合粒度 /
- 与-异或-非图
Abstract: Recently, the majority of fine-grained sequence-coding algorithms are not applied to the existing Coarse-Grained ReConfigurable Arrays (CGRCA). Moreover, competition conflicts often occur in the encoding stages, which causes low resource utilization and high latency for CGRCA. To address this issue, a Hybrid-grained Reconfigurable Multifunctional Cryptographic Arithmetic unit (RHMCA) at transistor-level is proposed in this paper, which can be compatible with non-linear Boolean functions in existing stream cryptography algorithms with improved performance metrics. More specifically, a Reconfigurable And-Xor-Nand (RAXN) logic element based on the And-Xor-Inv Graph (AXIG) logic is designed, which can reconfigure the several logic functions (including the And, Xor, and Nand). A transistor-level implementation and layout structure of RAXN is proposed to reduce the delay overhead; A functional extension method of RAXN is proposed in this paper and a basic functional Unit (RAXN_U) is proposed to realize full adder, three-input And/Xor logic, and multiplier partial product generation functions; A hybrid-grained RHMCA is designed by combining the interconnect resources and RAXN_Us in the array, which can implement 32 bit addition, 8 bit multiplication, CF(2⁸) finite field multiplication, and complex nonlinear Boolean functions. The proposed design is validated with the CMOS 40 nm technology, and the results show that the proposed design reduces 1.27 ns delay and decreases 44.8% Area-Delay Product (ADP) value compared to the existing approaches.
- Cryptographic operation unit /
- Multifunctional reconfiguration /
- Mixed granularity /
- And-Xor-Inv Graph (AXIG)

HTML全文

图 1 RAXN晶体管级实现

下载: 全尺寸图片幻灯片

图 2 RAXN的版图设计

下载: 全尺寸图片幻灯片

图 3 “与-异或-与非锥”3级深度的互联结构

下载: 全尺寸图片幻灯片

图 4 混合粒度多功能密码运算单元

下载: 全尺寸图片幻灯片

图 5 RAXN_U电路结构

下载: 全尺寸图片幻灯片

图 6 单元扩展与拆分示意图

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图 7 32 bit模乘计算过程

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图 8 各功能模式下的延迟情况

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图 9 不同功能模式下性能和资源占用对比

下载: 全尺寸图片幻灯片

表 1 RAXN电路信号传输路径分析

M	A	B	C	信号路径	M	A	B	C	信号路径
0	A	0	0	F=1	1	A	0	0	F=0
		0	1	F=1			0	1	N5→N2→P9→F/ P5→N7→F
		1	0	F=1			1	0	N1→P9→F/ P2→P4→N7→F
		1	1	P6→P10(P9)→F / N10→N8→N6→F			1	1	P6→P9→F/ N10→N8→N6→F
	0	B	0	F=1		0	B	0	F=0
	0		1	F=1		0		1	N4→N2→P9→F/ P3→P5→N7→F
	1		0	F=1		1		0	N3→N1→P9→F/ P1→P4→N7→F
	1		1	P7→P10(P9)→F/N8→N6→F		1		1	P7→P9→F/ N8→N6→F
	0	0	C	F=1		0	0	C	F=0
	0	1		F=1		0	1		N2→P9→F/ P4→N7→F
	1	0		F=1		1	0		N2→P9→F/ P4→N7→F
	1	1		P8→ P10(P9)→F / N6→F		1	1		P8→P9→F/ N6→F

下载: 导出CSV

表 2 两种方式实现下延迟和面积

	延迟(ns)				总面积(μm²)
	8 bit乘法	Xtime	8 bit加法	NLBF	总面积(μm²)
CMOS标准单元实现	1.580	1.260	0.460	1.440	3634.57
定制优化	1.076	0.571	0.391	0.589	1512.12

下载: 导出CSV

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