Efficiency Optimized Design of Active Neutral Point Clamped Inverter Based on Deep Reinforcement Learning
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摘要: 传统电力电子变换器设计多采用顺序设计法，依赖人工经验。近年来，电力电子自动化设计可通过计算机快速优化设计电力电子系统而备受关注。该文以有源中点钳位(ANPC)逆变器的效率优化设计为例，提出一种基于深度强化学习(DRL)的电力电子自动化设计方法，可实现在变换器设计需求变化时，根据设计目标快速得到最优的设计参数。首先介绍了基于DRL的逆变器效率优化整体框架；然后建立了逆变器的效率模型；接着通过深度确定性策略梯度(DDPG)算法的自学习不断训练智能体，获得了最小化功率损耗的优化策略，该策略能够快速响应设计规格变化提供最大化效率的设计变量；最后，搭建了140 kW的实验样机，实验结果验证了所提方法的有效性，相比于遗传算法和强化学习(RL)，实测效率分别提高了0.025 %和0.025 %。Abstract: The traditional power electronic converter design adopts mostly the sequential design method, which relies on manual experience. In recent years, power electronics automation design has attracted much attention by optimizing rapidly the design of power electronic systems with computers. Taking the efficiency optimized design of Active Neutral Point Clamped (ANPC) inverter as an example, a power electronics automation design method based on Deep Reinforcement Learning (DRL) is proposed, which can realize quickly to obtain the optimal design parameters according to the design objectives when the design requirements of converter change. Firstly, the overall framework of inverter efficiency optimization based on DRL is introduced; Then the efficiency model of the inverter is established; After that the agent is continuously trained through the self-learning of the Deep Deterministic Policy Gradient (DDPG) algorithm, and an optimization strategy that minimizes power loss is obtained; The strategy can quickly respond to design specification changes and provide design variables that maximize efficiency; Finally, a 140 kW experimental prototype is built, and the effectiveness of the proposed method is verified by the experimental results, which demonstrates efficiency improvements of 0.025 % and 0.025 % respectively compared to genetic algorithm and Reinforcement Learning (RL).
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表 1 三相三电平ANPC逆变器的系统规格
参数 数值 额定功率Prated(kW) 140 直流侧输入电压UDC(V) 1 200 直流侧支撑电容CDC(μF) 20 滤波电容CAC(μF) 3 调制度m 0.9 功率因数λ 1 
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表 2 DDPG算法的关键参数
变量 取值 超参数 数值 UDC(V) 1000～1200 奖励系数ϕ 1 I(A) 100～120 经验回放池容量 40000 fsw(kHz) 10～100 小批量数目N 32
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表 3 不同状态下的开关频率优化结果对比
状态 UDC(V) I(A) fsw(kHz) 遍历法 遗传算法 RL DRL S1 1000 100 25.7 36.5 30.5 22.9 S2 1200 100 22.0 37.0 29.8 27.1 S3 1100 110 24.1 37.6 31.4 25.2 S4 1000 120 27.2 36.8 33.7 23.2 S5 1200 120 23.3 38.2 32.5 27.5
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表 4 I = 30 A时，相比于遍历法，其他优化方法的各部分功率损耗对比
UDC(V) 方法 Pcond(W) Psw(W) Pg(W) Pcop(W) Pcore(W) 误差百分比平均值(%) 400 遍历法 111.73 27.98 4.95 36.35 12.44 – 遗传算法 111.89 33.97 4.92 31.22 12.45 7.27 RL 111.47 18.81 4.99 51.31 12.70 15.41 DRL 111.58 22.76 4.97 43.34 12.47 7.73 500 遍历法 111.66 32.17 4.96 42.78 15.35 – 遗传算法 111.91 43.05 4.92 34.49 15.15 11.11 RL 111.52 25.97 4.98 51.60 15.05 8.47 DRL 111.58 28.57 4.97 47.63 15.09 4.90 600 遍历法 111.60 35.52 4.97 50.24 17.80 – 遗传算法 111.88 50.12 4.92 38.75 17.97 13.24 RL 111.48 28.92 4.99 59.64 17.68 7.70 DRL 111.69 39.93 4.95 46.14 17.73 4.29
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表 5 实验样机的测试条件
测试条件 输入功率
Pin(kW)直流侧输入电压
UDC(V)负载电阻
RL(Ω)开关频率fsw(kHz) 遍历法 遗传算法 RL DRL P1 7.0 400 6.5 30.6 35.2 21.8 25.0 P2 8.8 450 6.5 29.6 36.3 22.5 27.1 P3 11.0 500 6.5 28.1 36.7 23.1 29.2 P4 13.1 550 6.5 26.8 36.4 22.4 31.3
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