基于脉冲跨周期调制的DC-DC变换器自适应电压调节技术

王东俊; 罗萍; 彭宣霖; 甄少伟; 贺雅娟

doi:10.11999/JEIT160283

基于脉冲跨周期调制的DC-DC变换器自适应电压调节技术

doi: 10.11999/JEIT160283

基金项目:

国家自然科学基金(61274027)，国家自然科学基金青年基金(61404025)

计量
- 文章访问数: 1370
- HTML全文浏览量: 165
- PDF下载量: 343
- 被引次数: 0
出版历程
- 收稿日期: 2016-03-28
- 修回日期: 2016-08-30
- 刊出日期: 2017-01-19

Adaptive Voltage Scaling Technique for DC-DC Converter Based on Pulse Skip Modulation

Funds:

The National Natural Science Foundation of China (61274027), The National Natural Science Youth Foundation of China (61404025)

摘要

摘要: 为实现减小数字电路的供电电压来降低其能量消耗的目的，该文提出基于脉冲跨周期调制(PSM)的DC-DC变换器自适应电压调节(AVS)技术。AVS技术通过追踪和探测关键路径复制(CPR)的延迟时间自适应地调节数字电路的供电电压。同时，具有自适应占空比的PSM调制模式(APSM)被用来改善轻负载下变换器输出电压的纹波和效率。实验结果显示，当负载工作频率在30～150 MHz范围内变化时，输出电压在0.6～1.5 V之间稳定输出。和传统的固定工作电压相比，该文设计的DC-DC变换器最大可节省83%的能耗。
- DC-DC变换器 /
- 自适应电压调节 /
- 脉冲跨周期调制 /
- 关键路径复制 /
- 自适应占空比
Abstract: In order to decrease energy consumption of digital circuits by reducing the supply voltage, an Adaptive Voltage Scaling (AVS) for DC-DC converter based on Pulse Skip Modulation (PSM) is proposed. The AVS technique can scale supply voltage adaptively by probing and tracking the Critical Path Replica (CPR) delay time. To improve the output voltage ripple and efficiency of converter especially in light load, the PSM with Adaptive ratio duty (APSM) also is used. The experimental results show that the output voltage is well regulated from 0.6~ 1.5 V when the operation frequency of load varies within the range of 30~150 MHz. The maximum energy saving of 83% is obtained with the proposed converter compared to the traditional fixed voltage.
- DC-DC converter /
- Adaptive Voltage Scaling (AVS) /
- Pulse Skip Modulation (PSM) /
- Critical Path Replica (CPR) /
- Adaptive duty ratio

HTML全文

参考文献(23)

KONIJNENBURG M, STANZIONE S, YAN L,?et al. A battery-powered efficient multi-sensor acquisition system with simultaneous ECG, BIO-Z, GSR, and PPG[C]. IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, 2016: 480-481.

DINI Michele, ROMANI Aldo, FILIPPI Mtteo, et al. A nanocurrent power management IC for low-voltage energy harvesting sources[J]. IEEE Transactions on Power Electronics, 2016, 31(6): 4292-4304.

JOSE Luis and NUNEZ Yanez. Adaptive voltage scaling with in-situ detectors in commercial FPGAs[J]. IEEE Transactions on Computers, 2015, 64(1): 45-53. doi: 10.1109/ TC.2014.2365963.

DANCY A P, AMIRTHARAJAH R, and CHANDRAKASAN A P. High-efficiency multiple-output DC-DC conversion for low-voltage systems[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, 8(3): 252-263. doi: 10.1109/92.845892.

ZHEN Shaowei, LUO Ping, and ZHANG Bo. Design of highly integrated power management unit with dual DVS-enabled regulators[J]. Analog Integrated Circuits and Signal Processing, 2014, 80: 209-220. doi: 10.1007/s10470-014-0313- 1.

WIRNSHOFER M, HEI L, GEORGAKOS G, et al. A variation-aware adaptive voltage scaling technique based on in-siut delay monitoring[C]. IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS), Cottbus, Germany, 2011: 261-266.

LUO Ping, FU Songlin, ZHANG Xiang, et al. An adaptive voltage scaling circuits based on dominate pole compensation [C]. Processing 11th IEEE International Conference on ASIC, Chengdu, China, 2015: 1-4.

CHO M, KIM S, TOKUNAGA C,?et al. Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating [C].?IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, 2016: 152-153.

ELGEBALY M and SACHDEV M. Variation-aware adaptive voltage scaling system[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007, 15(5): 560-571. doi: 10.1109/TVLSI.2007.896909.

IKENAGA Y, NOMURA M, SUENAGA S, et al. A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines[J]. IEEE Journal of Solid-State Circuits, 2012, 47(4): 832-840. doi: 10.1109/JSSC.2012.2185340.

KAPAT S, BANERJEE S, and PATRA A. Discontinuous map analysis of a DC-DC converter governed by pulse skipping modulation[J]. IEEE Transactions on Circuits and System I, 2010, 57(7): 1793-1801. doi: 10.1109/TCSI.2009. 2034888.

LIOU W R, YEH M L, and KUO Y L. A high efficiency Dual-Mode buck converter IC for portable applications[J]. IEEE Transactions on Power Electronics, 2008, 23(2): 667-677. doi: 101109/TPEL.2007.915047.

LUO Ping, LI Zhaoji, and ZHANG Bo. A novel improved PSM model in DCDC converter based on energy balance[C]. 37th IEEE Power Electronics Specialists Conference, Jeju, South Korea, 2006: 1-4.

KAPAT S, MANDI B C, and PATRA A. Voltage-mode digital pulse skipping control of a DC-DC converter with stable periodic behavior and improved light-load efficiency[J]. IEEE Transactions on Power Electronics, 2016, 31(4): 3372-3379. doi: 10.1109/TPEL.2015.2455553.

罗萍, 李肇基, 熊富贵, 等. 开关变换器的跨周期调制模式[J]. 电子与信息学报, 2004, 26(6): 984-988.

LUO Ping, LI Zhaoji, XIONG Fugui, et al. Pulse-cycle skip modulation in switching converter[J]. Journal of Electronics Information Technology, 2004, 26(6): 984-988.

牛全民, 罗萍, 李肇基, 等. Boost 变换器跨周期调制(PSM)的状态空间平均模型[J]. 电子与信息学报, 2006, 28(10): 1955-1958.

NIU Quanmin, LUO Ping, LI Zhaoji, et al. Space state average model of PSM in boost converter[J]. Journal of Electronics Information Technology, 2006, 28(10): 1955-1958.

李航标, 张波, 罗萍, 等. 开关DC-DC变换器的自适应占空比跨周期控制方法[J]. 电子与信息学报, 2014, 36(9): 2265-2271. doi: 10.3724/SP.J.1146.2013.01693.

LI Hangbiao, ZHANG Bo, LUO Ping, et al. Pulse skip with adaptive duty ratio control technique for switching DC-DC converter[J]. Journal of Electronics Information Technology, 2014, 36(9): 2265-2271. doi: 10.3724/SP.J.1146. 2013.01693.

LI Hangbiao, ZHANG Bo, LUO Ping, et al. Adaptive duty ratio modulation technique in switching DC-DC converter operating in discontinuous conduction mode[J]. Analog Integrated Circuits and Signal Processing, 2014, 78(2): 361-371. doi: 10.1007/s10470-015-0603-2.

WEI G Y and HOROWITZ M. A fully digital energy-efficient adaptive power supply regulator[J]. IEEE Journal of Solid-State Circuits, 1999, 34(4): 520-528. doi: 10.1109/ 4.753685.

CALHOUN B H, WANG A, and CHANDRAKASAN A. Model and sizing for minimum energy operation in subthreshold circuits[J]. IEEE Journal of Solid-State Circuits, 2005, 40(9): 1778-1786. doi: 10.1109/JSSC.2005.852162.

施引文献

资源附件(0)

访问统计