高级搜索

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

面向密码流体系结构的超长指令字可重构研究

严迎建 王寿成 徐进辉 陈韬

严迎建, 王寿成, 徐进辉, 陈韬. 面向密码流体系结构的超长指令字可重构研究[J]. 电子与信息学报, 2017, 39(1): 206-212. doi: 10.11999/JEIT160213
引用本文: 严迎建, 王寿成, 徐进辉, 陈韬. 面向密码流体系结构的超长指令字可重构研究[J]. 电子与信息学报, 2017, 39(1): 206-212. doi: 10.11999/JEIT160213
YAN Yingjian, WANG Shoucheng, XU Jinhui, CHEN Tao. Research of Reconfigurable Very Large Instruction Word on Cipher Stream Architecture[J]. Journal of Electronics & Information Technology, 2017, 39(1): 206-212. doi: 10.11999/JEIT160213
Citation: YAN Yingjian, WANG Shoucheng, XU Jinhui, CHEN Tao. Research of Reconfigurable Very Large Instruction Word on Cipher Stream Architecture[J]. Journal of Electronics & Information Technology, 2017, 39(1): 206-212. doi: 10.11999/JEIT160213

面向密码流体系结构的超长指令字可重构研究

doi: 10.11999/JEIT160213
基金项目: 

国家863计划项目(2009AA012201),国家自然科学基金(61302107)

Research of Reconfigurable Very Large Instruction Word on Cipher Stream Architecture

Funds: 

The National 863 Project of China (2009AA 012201), The National Natural Science Foundation of China (61302107)

  • 摘要: 可重构密码流体系结构是一种面向密码运算的新型体系结构,但存在着超长指令字(VLIW)代码稀疏和Kernel体积过大的问题。该文以可重构密码流处理架构S-RCCPA为研究平台,通过大量密码算法在S-RCCPA架构上的适配分析,提出了VLIW可重构技术,并设计了Kernel级指令集、VLIW可重构算法及指令可重构单元。实验证明,该技术能够有效提高VLIW的指令密度,同时降低了VLIW的指令宽度,使得整个Kernel体积减小了约33.3%,并将微码存储器的容量由96 kB降为64 kB,有效降低芯片整体面积和系统功耗。
  • 陈韬, 罗兴国, 李校南, 等. 一种基于流处理框架的可重构分簇式分组密码处理结构模型[J]. 电子与信息学报, 2014, 36(12): 3027-3034. doi: 10.3724/SP.J.1146.2014.00023.
    CHEN Tao, LUO Xingguo, LI Xiaonan, et al. An architecture of stream based reconfigurable clustered block cipher processing array[J]. Journal of Electronics Information Technology, 2014, 36(12): 3027-3034. doi: 10.3724/SP.J.1146. 2014.00023.
    LEE K Y, KYUNG G, PARK T R, et al. A design of a GP-GPU based stream processor for an image processing[C]. IEEE International Conference on Telecommunications Signal Processing, Prague, Czech Republic, 2015: 535-539.
    CHENG Tengyuan, CHEN Tsunghuang, CHEN J C, et al. Coarse-grained reconfigurable image stream processor architecture for high-definition cameras and camcorders[C]. IEEE International SoC Design Conference, Incheon, South Korea, 2010: 95-98.
    KRIMER E, PAWLOWSKI R, EREZ M, et al. Synctium: A near-threshold stream processor for energy-constrained parallel applications[J]. IEEE Computer Architecture Letters, 2010, 9(1): 21-24. doi: 10.1109/L-CA.2010.5.
    李校南, 王雪瑞, 戴紫彬, 等. 可重构分簇式分组密码处理架构[J]. 计算机应用与软件, 2014, 31(1): 315-318. doi: 10.3969 /j.issn.1000-386x.2014.01.085.
    LI Xiaonan, WANG Xuerui, DAI Zibin, et al. Reconfigurable clustered block cipher processing architecture[J]. Computer Applications and Software, 2014, 31(1): 315-318. doi: 10.3969 /j.issn.1000-386x.2014.01.085.
    HUANG Wei, HAN Jun, WANG Shuai, et al. A low- complexity heterogeneous multi-core platform for security SoC[C]. IEEE Asian Solid-State Circuits Conference, Beijing, China, 2010: 126-129.
    WANG Bo and LIU Leibo. A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing [C]. IEEE International Symposium on Circuits and Systems, Lisbon, Portugal, 2015: 1182-1185.
    SAYILAR G and CHIOU D. Cryptoraptor: high throughput reconfigurable cryptographic processor[C]. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, USA, 2014: 155-161.
    管茂林, 何义, 杨乾明, 等. 流体系结构指令存储器优化设计研究[J]. 电子学报, 2012, 40(7): 1379-1385. doi: 10.3969/ j.issn.0372-2112.2012.07.016.
    GUAN Maolin, HE Yi, YANG Qianming, et al. Optimized design research of instruction memory for stream architecture[J]. Acta Electronica Sinica, 2012, 40(7): 1379-1385. doi: 10.3969/j.issn.0372-2112.2012.07.016.
    HELKALA J, VIITANEN T, KULTALA H, et al. Variable length instruction compression on transport triggered architectures[C]. IEEE International Conference on Embedded Computer Systems: Architectures, Modeling Simulation, Samos Island, Greece, 2014: 149-155.
    JIN T, AHN M, YOO D, et al. NOP compression scheme for high speed DSPs based on VLIW architecture[C]. IEEE International Conference on Consumer Electronics, Las Vegas, Nevada, USA, 2014: 304-305.
    HE Yi, GUAN Maolin, ZHANG Chunyuan, et al. Fully distributed on-chip intruction memory design for stream architecture based on field-divided VLIW compression[C]. IEEE 14th International Conference on High Performance Computing and Communications, Liverpool, United Kingdom, 2012: 25-32.
    CHUNG Mookyoung, KIM Junkyoung, CHO Yeongon, et al. Adaptive compression for instruction code of coarse grained reconfigurable architectures[C]. IEEE International Conference on Field-programmable Technology, Kyoto, Japan, 2013: 394-397.
    李勇, 王志英, 赵学秘, 等. 配置流驱动计算体系结构指导下的ASIP设计[J]. 计算机研究与发展, 2007, 44(4): 714-721.
    LI Yong, WANG Zhiying, ZHAO Xuemi, et al. Design of application specific instruction-set processors directed by configuration stream driven computing architecture[J]. Journal of Computer Research and Development, 2007, 44(4): 714-721.
    BUCHOLC K, CHMIEL K, GROCHOLEWSKA C A, et al. PP-2 block cipher[C]. International Conference on Emerging Security Information, Systems and Technologies, Barcelona, Spain, 2013: 162-168.
  • 加载中
计量
  • 文章访问数:  1279
  • HTML全文浏览量:  121
  • PDF下载量:  307
  • 被引次数: 0
出版历程
  • 收稿日期:  2016-03-07
  • 修回日期:  2016-07-22
  • 刊出日期:  2017-01-19

目录

    /

    返回文章
    返回