一种-100 dB电源抑制比的非带隙基准电压源

黄国城; 尹韬; 朱渊明; 许晓冬; 张亚朝; 杨海钢

doi:10.11999/JEIT151256

一种-100 dB电源抑制比的非带隙基准电压源

doi: 10.11999/JEIT151256

2.
(中国科学院电子学研究所北京 100190) ②(中国科学院大学北京 100190)

基金项目:

国家自然科学基金(61474120)，国家重点基础研究发展计划(2014CB744600)

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- 被引次数: 0
出版历程
- 收稿日期: 2015-11-09
- 修回日期: 2016-03-25
- 刊出日期: 2016-08-19

A -100 dB Power Supply Rejection Ratio Non-bandgap Voltage Reference

Funds:

The National Natural Science Foundation of China (61474120), The National Key Basic Research Program of China (2014CB744600)

摘要

摘要: 该文提出一种非带隙基准电路，通过一个带超级源极跟随器的预调制电路提供一个稳定的电压，为基准核心电路供电。超级源极跟随器通过降低基准核心电路电源端的对地阻抗，有效提高了基准电路的电源抑制能力。该基准电路采用0.35 m CMOS 工艺设计并流片，测试结果表明，该电路的工作电源电压为1.8~5 V，静态电流约为13 A。低频处电源抑制比(PSRR)约等于-100 dB，在小于1 kHz频率范围内PSRR均优于-93 dB。并且其片上面积仅为0.013 mm2。
- CMOS基准电路 /
- 非带隙基准电路 /
- 预调制电路 /
- 超级源极跟随器 /
- 电源抑制比
Abstract: This paper presents a non-bandgap voltage reference, which contains a pre-regulated circuit with a super source follower. The pre-regulated circuit includes a super source follower, which attenuates the impedance from the supply of the core reference circuit to ground. In this way, the pre-regulated circuit provides a relative stable voltage for the core reference circuit, improving the Power Supply Rejection Ratio (PSRR) of the output voltage of the reference. The proposed reference circuit is implemented in standard 0.35 m CMOS process. Measured results show that the supply range is from 1.8 to 5 V and the quiescent current is only about 13 A at room temperature. The PSRR at low frequency achieves -100 dB and the PSRR below 1 kHz is better than -93 dB. The active area of the proposed reference is only 0.013 mm2.
- CMOS reference circuit /
- Non-bandgap reference circuit /
- Pre-regulated circuit /
- Super source follower /
- Power Supply Rejection Ratio (PSRR)

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参考文献(18)

GRAY P R, HURST P, MEYER R G, et al. Analysis and Design of Analog Integrated Circuits[M]. New Jersey, USA. Wiley, 1990: 201-300.

ZHU Y, LIU F, YANG Y, et al. A -115 dB PSRR CMOS bandgap reference with a novel voltage self-regulating technique[C]. 2014 IEEE Proceedings of the Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2014: 1-4. doi: 10.1109/CICC.2014.6946006.

BASYURT P B and AKSIN D Y. A compact curvature corrected bandgap reference in 0.35m CMOS process[J]. Analog Integrated Circuits and Signal Processing, 2015, 83(1): 65-73. doi: 10.1007/s10470-015-0503-5.

WANG B, LAW M K, and BERMAK A. A precision CMOS voltage reference exploiting silicon bandgap narrowing effect [J]. IEEE Transactions on Electron Devices, 2015, 62(7): 2128-2135. doi: 10.1109/TED.2015.2434495.

CHAHARDORI M, ATARODI M, and SHARIFKHANI M. A sub 1V high PSRR CMOS bandgap voltage reference[J]. Microelectronics Journal, 2011, 42(9): 1057-1065. doi: 10.1016/j.mejo.2011.06.010.

CAI C, SONG S X, LUO Y, et al. A high accuracy low-power bandgap voltage reference with trimming[C]. 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China. 2014: 1-4. doi: 10.1109/ICSICT.2014.7021565.

LAM Y H and KI W H. CMOS bandgap references with self- biased symmetrically matched currentvoltage mirror and extension of sub-1-V design[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(6): 857-865. doi: 10.1109/TVLSI.2009.2016204.

COLOMBO D M, WIRTH G, and BAMPI S. Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13m CMOS[J]. Analog Integrated Circuits and Signal Processing, 2015, 82(1): 25-37. doi: 10.1007/ s10470-014-0343-8.

LEUNG K N and MOK P K T. A CMOS voltage reference based on weighted VGS for CMOS low-dropout linear regulators[J]. IEEE Journal of Solid-State Circuits, 2003, 38(1): 146-150. doi: 10.1109/JSSC.2002.806265.

CAJUEIRO J P C. Tracking-Vgs: a temperature compensation technique to implement all-MOS reference voltages[C]. Proceedings of the 6th International Caribbean Conference on Devices, Circuits and Systems, Playa del Carmen, Mxico, 2006: 287-291. doi: 10.1109/ICCDCS.2006.250875.

CHANG S I, ALASHMOUNY K, and YOON E. A 1.5 V 120 nW CMOS programmable monolithic reference generator for wireless implantable system[C]. 2011 Annual International Conference of the Engineering in Medicine and Biology Society (EMBC), Boston, MA, USA, 2011: 2981-2984. doi: 10.1109/IEMBS.2011.6090818.

ZHOU Z, ZHU P, SHI Y, et al. A resistorless CMOS voltage reference based on mutual compensation of VT and VTH[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2013, 60(9): 582-586. doi: 10.1109/TCSII.2013. 2268639.

CHOUHAN S S and HALONEN K. Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of Vgs[J]. Microelectronics Journal, 2015, 46(1): 36-42. doi: 10.1016/j.mejo.2014.09.015.

CHOUHAN S S and HALONEN K. Design and implementation of all MOS micro-power voltage reference circuit[J]. Analog Integrated Circuits and Signal Processing, 2014, 80(3): 399-406. doi: 10.1007/s10470-014-0361-6.

CHOUHAN S S and HALONEN K. A simple all MOS voltage reference for RFID applications[C]. 2013 IEEE NORCHIP Conference, Vilnius, Lithuania, 2013: 1-3. doi: 10.1109/NORCHIP.2013.6702027.

ROH H D, ROH J, and DUAN D Q Z. All mos transistors bandgap reference using chopper stabilization technique[C]. 2010 International SoC Design Conference (ISOCC), Incheon, South Korea, 2010: 353-357. doi: 10.1109/SOCDC.2010. 5682897.

TAN X L, CHONG S S, CHAN P K, et al. A LDO regulator with weighted current feedback technique for 0.47 nF-10 nF capacitive load[J]. IEEE Journal of Solid-State Circuits, 2014, 49(11): 2658-2672. doi: 10.1109/JSSC.2014.2346762.

FILANOVSKY I M and ALLAM A. Mutual compensation of mobility and threshold voltage temperature effects with application in CMOS circuits[J]. IEEE Journal of Solid-State Circuits, 2001, 48(7): 876-884. doi: 10.1109/81.933328.

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