一种基于与非锥簇架构FPGA输入交叉互连设计优化方法

黄志洪; 李威; 杨立群; 江政泓; 魏星; 林郁; 杨海钢

doi:10.11999/JEIT151216

一种基于与非锥簇架构FPGA输入交叉互连设计优化方法

doi: 10.11999/JEIT151216

2.
(中国科学院电子学研究所北京 100190) ②(中国科学院大学北京 100190)

基金项目:

国家自然科学基金(61271149)

计量
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- 被引次数: 0
出版历程
- 收稿日期: 2015-10-28
- 修回日期: 2016-03-04
- 刊出日期: 2016-09-19

An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA

2.
(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds:

The National Natural Science Foundation of China (61271149)

摘要

摘要: 该文针对与非锥(And-Inverter Cone, AIC)簇架构FPGA开发中面临的簇面积过大的瓶颈问题，对其输入交叉互连设计优化进行深入研究，在评估优化流程层次，首次创新性提出装箱网表统计法对AIC簇输入和反馈资源占用情况进行分析，为设计及优化输入交叉互连结构提供指导，以更高效获得优化参数。针对输入交叉互连模块，在结构参数设计层次，首次提出将引脚输入和输出反馈连通率分离独立设计，并通过大量的实验，获得最优连通率组合。在电路设计实现层次，有效利用AIC逻辑锥电路结构特点，首次提出双相输入交叉互连电路实现。相比于已有的AIC簇结构，通过该文提出的优化方法所得的AIC簇自身面积可减小21.21%，面积制约问题得到了明显改善。在实现MCNC和VTR应用电路集时，与Altera公司的FPGA芯片Stratix IV(LUT架构)相比，采用具有该文所设计的输入交叉互连结构的AIC架构FPGA，平均面积延时积分别减小了48.49%和26.29%；与传统AIC架构FPGA相比，平均面积延时积分别减小了28.48%和28.37%，显著提升了FPGA的整体性能。
- 与非锥(AIC); AIC簇 /
- 装箱网表统计法 /
- 连通率 /
- 分类独立设计 /
- 双相输入交叉互连
Abstract: In order to break through the bottleneck of the huge cluster area in AIC (And-Inverter Cone) architecture based FPGA, the research on the optimisation of the input crossbar architecture is carried on. A post-pack netlist statistics method is creatively proposed to analyze the utilization of AIC cluster inputs and feedbacks and to guide the input crossbar design. And on the architecture parameter design level, it is firstly proposed to separately design the connective probability of the AIC cluster inputs and feedbacks. Through substantial experiments, optimum connective probability combination is derived. From the circuit implement view, dual-phases multiplexer input crossbar is presented according to the characteristics of AIC. The area of the AIC cluster, optimized through the proposed approach, achieves 21.21% smaller than the original one, the huge area problem is markedly ameliorated. When implementing the MCNC and VTR benchmarks, compared to Stratix IV, LUT based FPGA from Altera, the area-delay product of the AIC FPGA after optimisation is reduced by 48.49% and 26.29%, respectively. Compared to the original AIC-based FPGA architecture, the area-delay product is reduced by 28.48% and 28.37%, respectively.
- And-Inverter Cone (AIC) /
- AIC cluster /
- Post-pack netlist statistics /
- Connective probability /
- Separately design

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参考文献(19)

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