FPGA布线通道分布对面积效率的影响研究

徐新民; 王倩; 严晓浪

FPGA布线通道分布对面积效率的影响研究

徐新民^①;王倩,
王倩,
严晓浪

计量
- 文章访问数: 2400
- HTML全文浏览量: 114
- PDF下载量: 1286
- 被引次数: 0
出版历程
- 收稿日期: 2005-02-17
- 修回日期: 2005-07-04
- 刊出日期: 2006-10-19

The Research of Area-Efficiency for the Routing Channel Distribution in FPGAs

摘要

摘要: 该文提出了现场可编程门阵列(FPGA)布线通道不均匀分布对芯片面积的影响。引入几个典型的数学分布函数(高斯，正弦和三角分布)，实现通道容量随函数分布变化的新FPGA结构。将这些结构的FPGA与传统的布线通道均匀分布的FPGA作比较，结果表明按照数学分布变化的布线通道分布结构比均匀分布情况下的面积效率要高。亦即通道分布的变化趋势是峰值位置位于芯片中央，即通道容量最大，从中间位置向边缘按函数变化趋势逐渐变小。
- FPGA; 布线; 通道容量; 轨道; 高斯分布
Abstract: The effect of track distribution on chip area is investigated in this paper. Several typical distributions in math (Gaussian, Sine and Trigonal) are introduced to realize FPGAs architectures with routing channel width varying randomly on software platform. These various kinds of FPGA architecture are made comparison to the traditional FPGA with uniform routing channel width. The key results are that the non-uniform routing architectures educed from the introduction of maths distribution have a better area efficient than the uniform ones without sacrificing the circuit speed. And the trend of routing channel width transformation is that in the center of the chip is the peak point, and from the center to the edges the channel width becomes narrow gradually.

HTML全文

参考文献(1)

Xilinx Inc. The Programmable Logic Products Data Book 2000.[2]DeHon, Andre. Balancing interconnect and computation in a reconfigurable computing array. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, California, United States, 1999: 69-78.[3]Wilton S J E. Implementing logic in FPGA embedded memory arrays: Architectural implications. Proc IEEE Custom Integrated Circuits Conference, Santa Clara, May 1998: 1241-1244.[4]Trimberger Stephen. Effects of FPGA architecture on FPGA routing. Proceedings of the 32nd ACM/IEEE conference on Design automation, San Francisco, 1995: 574-578.[5]Masud M I, Wilton S J E. A new switch block for segmented FPGAs. International Workshop on Field Programmable Logic and Applications, Glasgow, United Kingdom, September 1999: 274-281.[6]Chow Paul, Soon O S. The design of an SRAM-based fieldprogrammable gate array-Part I: Architecture[J].IEEE Trans.onVLSI Systems.1999, 7(2):191-197[7]Khalid M, Rose J. The effect of fixed I/O positioning on theroutability and speed of FPGAs. Proc. Canadian Workshop on Field-Programmable Devices, Montreal, Canada, 1995: 94-102.[8]Yang S. Logic synthesis and optimization benchmarks, Version 3.0. Technical Report, Microelectronics Center of North Carolina, 1991.[9]Sentovich E M. SIS: A system for sequential circuit synthesis. Technical Report, No. UCB/ERL M92/41 University of California, Berkeley, May 1992.[10]Cong J, Ding Y. Flowmap: An optimal technology mapping algorithm for delay optimization in Lookup-Table based FPGA designs[J].IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems.1994, 13:1-12[11]Betz V, Rose J. VPR: A new packing, placement and routing tool for FPGA research. Seventh International Workshop on Field-Programmable Logic and Applications, London, UK, 1997: 213-222.[12]Wolf W. FPGA-Based System Design. Prentice Hall, 2004, chapter 3.1-3.3.

施引文献

资源附件(0)

访问统计