Abstract: Two methods of rapid code acquisition based on FFT are presented, one method is based on fractional multiple sampling rate convertor, and the other is based on decimation. To reduce hardware resource, two rapid code acquisition circuits utilizes duplicate design. Two designs applied parallel pipeline structure to improve the processing speed. Block floating-point arithmetic is used to enhance the dynamic range and computation accuracy. Two designs are implemented with a chip of FPGA respectively, simulation and measurement results show that the rapid code acquisition circuit based on fractional multiple sampling rate convertor costs more hardware resource, but can gain higher acquisition accuracy to be compared with the method based on decimation.