高性能半静态双边沿D触发器

王伦耀<EM>; </EM>夏银水; 叶锡恩

高性能半静态双边沿D触发器

王伦耀,

夏银水,
叶锡恩

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出版历程
- 收稿日期: 2005-03-11
- 修回日期: 2005-08-30
- 刊出日期: 2006-11-19

Design of High Performance Semi-Static Double Edge-Triggered Flip-Flops

摘要

摘要: 在分析现有静态结构双边沿触发器和动态结构双边沿触发器优缺点的基础上，该文提出了半静态结构双边沿触发器设计。PSPICE模拟表明，新设计功能正确。与以往一些设计相比，新设计在功耗、速度、功耗延迟积以及减少MOS晶体管使用数目等方面都具有明显的优势，从而使新设计具有良好的综合性能。该文的另一个贡献是对双边沿触发器性能的测试方法进行了探讨，提出了测试双边沿触发器最高频率的新方法。
- 集成电路; 半静态; D触发器; 低功耗; 双边沿触发器
Abstract: Based on analysis of traditional static and dynamic Double Edge-Triggered Flip-Flops (DETFFs), a new semi-static DETFF is proposed in this paper. PSPICE simulation shows that the proposed DETFF has correct operation. Compared with traditional static DETFFs, the proposed DETFF has significant improvement in terms of power, speed, Power-Delay-Product (PDP) and area. In addition, the performance measurement of the DETFFs is also discussed in this paper, and a new approach is proposed for testing the maximum working frequency of the DETFFs.

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Pedram M. Power minimization in IC Design: Principles and applications[J].ACM Trans. on Design Automation.1996, 1(1):3-56[2]Sakurai T.[J].Kuroda T. Low-power circuits design for multimedia CMOS VLSIs. In Proc. Synthesis and System Integration of Mixed Technologies, Fukuoka, Japan.1996,:-Llopis R P, Sachdev M. Low power, testable dual edge triggered flip-flops. Int. Symp. Low Power Electronics and Design, Monterey CA USA, 1996: 341-345.[3]Chung W, Lo T, Sachdev M. A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops[J].IEEE Trans. on Very Scale Integration(VLSI) Systems.2002, 10(6):913-918[4]Pedram M, Wu Q, Wu X. A new design of double edge triggered flip-flops. in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 1998: 417-421.[5]Blair G M. Low-power double-triggered flip-flops. ElectronicLetters, 1997, 33(10): 845-847.[6]Strollo A G, Napoli E, Cimino C. Low power double edge-triggered flip-flop using one latch[J].Electronic Letters.1999, 35(3):187-188[7]Hossain R, Wornski L D, Albicki A. Low power design using double edge triggered Flip-flopd. IEEE Trans. on Very Scale Integration(VLSI) Systems, 1994, 10(6): 261-265.[8]王伦耀, 吴训威, 叶锡恩. 新型半静态低功耗D触发器设计. 电路与系统学报, 2004, 9(6): 26-28.[9]Manolescu M, I-Pei Lin. Low-power half-static flip-flop structure. In Proc. Int. Semicond. Conf., Sinaia, Romania, 2000: 211-214.[10]Qiu X H.[J].Chen H Y. Discussion on the low-power latches and flip-flops. Int. Conf. on Solid-State Integrated Circuit Technology, Beijing, China.1998,:-[11]Mishra S M, Rofail S S, Yeo K S. Design of high performance double edge-triggered flip-flops[J].IEE Proc. Circuits Devices Systems.2000, 147(5):283-290[12]Kim S, Kim J, Hwang S Y. New path balancing algorithm for glitch power reduction[J].IEE Proc. Circuits Devices Systems.2001, 148(3):151-156

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