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一个VLSI三层布线通孔最少化的启发式算法

马琪 严晓浪

马琪, 严晓浪. 一个VLSI三层布线通孔最少化的启发式算法[J]. 电子与信息学报, 2001, 23(10): 1014-1021.
引用本文: 马琪, 严晓浪. 一个VLSI三层布线通孔最少化的启发式算法[J]. 电子与信息学报, 2001, 23(10): 1014-1021.
Ma Qi, Yan Xiaolang. A HEURISTIC ALGORITHM TO THREE-LAYER CONSTRAINED VIA MINIMIZATION[J]. Journal of Electronics & Information Technology, 2001, 23(10): 1014-1021.
Citation: Ma Qi, Yan Xiaolang. A HEURISTIC ALGORITHM TO THREE-LAYER CONSTRAINED VIA MINIMIZATION[J]. Journal of Electronics & Information Technology, 2001, 23(10): 1014-1021.

一个VLSI三层布线通孔最少化的启发式算法

A HEURISTIC ALGORITHM TO THREE-LAYER CONSTRAINED VIA MINIMIZATION

  • 摘要: 该文在三层布线的线段-相交图模型基础上,提出了一个启发式算法来解决VLSI三层布线通孔最少化问题,该算法通过总体优化和局部优化两个阶段对三层布线进行通孔优化。算法考虑了实际约束的处理方法,并进行大量的布线实例验证。
  • K.C. Chang, D. H-C. Du, Layer assignment problem for 3-layer routing, IEEE Trans. on Computer, 1988, C-37(5), 625-629.[2]K.E. Chang, H. F. Jyu, W. S. Feng, Constrained via minimization for three-layer routing, IEEE Trans. on Computer-Aided Design, 1989, CAD-2(6), 346-354.[3]S.C. Fang, K. E. Chang, W. S. Feng, S. J. Chen, Constrained via minimization with practical consideration for multi-layer VLSI/PCB routing problem, in Proc. 28th ACM/IEEE Design Automation Conf., 1991, 4, 5, 60-65.[4]K. Ann, S. Sahni, Constrained via minimization, IEEE Trans. on CAD of IC and Sys., 1993,12(2), 273-282.[5]J.S. Cherng, S. J. Chen, C. C. Tsai, J. M. Ho, An efficient approach for via minimization in multi-layer VLSI/PCB routing, in Proc. IEEE Custom Integrated Circuits Conf., 1995, 473-476.[6]K. Takahashi, T. Watanabe, A heuristic algorithm to solve constrained via minimization for three-layer routing problem, in Proc. ISCAS, 1998, 486-490.[7]Y.K. Chen, M. L. Liu, Three-layer channel routing, IEEE Trans. on Computer-Aided Design,1984, CAD-3(2), 156-163.
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出版历程
  • 收稿日期:  1999-09-06
  • 修回日期:  2000-02-13
  • 刊出日期:  2001-10-19

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