高清晰度电视视频解码器系统控制的设计与实现
Design and implementation of system control for the HDTV video decoder
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摘要: 该文提出了一种高清晰度电视(HDTV)视频解码器系统控制的设计方案,并对其工作原理进行了阐述。该方案采用FPGA(现场可编程门阵列)技术实现,具有设计灵活,方便的特点,经整机联试系统控制工作稳定、可靠,保障了正常的解码和显示。Abstract: This paper presents the design and implementation of system control for HDTV video decoder. The principle of the system control is described in detail too. FPGA is adopted for its programmable and reconfigurable features. The system control works perfectly and steadily which ensures the perfect work of decoder and display buffer.
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ISO/IEC 13818-1 Generic Coding of Moving Pictures and Associated Audio Information: System,Jan. 20, 1995. ［2］SO/IEC 13818-2 Generic Coding of Moving Pictures and Associated Audio Information: Video,Jan. 20, 1995. ［3］ATSC: ATSC Digital Television Standard, Oct. 4, 1995.[2]ATSC: Guide to the Use of the ATSC Digital Television Standard, Oct. 4, 1995.[3]K. Kawahara, H. Yamauchi, S. Okada, A single chip MPEG1 decoder, IEEE Trans. on Consumer Electronics, 1995, 41(3), 707-715.[4]Aldo Cugnini, Richard Shen, MPEG-2 video decoder for the digital HDTV grand allance system,IEEE Trans. on Consumer Electronics, 1995, 41(3), 748-752. -
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