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R.K.Brayton et al.,Logic Minimization Algorihms for VLSI SyntLesis, Kluwer Academic Publishers-Boston, (1984), Char 4.[2]S. J. Hong, P. G.Cain, D. L. Ostapko, IBM J. Res. Develop., 18(1974)5, 443-458.[3]P. Agrawal, V. D. Agrawal, N. N. Biswas, Multiple Output Minimizatioa[4]nd Design Automation Conference, Las Vegas. Nevada, (1985), 674-680.[5]D. W. Brown, A State-Machine Synthesizer-SMS, 18th Design Automation Conference, Nashville, Tenn. (1981), 301-305.[6]M. R. Dagenais, V. K. Agarwal, N. C Rumin; IEEE Trans. on CAD, CAD-5(1986)1, 229-238.[7]M. P. Roth; Computer Logic, Testing and Verification, Computer Science Press, Inc., Potomac, Maryland, (1980), 1-32.[8]S. J. Hong, S. Muroga, IEEE Trans. on C.,C-40(1991)1, 53-65.[9]S. R. Petrick, A Direct Determination of the Irredundant Forms of a Boolean Function From the Set of Prime Implicants, Air Force Cambridge Res. Center, Betford, MA, Tech, Rep. No. AFCRC-TR-56-110, (1956).[10]刘明业,李建一,计算机学报,6(1983)2,136-145.[11]J. P. Roth, Algebraic topological methods in synthesis, Annals of Computation Lab. of Harvard Univ Vol.[12], (1959), 53-73.[13]刘明业,计算机辅助逻辑设计理论,第一版,科学出版社,北京,1985年,第三章.
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