时序电路的状态验证研究与设计
VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS
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摘要: 采用二元判定图(BDD)作为工具来描述时序电路是非常有意义和有效的.本文通过对BDD的简化达到对状态变换图(STG)输入、路径和状态的压缩,从而提高状态遍历的效率,另外根据电路的特点,提出状态冲突和不相交分解的启发技术以有效地完成验证.
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关键词:
- 二元判定图; 节点; 压缩; 状态变换图
Abstract: It is very effective that use BDD to describe the synchronous circuits. This paper has proposed the reducing way for BDD in order to collapse the number of inputs, routes and states. Based on the features of circuit, several heuristic methods that speed up verification are presented. -
Odawara G.[J].et al. A logic verifier based on Boolean comparison, DA8.1986,:-. A logic verifier based on Boolean comparison, DA' target='_blank'>[2]Bose S.[J].Fisher A L. Automatic verification of synchronous circuits using symbolic logic simulation and temporal logic, IFIP9.1990,:-Touati H J.[J].et al.Implicit state enumeration of finite state machine using BDDs, ICCAD9.1990,:-.Implicit state enumeration of finite state machine using BDD' target='_blank'> -
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