基于并联开关的低电压低功耗电流型CMOS电路设计
Design of Low Voltage Low Power Current-Mode CMOS Circuits Based on Parallel Switches
-
摘要: 该文提出了一种电流型CMOS电路的并联开关结构，使得电流型CMOS电路能在较低的电源电压下工作，因而可以实现电路的低功耗设计，同时在相同的电源电压下，采用并联开关结构的电路比相应的串联开关电路具有更快的速度，PSPICE模拟证明了采用并联开关结构设计的电路能在较低的电源电压下工作，并具有较小的电路延时。Abstract: A novel current-mode CMOS parallel structure is proposed. This parallel switch structure allows current-mode CMOS circuits to perform under lower source voltage which makes low power consuming possible. Beside, the current-mode circuits based on the pro-posed parallel structure have smaller propagation delay time than its counterpart which use cascade switches under the same source voltage. PSPICE simulation proves that circuits designed with the proposed structure can perform under low source voltage while holding short propagation delay time.
-
Rabaey J M,Pedram M.Low Power Design Methodologies.Boston:Klumer Academic Press,1996:1-16.[2]Chandrakasan A P,Sheng S,Brodersen R W.Low power CMOS digital design[J].IEEE J.of Solid-State Circuits.1992,27(4):473-484[3]Small C.Shrinking devices put the squeeze on system packaging.EDN,1994,39(4):41-46.[4]Mead C,Conway L.Introduction to VLSI System.New York:Addison-Wesley Publishing Company,1980:1-8.[5]Masayuki Mizuno,Masakazu Yamashina,Koichiro Furuta.A GHz MOS adaptive pipeline technique using MOS current-mode logic[J].IEEE J.of Solid-State Circuits.1996,31(6):784-791[6]Wayne Current K.Current-mode CMOS multiple-valued logic circuits[J].IEEE J.of Solid-State Circuits.1994,29(2):95-107[7]吴训威,应时彦.基于开关信号理论的三值电流型CMOS电路设计.电子科学学刊,1993,15(2):113-120.[8]吴训威,Prosser F.数字电路的开关级设计理论.中国科学(E辑),1996,26(3):257-265.[9]Yeo K S,Lee H K.Novel 1V full-swing high-speed BiCMOS circuit using positive feedback baseboost technique.IEE Proc.-Circuits Devices Syst.,1999,146(3):129-134. -
计量
- 文章访问数: 2619
- HTML全文浏览量: 104
- PDF下载量: 1021
- 被引次数: 0
下载:
