Abstract: In deep-submicron Integrated Circuit (IC) design regime, the portion of leakage power consumption increases rapidly, therefore, leakage power optimization becomes a crucial part of circuit design flow. This paper proposes a mixed method of leakage optimization for gate-level netlist. The proposed method combines integer programming and heuristic algorithm to optimize leakage power at the cost of decreased timing slack. It starts at a given timing feasible design and finds alternative cell for each gate in the netlist with optimal power-delay sensitivity, then assigns alternative cell to individual gate during a levelized traverse on netlist according to specific rules. Finally, the proposed method performs a path-based timing recovery phase to fix timing violations. The entire flow iteratively converts timing slack to power-saving until no improvements could be gained. The benchmark results shows that our the proposed method achieves 10% on average, maximum 26% leakage power reduction while timing violation is confined within 5 ps.