An Efficient Reliability Estimation Method for Gate-level Circuit
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摘要: 随着半导体技术的不断发展,芯片的集成度越来越高,软差错已经成为影响电路可靠性的关键因素之一。为了有效评估软差错对电路的影响,该文提出一种基于信号取值概率的门级电路可靠度估算方法。首先计算电路所有节点在软差错影响下的取值概率,然后用故障模拟分析电路整体可靠性。通过对基准电路的实验并与概率转移矩阵方法进行比较,该方法在不损失准确度的前提下,在时间与空间开销方面都具有优势,尤其适合估算特定向量和随机向量激励下电路的可靠度。Abstract: With the development of semiconductor technologies and integration of chips, soft errors become the key factor influencing circuit reliability. In order to estimate the effects of soft errors, a reliability calculation method of gate-level circuit based on signals probability is proposed. All signals probabilities under soft errors are calculated first, and then the whole reliability is estimated using fault simulation. The proposed method is compared with the probabilistic transfer matrix approach and benchmark circuit experiments are finished, results show the method has the same accuracy as the Probabilistic Transfer Matrix (PTM) approach, but it needs shorter time and less space, especially suitable for calculation of reliability under specific vector and random vectors.
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Key words:
- VLSI /
- Soft error /
- Probabilistic gate model /
- Probabilistic Transfer Matrix (PTM) /
- Circuit reliability
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