Abstract: To accelerate the locking speed of the Digitally Controlled Phase-Locked Loop (DCPLL), a Dynamic Bandwidth Management (DBM) algorithm for DCPLL is presented. Only when the phase error sensed by the phase detector is less than the boundary condition for three times, the proposed algorithm decreases the DCPLL bandwidth. In addition, the proposed algorithm increases the DCPLL bandwidth immediately when the sensed phase error is larger the boundary condition. To verify the proposed algorithm, a behavioral model is developed in MATLAB environment. The simulation results show that, under the same condition, the locking time of the DCPLL with the proposed algorithm is reduced to 28.6%?85.7% of the locking time with the traditional DBM algorithm. Finally, a DCPLL is implemented by CSM 0.18 m 1P6M CMOS and tested. The measured results show that the proposed algorithm can decrease the phase error rapidly and keep the DCPLL in locking status. Therefore, the proposed algorithm can avoid the limitation of traditional DBM algorithm, decrease the probability of changing the PLL bandwidth falsely, and accelerate the locking speed.