一种10位200 kS/s 65 nm CMOS SAR ADC IP核
doi: 10.3724/SP.J.1146.2010.00688
A 10-bit 200 kS/s 65 nm CMOS SAR ADC IP Core
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摘要: 该文基于65 nm CMOS低漏电工艺，设计了一种用于触摸屏SoC的8通道10位200 kS/s逐次逼近寄存器型(Successive Approximation Register，SAR) A/D转换器(Analog-to-Digital Converter，ADC) IP核。在D/A转换电路的设计上，采用7MSB (Most-Significant-Bit) + 3LSB (Least-Significant-Bit) R-C混合D/A转换方式，有效减小了IP核的面积，并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上，通过采用一种低失调伪差分比较技术，有效降低了输入失调电压。在版图设计上，结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322m267m。在2.5 V模拟电压以及1.2 V数字电压下，当采样频率为200 kS/s，输入频率为1.03 kHz时，测得的无杂散动态范围(Spurious-Free Dynamic Range，SFDR)和有效位数(Effective Number Of Bits，ENOB)分别为68.2 dB和9.27，功耗仅为440W，测试结果表明本文ADC IP核非常适合嵌入式系统的应用。
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关键词:
- 模数转换器(ADC) /
- 逐次逼近寄存器(SAR) /
- 触摸屏SoC /
- CMOS /
- 低功耗
Abstract: Based on 65 nm CMOS low leakage process, an 8-channel 10-bit 200 kS/s SAR (Successive Approximation Register) ADC (Analog-to-Digital Converter) IP core for touch screen SoC is realized. In the D/A converter design, a 7MSB (Most-Significant-Bit)-plus-3LSB (Least-Significant-Bit) R-C hybrid conversion approach is utilized to reduce the area of the converter, and by reusing the MSB resistor string, the matching requirement of the capacitors is alleviated. With a low-offset pseuso-differential comparison approach, the input offset of the comparator is reduced. In the layout design, capacitor array symmetrical layout routing approach and resistor string dummy surrounding method are utilized to improve the matching performance. The area of the IP core is 322m267m. This converter operates with a 2.5 V analog supply and a 1.2 V digital supply. With the input frequency of 1.03 kHz at 200 kS/s sampling rate, the SFDR (Spurious-Free Dynamic Range) and ENOB (Effective Number Of Bits) are measured to be 68.2 dB and 9.27 respectively, and the power dissipation is just measured to be 440W. The design results prove the applicability of this converter to embedded SoC. -
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