一种基于并行处理器的快速车道线检测系统及FPGA实现

李元金; 张万成; 吴南健

doi:10.3724/SP.J.1146.2010.00111

一种基于并行处理器的快速车道线检测系统及FPGA实现

doi: 10.3724/SP.J.1146.2010.00111

基金项目:

国家自然科学基金(60976023)资助课题

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- 被引次数: 0
出版历程
- 收稿日期: 2010-01-28
- 修回日期: 2010-05-20
- 刊出日期: 2010-12-19

A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation

摘要

摘要: 该文提出了一种并行的快速车道线检测系统。该系统包含一个3232的处理器单元(PE)阵列和双RISC子系统。PE阵列实现车道线图像像素级并行预处理，获取图像边缘特征，双RISC核子系统根据边缘特征实现两条车道线直线参数的并行检测，从而使得检测过程的每一步都是并行进行，显著提高检测速率。该系统用FPGA实现。实验结果表明本系统具有良好的鲁棒性且可达到每秒50帧的检测速率，满足了车道偏离预警系统实时性要求，具备重要的应用价值。
- 图像处理 /
- 车道线检测 /
- 并行 /
- FPGA /
- 精简指令集计算机(RISC)
Abstract: This paper proposes a parallel fast traffic lane detection system. The system consists of a 3232 Processing Elements (PE) array and a dual RISC core subsystem. The PE array performs pixel-parallel image preprocessing and outputs edge features, the dual RISC core subsystem performs two lanes parameters detection in parallel based on edge features. In this way, every step in the detection process is in parallel and the detection rate is rapidly increased. The system is implemented with FPGA. The experiment shows that it has good robustness and can reach up to 50 fps. This meets the demand of real-time for lane departure warning system and makes an important sense for practical application.
- Image processing /
- Traffic lane detection /
- Parallel /
- FPGA /
- RISC (Reduced Instruction Set Computer)

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参考文献(1)

余天洪. 基于机器视觉的车道偏离预警系统的研究[D]. [博士论文], 吉林大学, 2006.[2]Yu T. Study on vision-based lane departure warning system [D]. [Ph.D. dissertation], Jilin University, 2006.[3]王荣本, 余天洪, 郭列. 基于机器视觉的车道偏离预警系统研究综述[J].汽车工程.2005, 27(4):463-464Wang R, Yu T, and Guo L. A survey on research of vision-based lane departure warning system [J]. Automotive Engineering, 2005, 27(4): 463-464.[4]Pankiewicz P, Powiretowski W, and Roszak G.VHDL implementation of the lane detection algorithm [C]. Mixed Design of Integrated Circuits and Systems, Poland, June 19-21, 2008: 581-584.[5]Hsiao Pei-yung, Cheng Hsien-chein, and Yeh Chun-wei. Automobile lane detection system-on-chip integrated with mixed signal mode CMOS image sensor[C]. Consumer Electronics, Macau, June 14-16, 2005: 320-323.[6]Miao W, Lin Q Y, Zhang W C, and Wu N J. A programmable SIMD vision chip for real-time vision applicaions[J].IEEE Journal of Solid-State Circuit.2008, 43(6):1470-1479[7]Lin Q Y, Miao W, Zhang W C, Fu Q Y, and Wu N J. A 1000 frames/s programmable vision chip with variable resolution and row-pixel-mixed parallel image processors [J].Sensors.2009, 9(8):5933-5951[8]田炳香, 郑榜贵, 吴晴. 高速公路车道线检测与跟踪算法研究[J]. 现代电子技术, 2008, 9(31): 180-183.[9]Tian B, Zheng B, and Wu Q. Research on lane detection and tracking algorithm of highway[J]. Modern Electronic Technique, 2008, 31(9): 180-183.[10]Huang Pei-yung, Yeh Chun-wei, and Huang Shih-shinh. A portable vision-based real-time lane departure warning system based on embedded calculating technique [C]. Vehicular Technology Conference, Australia May 7-10, 2006, 6: 2982-2986.

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