全数字接收机中一种基于并行流水线与快速FIR算法的插值滤波器结构及其实现
doi: 10.3724/SP.J.1146.2009.01292
Structure of Interpolation Filter Based on Parallel Pipelining and Fast FIR Algorithm and Its Implementation for All Digital Receiver
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摘要: 该文在对已有的拉格朗日立方插值滤波器Farrow结构进行分析和研究的基础上，使用了流水线技术和并行处理技术来提高滤波器的速度。在此基础上提出了基于快速FIR算法的结构，降低了并行的Farrow结构的复杂度。对该算法结构进行了仿真，并在FPGA上实现。分析结果表明，改进后的结构有更快的运行速度和更低的功耗。Abstract: The analysis and research are based on the existing Farrow structure of Lagrange interpolation filter. The pipelining and parallel processing technology are used to improve the speed of filter. On this basis, a new structure based on the fast FIR algorithm is proposed. It is used to reduce the complexity of the parallel Farrow structure. The structure is implemented for FPGA. The analysis results show that the structure has faster operational rate and lower power consumption.
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Key words:
- All-digital receiver /
- Interpolation filter /
- Farrow structure /
- Fast FIR algorithm
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