高级搜索

留言板

尊敬的读者、作者、审稿人, 关于本刊的投稿、审稿、编辑和出版的任何问题, 您可以本页添加留言。我们将尽快给您答复。谢谢您的支持!

姓名
邮箱
手机号码
标题
留言内容
验证码

一种改进的适用于Sigma-Delta ADC的数字抽取滤波器

郝志刚 杨海钢 张翀 吴其松 尹韬

郝志刚, 杨海钢, 张翀, 吴其松, 尹韬. 一种改进的适用于Sigma-Delta ADC的数字抽取滤波器[J]. 电子与信息学报, 2010, 32(4): 1012-1016. doi: 10.3724/SP.J.1146.2009.00247
引用本文: 郝志刚, 杨海钢, 张翀, 吴其松, 尹韬. 一种改进的适用于Sigma-Delta ADC的数字抽取滤波器[J]. 电子与信息学报, 2010, 32(4): 1012-1016. doi: 10.3724/SP.J.1146.2009.00247
Hao Zhi-gang, Yang Hai-gang, Zhang Chong, Wu Qi-song, Yin Tao. An Improved Digital Decimation Filter for Sigma-Delta ADC[J]. Journal of Electronics & Information Technology, 2010, 32(4): 1012-1016. doi: 10.3724/SP.J.1146.2009.00247
Citation: Hao Zhi-gang, Yang Hai-gang, Zhang Chong, Wu Qi-song, Yin Tao. An Improved Digital Decimation Filter for Sigma-Delta ADC[J]. Journal of Electronics & Information Technology, 2010, 32(4): 1012-1016. doi: 10.3724/SP.J.1146.2009.00247

一种改进的适用于Sigma-Delta ADC的数字抽取滤波器

doi: 10.3724/SP.J.1146.2009.00247

An Improved Digital Decimation Filter for Sigma-Delta ADC

  • 摘要: 数字滤波器在sigma-delta ADC芯片中占据了大部分芯片面积,该文提出了一种数字滤波器结构,这种结构滤波器采用一个控制单元和一个加法器取代了Hogenauer结构滤波器中差分器的多个加法器,从而减小数字电路的面积。一个采用这种结构的4阶的数字滤波器在CYCLONE II FPGA芯片中被实现,耗费的硬件资源比Hogenauer结构的滤波器减少近29%。
  • Fujimori I, Koyama K, and Trager D, et al.. A 5-V single-chipdelta-sigma audio A/D converter with 111 dB dynamic range[J].IEEE Journal of Solid-State Circuits.1997, 32(3):329-336[2]Geerts Y, Marques M A, and Steyaert M S. A 33-V, 15-bit,delta-sigma ADC with a signal bandwidth of 1.1 MHz forADSL applications [J].. IEEE Journal of Solid-State Circuits.1999, 34(7):927-936[3]Dolecek G and Mitra S. On design of CIC decimation filterwith improved response 2008.ISCCSP 2008.3rd InternationalSymposium on Communications, Control and SignalProcessing, Malta, March 12-14, 2008: 1072-1076.Chong K and Gopalakrishanan P, et al.. Low power approachfor decimation filter hardware realization [C]. Proceedings ofWorld Academy of Science, Engineering and Technology,Singapore, August 29-31, 2008: 550-553.[4]Shiraishi M. A simultaneous coefficient calculation methodfor sincN FIR filters [J].IEEE Transactions on Circuits andSystems I: Fundamental Theory and Applications.2003, 50(4):523-529[5]Quiquempoix V and Bellini G, et al.. Digital decimation filter[P] US, 6,788,233, 2004.[6]Hogenauero B. An economical class of digital filters fordecimation and interpolation [J].IEEE Transactions onAcoustics, Speech, and Signal Processing.1981, 29(2):155-162[7]Chu S and Burrus C. Multirate filter designs using combfilters [J]. IEEE Transactions on Circuit Systems, 1984,32(11): 913-924.[8]Losada R and Lyons R. Reducing CIC filter complexity [J].IEEE Signal Process Magazine, 2006, 23(4): 124-126.[9]Laddomada M. Generalized comb decimation filters for A/D converters: analysis and design [J].IEEE Transactionson Circuits Systems I.2007, 54(5):994-1005[10]Zhu Heng-fang, Wu Xiao-bo, and Yan Xiao-lang. Low-powerand hardware efficient decimation filters in sigma-delta A/Dconverters [C]. 2005 IEEE Conference on Electron Devicesand Solid-State circuit, Hong Kong, Deccember 19-21, 2005:665-668.
  • 加载中
计量
  • 文章访问数:  4097
  • HTML全文浏览量:  144
  • PDF下载量:  2384
  • 被引次数: 0
出版历程
  • 收稿日期:  2009-03-02
  • 修回日期:  2009-07-22
  • 刊出日期:  2010-04-19

目录

    /

    返回文章
    返回