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具有预计算功能的新型绝热数值比较器设计

汪鹏君 曾小旁

汪鹏君, 曾小旁. 具有预计算功能的新型绝热数值比较器设计[J]. 电子与信息学报, 2010, 32(1): 214-218. doi: 10.3724/SP.J.1146.2008.01718
引用本文: 汪鹏君, 曾小旁. 具有预计算功能的新型绝热数值比较器设计[J]. 电子与信息学报, 2010, 32(1): 214-218. doi: 10.3724/SP.J.1146.2008.01718
Wang Peng-jun, Zeng Xiao-pang. Design of New Adiabatic Digital Comparator with Pre-Computational Function[J]. Journal of Electronics & Information Technology, 2010, 32(1): 214-218. doi: 10.3724/SP.J.1146.2008.01718
Citation: Wang Peng-jun, Zeng Xiao-pang. Design of New Adiabatic Digital Comparator with Pre-Computational Function[J]. Journal of Electronics & Information Technology, 2010, 32(1): 214-218. doi: 10.3724/SP.J.1146.2008.01718

具有预计算功能的新型绝热数值比较器设计

doi: 10.3724/SP.J.1146.2008.01718

Design of New Adiabatic Digital Comparator with Pre-Computational Function

  • 摘要: 该文通过对钟控传输门绝热逻辑(Clocked Transmission Gate Adiabatic Logic,CTGAL)电路和数值比较器电路工作原理及结构的研究,提出了一种基于CTGAL电路的具有预计算功能的新型绝热数值比较器设计方案。该方案具有冗余抑制作用,将其与利用PAL-2N电路设计的低功耗绝热数值比较器相比,功耗节省平均约60%。PSPCIE模拟结果表明,此数值比较器逻辑功能正确,低功耗特性明显。
  • 汪鹏君, 方振贤, 刘莹. 基于2N-2N2P结构的绝热非整数除电路设计[J].电子与信息学报.2006, 28(2):380-384浏览[2]Wisetphanichkij S P and Dejhan K. The combinational andsequential adiabatic circuit design and its applications[J].Circuits, Systems, and Signal Processing, 2009, doi: 10.1007/s00034-009-9096-5.[3]Thomsen M K and Gluck R. Optimized reversible binary-codeddecimal adders[J]. Journal of Systems Architecture, 2008, doi:10.1016/j, sysarc. 2007. 12. 006.[4]Sarandy M S, Wu L A, and Lidar D A. Consistency of theadiabatic theorem[J].Quantum Information Processing.2004,3(6):331-349[5]吴晓波, 吴蓉, 严晓浪. 一种高精度动态CMOS 比较器的设计与研制[J]. 电路与系统学报, 2007, 12(4): 118-123.Wu Xiao-bo, Wu Rong, and Yan Xiao-lang. A precise dynamicCMOS comparator[J]. Journal of Circuits Systems, 2007, 12(4):118-123.[6]Liu Ki and Yang Hai-gang. A CMOS dynamic comparator forpipelined ADCs with improved speed/power ratio[J]. Journal ofSemiconductors, 2008, 29(1): 75-81.[7]Wang Peng-jun and Yu Jun-jun. Design of two-phase sinusoidalpower clock and clocked transmission gate adiabatic logiccircuit[J]. Journal of Electronics(China), 2007, 24(2): 225-231.[8]Hamed H F A, Kaya S, and Starzyk J A. Use of nano-scaledouble-gate MOSFETs in low-power tunable current modeanalog circuits[J].Analog Integrated Circuits and SignalProcessing.2008, 54(3):211-217[9]Chen Feng, Bakkaloglu B, and Ramaswamy S. Design andanalysis of a CMOS passive △ ADC for low power RFtransceivers[J].Analog Integrated Circuits and Signal Processing.2009, 59(2):129-141[10]Navi K, et al.. A novel low-power full-adder cell for low voltage[J].Integration, the VLSI Journal, 2009, doi: 10.1016/ j.vlsi.2009.02.001.[11]Senthilpari C, Singh A K, and Diwakar K. Design of a low-power,high performance, 88 bit multiplier using a Shannon-basedadder cell[J].Microelectronics Journal.2008, 39(5):812-821[12]Naderi A, et al.. A new high speed and low power four-quadrantCMOS analog multiplier in current mode[J]. InternationalJournal of Electronics and Communications(AEU), 2008,doi:10.1016/j,aeue.2008.06.002.[13]谢小平, 阮晓声. 二种EPAL 绝热开关电路[J]. 半导体学报, 2004,25(11): 1526-1531.Xie Xiao-ping and Ruan Xiao-sheng. Two types EPAL adiabaticlogic circuits[J]. Journal of Semiconductors, 2004, 25(11):1526-1531.
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出版历程
  • 收稿日期:  2008-12-18
  • 修回日期:  2009-06-19
  • 刊出日期:  2010-01-19

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