Abstract: Motivated by an enormous amount of storage between DWT and EBCOT in JPEG2000 hardware implementation, a novel memory-efficient scheme based on code block size is proposed. Further reuse of on-chip code block size memories and efficient scheduling of them reduce hardware cost in both area and power. In the implementation, line-based lifting DWT architecture and bit plane parallel EBCOT design are used. The resulting coding efficiency is improved and the whole architecture can achieve real time processing. Experimental results show that on demand of real time coding, when a tile with resolution up to 512-width and 512-height is decomposed with four levels in 9/7 or 5/3 filters and the size of code block is 3232, the wavelet coefficients memory needed in the proposed architecture is reduced by over 80%, compared with existing architectures that wavelet coefficients are directly deposited in off-chip memories. The whole design has been synthesized and mapped into Xilinx FPGA, passing the verification when the system is working at the clock of 100MHz.