用于HDTV视频解码器的高性能SDRAM控制器

赵强; 罗嵘; 汪蕙; 杨华中

doi:10.3724/SP.J.1146.2006.00429

用于HDTV视频解码器的高性能SDRAM控制器

doi: 10.3724/SP.J.1146.2006.00429

基金项目:

国家自然科学基金(90307016)和广东省关键领域重点突破项目资助课题

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出版历程
- 收稿日期: 2006-04-06
- 修回日期: 2006-07-07
- 刊出日期: 2007-06-19

High Performance SDRAM Controller Design for HDTV Video Decoder

摘要

摘要: 该文提出了一种适用于HDTV视频解码器的高性能SDRAM控制器。通过为SDRAM控制器设置多个端口并集成仲裁功能，该SDRAM控制器可以取代传统的总线＋DMA结构，为解码器中的功能单元有效地分配存储器的带宽资源。该文提出的SDRAM控制器内建流水线式的地址和数据路径，配合SDRAM本身流水处理指令的特性，能够无延时地处理各个端口上的存储器访问请求，从而降低了对片上缓存的需求。仿真综合结果表明，该文设计的SDRAM控制器满足HDTV解码的性能要求，且与总线＋DMA结构相比，片上缓存容量减少了约70%。
- HDTV;SDRAM控制器;视频;解码
Abstract: A high performance SDRAM controller for HDTV video decoder is proposed. Configured with multiple ports and integrated with an arbitration function, the SDRAM controller proposed can be used in place of traditional structures of bus + DMA to share the bandwidth resource of the SDRAM among several function blocks in the HDTV decoder. The SDRAM controller consists of pipelined address path and data path, which take advantage of the pipeline feature of the SDRAM to enable the controller to process access requests from each port continuously, so that the storage volume of on-chip memories is significantly reduced. The simulation results show that up to 70% of the on-chip memories could be reduced compared to the traditional bus + DMA structures, while the performance for HDTV decoding is assured.

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参考文献(1)

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