基于物理指数MOSFET模型的SRAM存储体单元优化
doi: 10.3724/SP.J.1146.2005.01313
Optimization of SRAM Memory Cell Based on Physical Alpha-Power Law MOSEFT Model
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摘要: 存储体单元是静态随机存储器(SRAM)最基本、最重要的组成部分,它在改善系统性能、提高芯片可靠性、降低成本与功耗等方面都起到了积极的作用。该文采用物理指数MOSFET模型建立了与SRAM存储体单元相关的功耗,延迟的性能模型,并结合存储体单元面积模型以及可靠性分析,提出了一种存储体单元结构优化方法。实验结果表明采用此优化方法得出的存储体单元结构降低了功耗,访问时间以及面积,与仿真结果相比误差小于10%,实验仿真结果证明了性能模型和优化方法的有效性和正确性。Abstract: Memory Cell is a basic and important macro block of SRAM. It has played a positive role in improving performance and reliability, lowering cost and power consumption. In this paper a new physical alpha-power law MOSEFT model is used to establish power and delay model related with SRAM memory cell. Adopting those performance models, memory cell area model and reliability analysis, a new memory cell structure optimization method is proposed. Experimental result shows SRAM power, access time and area are reduced by adopting this method, and computed performance parameter varies less than 10% compares with simulation result. Experiment results indicate the effectiveness and validity of the performance model and optimization method.
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[1] Burns J R. Switching response of complementary symmetry MOS transistor logic circuits[J]. RCA Rev, 1964, 25(12): 627 -661. [2] Hedenstierna N and Jeppson K O. CMOS circuit speed and buffer optimization[J]. IEEE Trans. on CAD, 1987, 6(2): 270 -281. [3] Vemuru S R. A model for delay evaluation of a CMOS inverter[C]. Proceeding of the ISCAS, New Orleans, USA, 1990: 89-92. [4] Sakurai T and Newton A R. Alpha-Power law MOSEFT model and its applications to CMOS inverter delay and other formulas[J].Solid State Circuits.1990, 25(2):584- [5] Bowman K A and Austin B L, et al.. A physical Alpha-power law MOSEFT model[J].Solid State Circuits.1999, 34(10):1410- [6] Sakurai T. Closed form expressions for interconnection delay, coupling and crosstalk in VLSIs [J].IEEE Trans. on Electron Devices.1993, 40(1):118- [7] Rabaey J M, et al. Digital integrated circuits: A design perspective[M]. New Jersey: Prentice-Hall, 2003: 657-661. [8] Bhavnagarwala A J. The impact of intrinsic device fluctuations on CMOS SRAM cell stability[J].Solid State Circuits.2001, 36(4):658-
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