基于双侧P型柱与电流扩展层协同设计的1200 V沟槽型SiC MOSFET性能优化与栅氧电场分析
doi: 10.11999/JEIT260164 cstr: 32379.14.JEIT260164
Performance Optimization and Gate Oxide Electric Field Analysis of 1200V Trench SiC MOSFET Based on PCL-CSL Collaborative Design
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摘要: 碳化硅(SiC)功率金属-氧化物-半导体场效应晶体管(MOSFET)凭借耐压高、导通电阻低和功耗小的优势，已广泛应用于中高压电力电子系统中，在提升系统效率与功率密度方面具有重要意义。该文基于TCAD仿真平台，开展
1200 V等级沟槽型SiC MOSFET的结构设计与电学特性仿真研究。通过双侧P型柱(PCL)与电流扩展层(CSL)协同设计，有效优化了器件在阻断状态下的电场分布与导通状态下的电流输运性能。系统仿真分析了外延层掺杂浓度(NEpi)、沟槽宽度与深度、P型阱区(PW)注入剂量、PCL间距及CSL注入剂量等关键结构参数对器件比导通电阻(Ron,sp)、阈值电压(VTH)、击穿电压(BV)及栅氧峰值电场(Eox-max)的影响机制。研究结果表明，优化后的器件可实现VTH=4.7 V, Ron,sp=1.57 mΩ·cm2, BV=1708 V, Eox-max=2.5 MV/cm的良好性能折衷。该研究为开发高性能沟槽型SiC MOSFET提供了系统的仿真方法与设计依据。Abstract:Objective 1 200 V Silicon Carbide (SiC) trench Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are key devices in medium- and high-voltage power conversion systems. They feature high switching performance, low conduction loss, and high-temperature stability. However, conventional trench structures suffer from electric-field concentration at the trench corner and bottom gate oxide. This effect can cause the peak gate oxide electric field to exceed the industrial reliability criterion of 3 MV/cm, reducing long-term reliability. In addition, strong trade-offs exist among breakdown voltage, specific on-resistance, threshold voltage, and peak gate oxide electric field. These trade-offs make it difficult to achieve high efficiency and high reliability at the same time. To address these issues, this work studies a synergistic structure that combines deep P-type Column (PCL), Carrier Storage Layer (CSL), and locally thickened gate oxide. The aim is to regulate the electric-field distribution, suppress electric-field concentration, improve carrier transport, and achieve balanced device performance. This study provides a systematic design method for high-reliability and high-performance 1 200 V Trench SiC MOSFETs for industrial applications. Methods Numerical device simulations were performed using a Technology Computer-Aided Design (TCAD) platform to analyze and optimize the electrical performance of 1 200 V Trench SiC MOSFETs. To ensure reliable simulations, physical models were used for bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, avalanche breakdown, incomplete dopant ionization, doping- and temperature-dependent mobility, and high-field mobility saturation. A device structure with deep PCL, CSL, and locally thickened bottom gate oxide is constructed to reduce the peak gate oxide electric field and improve device reliability. Key structural and process parameters were swept and quantitatively analyzed. These parameters included epitaxial layer thickness (TEpi), epitaxial layer doping concentration (NEpi), trench width, trench depth, P-Well (PW) implantation dose, PCL spacing, and CSL implantation dose. Static electrical characteristics, including threshold voltage (Vth), specific on-resistance (Ron,sp), Breakdown Voltage (BV), and peak gate oxide electric field (Eox,max) are extracted and evaluated. The final parameter combination is finally determined through a trade-off analysis between conduction performance and long-term device reliability. Results and Discussions The simulation results show that the deep PCL structure redirects electric-field lines away from the trench bottom gate oxide and reduces electric-field concentration. When this structure is combined with the locally thickened bottom gate oxide, Eox-max is reduced below 3 MV/cm, meeting the industrial reliability criterion. The CSL broadens the vertical conduction path, reduces current crowding, and decreases Ron,sp. Parameter optimization shows that TEpi, NEpi, trench dimensions, PW implantation dose, and CSL implantation dose determine the trade-off between BV and conduction performance ( Fig. 5 ,Fig. 6 ,Fig. 9 ,Fig. 10 , andFig. 19 ). PCL spacing has a strong effect on electric-field shielding and gate oxide protection (Fig. 16 andFig. 17 ). After multi-parameter optimization, the device achieves VTH=4.7 V, BV=1 708 V, Ron,sp=1.57 mΩ·cm2, and Eox-max=2.5 MV/cm (Table 2 ). These results indicate balanced performance for high-voltage power applications.Conclusions A synergistic PCL-CSL structural design for 1 200 V Trench SiC MOSFETs is studied and validated through TCAD simulation. The design addresses key limitations of conventional Trench SiC MOSFETs, including high peak gate oxide electric field, limited breakdown capability, and the trade-off between conduction performance and reliability. The effects of TEpi, NEpi, trench dimensions, PW implantation dose, PCL spacing, and CSL implantation dose on device performance and gate oxide reliability are clarified through parameter sweeping and comparative analysis. With coordinated structural optimization, the optimized device achieves low Ron,sp, high BV, suitable VTH, and suppressed electric-field concentration near the trench bottom oxide. Eox-max is controlled below the 3 MV/cm industrial reliability criterion, which reduces the risk of oxide degradation under high-bias operation. The proposed structural strategy and optimization method provide guidance for the design, simulation, and process development of high-voltage, high-reliability SiC power devices. -
表 1 沟槽型SiC MOSFET的主要结构参数以及性能参数
参数 数值 Cell宽度 2.8 μm EPI深度 12 μm EPI浓度 1×1016 cm–3 PCL掺杂 总剂量5×1014 cm–2，5步注入 PW掺杂 总剂量9.5×1012 cm–2，4步注入 CSL掺杂 总剂量5×1012 cm–2，5步注入 PW结深 0.7 μm Trench宽度 0.7 μm Trench深度 1.2 μm 侧壁氧化层厚度 50 nm 底部氧化层厚度 200 nm VTH 5.0 V Ron,sp 1.70 mΩ·cm2 BV 1712 VEox-max 2.6 MV/cm 
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表 2 器件关键结构参数以及主要性能参数
参数 数值 Cell宽度 2.8 μm EPI深度 12 μm EPI浓度 1×1016 cm–3 PCL掺杂 总剂量5×1014 cm–2，5步注入 PCL间距 1.0 μm PW掺杂 总剂量9.5×1012 cm–2，4步注入 CSL掺杂 总剂量5×1012 cm–2，5步注入 PW结深 0.7 μm Trench宽度 0.5 μm Trench深度 1.1 μm 侧壁氧化层厚度 50 nm 底部氧化层厚度 200 nm VTH 4.7 V Ron,sp 1.57 mΩ·cm2 BV 1708 VEox-max 2.5 MV/cm
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