一种面向单片三维集成电路层间通孔的并行测试方法

陈田; 陈炜坤; 刘军; 梁华国; 鲁迎春

doi:10.11999/JEIT251375

一种面向单片三维集成电路层间通孔的并行测试方法

doi: 10.11999/JEIT251375 cstr: 32379.14.JEIT251375

1.
合肥工业大学计算机与信息学院合肥 230601
2.
合肥工业大学微电子学院合肥 230601

基金项目: 国家自然科学基金(62174048, 62027815)

详细信息

作者简介:
陈田：女，副教授，研究方向为3D芯片与Chiplet、集成电路可测性设计、集成电路低功耗测试；人工智能、可穿戴计算

陈炜坤：男，硕士生，研究方向为3D芯片与Chiplet、三维集成电路的内建自测试与可测试性设计

刘军：男，副教授，研究方向为嵌入式系统、基于机器学习的故障测试和机器学习加速等软件、硬件结合方面

梁华国：男，教授，研究方向为容错计算与硬件安全、嵌入式系统综合与测试、智能控制系统

鲁迎春：男，副教授，研究方向为集成电路硬件安全技术、集成电路抗辐照加固技术、集成电路测试技术

通讯作者:
陈田　ct@hfut.edu.cn

中图分类号: TN407
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- 被引次数: 0
出版历程
- 收稿日期: 2025-12-30
- 修回日期: 2026-02-10
- 录用日期: 2026-02-10
- 网络出版日期: 2026-03-04

A Method for Parallel Testing of Interlayer Vias in Monolithic 3D Integrated Circuits

1.
School of Computer Science and Information Engineering, Hefei University of Technology, Hefei 230601, China
2.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: The National Natural Science Foundation of China (62174048, 62027815)

摘要

摘要: 在单片三维集成电路中，单片层间通孔(MIV)是实现垂直互连的关键结构，其制造缺陷会严重影响芯片可靠性。然而，面对MIV数量庞大、电气参数微小、故障类型多样的特点，实现高精度、低开销的测试是一个重要挑战。该文提出一种基于时间数字转换器(TDC)的MIV并行测试方法。通过行列分组将待测MIV构建成行或列的测试链，并通过数控延迟线(DCDL)来生成具有特定相位关系的测试激励信号。利用TDC测量电路的响应，并通过分析响应序列的规律性偏差，可以实现MIV硬故障和小延迟故障的测试。仿真结果表明，该方法在45 nm工艺下可检测阻值高于8.4 kΩ的开路故障，低于67 kΩ的泄漏故障以及低于32 kΩ的短路故障，而且测试结果在不同工艺-电压-温度(PVT)条件下保持稳定。与现有方案相比，该方法在检测精度、条件鲁棒性及硬件开销方面展现出更好的综合性能，为高密度M3D IC的MIV测试提供了一种有效解决方案。
- 单片三维集成电路 /
- 单片层间通孔 /
- 时间数字转换器 /
- 并行测试 /
- 内建自测试
Abstract: Objective As device dimensions in conventional two-dimensional integrated circuits approach fundamental physical limits, further improvements in performance and integration density face significant challenges. Monolithic three-dimensional integrated circuits (M3D ICs), which sequentially stack multiple active device layers on a single wafer, provide an effective solution to overcome these limitations. In M3D ICs, monolithic inter-tier vias (MIVs) are employed to realize vertical interconnections between device tiers. Compared with through-silicon vias (TSVs), MIVs feature much smaller dimensions, lower parasitic capacitance, and shorter interconnect delay. However, their small electrical variations and massive quantity cause defects to manifest mainly as subtle delay shifts, posing stringent requirements on test accuracy, efficiency, and robustness against Process, Voltage, and Temperature (PVT) variations. Existing MIV testing approaches suffer from limited scalability, strong PVT sensitivity, and difficulty in simultaneously achieving small-delay defect detection and fault localization in large-scale arrays. To address these challenges, a parallel MIV testing method based on a time-to-digital converter (TDC) is presented to enable efficient and reliable testing of large MIV arrays with low area and time overhead. Methods Large-scale MIVs are logically organized into a two-dimensional array structure. Each basic test cell consists of a device-under-test MIV, a tri-state buffer, and a D flip-flop, and multiple cells are cascaded to form row test chains and column test chains. By systematically exploiting the inherent input capacitance mismatch between the data and clock terminals of the D flip-flop, an embedded TDC structure incorporating the MIV under test is constructed. Test stimuli are generated by a digitally controlled delay line (DCDL), which produces START and STOP pulse signals with multiplicatively adjustable phase differences and injects them into different propagation paths of the test chains, enabling time quantization through a signal chasing mechanism. Structural symmetry between the test chains is employed to mitigate the influence of PVT variations. As the START and STOP phase difference is progressively amplified, multiple TDC readings are collected to characterize defect-induced small delay variations and to distinguish them from measurement noise and PVT-induced fluctuations. After fault information is obtained for individual test chains, cross-analysis of row and column test results enables fault localization within the two-dimensional MIV array. Results and Discussions Simulation results based on the Nangate 45 nm standard cell library demonstrate that, under fault-free conditions, TDC readings obtained at different phase difference settings exhibit a stable linear proportional relationship (Fig. 7). Extensive Monte Carlo simulations are performed to determine a robust deviation tolerance threshold of 2, which effectively separates normal variations caused by PVT fluctuations from abnormal shifts induced by defects. Fault injection experiments verify that small delay defects occurring on both the START chain and the STOP chain can be effectively detected and distinguished (Fig. 8). In terms of quantitative detection capability, the minimum detectable resistive open defect is approximately 8.4 kΩ, while the maximum detectable leakage defect and resistive short defect are about 67 kΩ and 32 kΩ, respectively, outperforming existing methods (Fig. 9). Moreover, the row–column decomposition architecture effectively alleviates the growth of test time as the MIV array size increases, resulting in a substantial reduction in overall test overhead. Area evaluation indicates that the average area overhead of the embedded built-in self-test structure is only 5.594 µm² per MIV, making it suitable for high-density M3D integration. Conclusions A parallel TDC-based testing approach for large-scale MIV arrays is presented, which combines row–column decomposition, phase-difference multiplication, and proportional deviation-based decision mechanisms to achieve efficient detection and accurate localization of both hard faults and small delay defects. Structural symmetry within the test chains effectively enhances robustness against PVT variations. Simulation results confirm that the proposed method can reliably detect resistive open, leakage, and short defects while maintaining low area and time overhead. Compared with existing techniques, a favorable balance among test accuracy, PVT robustness, test efficiency, and hardware cost is achieved. Owing to its scalability and practical feasibility, the proposed approach provides an effective and reliable solution for MIV testing in advanced monolithic three-dimensional integrated circuits.
- Monolithic 3D Integrated Circuits (M3D ICs) /
- Monolithic Inter-tier Via (MIV) /
- Time-to-Digital Converter (TDC) /
- Parallel test /
- Built-in self-test (BIST)

HTML全文

图 1 MIV电气参数模型

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图 2 MIV故障模型

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图 3 整体测试结构

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图 4 硬故障测试

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图 5 DCDL结构

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图 6 测试流程图

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图 7 不同PVT条件下，无故障MIV的bias分布

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图 8 故障MIV存在的小延迟故障的测试结果

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图 9 三类故障的统计结果

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表 1 仿真参数

参数	值
电压VDD	0.9 V−1.1 V
温度	–20 °C−60 °C
R_open范围	0 kΩ–15 kΩ
R_leak范围	10 kΩ–70 kΩ
R_short范围	10 kΩ–140 kΩ
C_D均值	0.955 fF
C_clk均值	0.864 fF

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表 2 与其他方案的对比实验结果

	[15]	[16]	[17]	[18]	[19]	本文方案
硬故障	能	能	能	能	能	能
故障定位	不能	不能	能	能	不能	能
最小开路电阻(kΩ)	15−75	25	17−130	19	6.7	8.4
最大泄漏电阻(kΩ)	/	/	/	/	14−41	67
最大短路电阻(kΩ)	3−15	12	10	3.3	0.17−28	32
抗PVT	不能	不能	不能	不能	能	能
面积(um²)	/	7.983	36.442	1.043	6.996	5.594
时间规模	O(n)	O(1)	O(n)	O($ \sqrt{n} $)	受分组影响	O($ \sqrt{n} $)

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