面向高速读写需求的宇航级抗辐射静态随机存储器加固单元设计

蔡烁; 帅威; 胡星; 梁鑫杰; 黄珠; 余飞

doi:10.11999/JEIT251287

面向高速读写需求的宇航级抗辐射静态随机存储器加固单元设计

doi: 10.11999/JEIT251287 cstr: 32379.14.JEIT251287

蔡烁^1, ,,
帅威¹,
胡星¹,
梁鑫杰²,
黄珠¹,
余飞¹

1.
长沙理工大学物理与电子科学学院长沙 410114
2.
湖南省康普通信技术有限责任公司长沙 410200

基金项目: 国家自然科学基金(62172058)

详细信息

作者简介:
蔡烁：男，博士，教授，研究方向为容错设计、抗辐射电路理论与可靠性分析

帅威：男，硕士生，研究方向为集成电路抗辐射加固设计、电路可靠性评估

胡星：女，博士，研究方向为集成电路安全理论、硬件木马检测

梁鑫杰：男，硕士，工程师，研究方向为宇航级高性能集成电路设计

黄珠：男，硕士生，研究方向为集成电路设计

余飞：男，博士，副教授，研究方向为非线性系统与理论

通讯作者:
蔡烁　caishuo@csust.edu.cn

中图分类号: TN402
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- HTML全文浏览量: 53
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- 被引次数: 0
出版历程
- 收稿日期: 2025-12-04
- 修回日期: 2026-02-16
- 录用日期: 2026-03-03
- 网络出版日期: 2026-03-15

Design of an Aerospace-grade Radiation-hardened SRAM Cell for High-speed Read/Write Applications

1.
School of Physics and Electronic Science, Changsha University of Science & Technology, Changsha 410114, China
2.
Hunan Kangpu Communication Technology Co., Ltd., Changsha 410200, China

Funds: The National Natural Science Foundation of China (62172058)

摘要

摘要: 随着CMOS工艺微缩，静态随机存取存储器(SRAM)在宇航级场景下面临严峻辐射可靠性挑战，且现有抗辐射加固(RHBD)结构难以兼顾高抗辐射能力与高速读写访问性能。为此，该文提出一种面向高速读写需求的宇航级抗辐射SRAM单元RFWF16T。该结构通过双源隔离机制，将敏感节点缩减至2个；同时，通过构建对称的反馈回路，该单元实现了100%的单节点翻转自恢复与83.3%的双节点翻转自恢复。为突破传统加固结构的速度瓶颈，RFWF16T利用短反馈路径与低阻抗电压泄放回路，在28 nm工艺下实现了20.97 ps的读访问时间与2.72 ps的写访问时间，其读写速度相比其他8种同类典型加固结构分别平均提升了46.65%和14.77%。蒙特卡罗与工艺角-电压-温度实验表明，该结构在宽扰动范围内具有强鲁棒性，并在综合电气质量度量评价中表现最优。结果表明，RFWF16T在保证高抗辐射能力的同时有效解决了读写速度瓶颈，具备工程应用潜力。
- 静态随机存取存储器 /
- 抗辐射加固 /
- 单节点翻转 /
- 双节点翻转 /
- 高速读写访问
Abstract: Objective With the continued scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technology nodes and the reduction in supply voltage, Static Random Access Memory (SRAM) in aerospace environments becomes increasingly sensitive to high-energy particle radiation and is prone to Single-Node Upset (SNU) and Double-Node Upset (DNU). This sensitivity poses a serious challenge to the reliability of spaceborne Systems-on-Chip (SoC). Existing Radiation-Hardened-By-Design (RHBD) structures, however, usually cannot balance strong radiation tolerance with high-speed access performance. This work therefore aims to design an aerospace-grade radiation-hardened SRAM cell for high-speed read/write applications that provides both strong radiation resistance and fast access performance. Methods The proposed Read Fast and Write Fast 16-Transistor (RFWF16T) SRAM is built on a dual-source isolation architecture composed of 16 transistors (8 PMOS and 8 NMOS) (Fig. 1, Fig. 2). By using a symmetric recovery mechanism, the RFWF16T reduces the number of key sensitive nodes to only two. Redundant transistors (P2 and P6) are used to establish a stable high-level isolation state, which isolates the storage nodes from potential disturbances during the non-access phase. To achieve high-speed operation, the RFWF16T combines a short feedback path with a low-impedance voltage discharge loop. Unlike conventional hardened cells that rely on stacked transistors, which increase resistance and delay, the RFWF16T adopts a parallel access topology connected to word lines and bit lines. This configuration forms a low-impedance path during write operations and significantly accelerates node voltage switching (Fig. 3). Performance verification confirms the self-recovery capability of the four data nodes. A comprehensive variation analysis is conducted, including Process-Voltage-Temperature (PVT) variations and 2,000-point Monte Carlo simulations. Additionally, an improved Electrical Quality Metric (EQM) is proposed to evaluate multidimensional performance quantitatively. Results and Discussions The RFWF16T exhibits strong overall performance, particularly in overcoming the speed bottleneck of hardened SRAM cells. In terms of access speed, the RFWF16T performs substantially better than typical models such as S8P8N, SAW16T, and RH20T. Under standard conditions (28 nm CMOS process, 1.0 V, 25 °C, TT corner), the RFWF16T achieves a Read Access Time (RAT) of 20.97 ps and a Write Access Time (WAT) of 2.72 ps. These values correspond to average speed improvements of 46.65% and 14.77%, respectively, over eight comparable hardened structures (Table 2). PVT analysis confirms that the RFWF16T maintains the lowest latency across voltages from 0.7 V to 1.1 V and temperatures from –25 °C to 125 °C (Fig. 6). This write-speed advantage is attributed to the removal of write contention through optimized discharge paths. In terms of noise margin and stability, the RFWF16T demonstrates strong robustness and achieves the highest Write Word-line Toggle Voltage (WWTV) among nine comparative structures. Its Hold Static Noise Margin (HSNM) and Read Static Noise Margin (RSNM) also rank among the best, which ensures stability under disturbances (Fig. 7). In radiation hardening, the RFWF16T achieves a 100% self-recovery rate for SNUs and an 83.3% recovery rate for DNUs, reaching the state-of-the-art level among DNU-recoverable units (Table 1). Monte Carlo simulations confirm that the average recovery times of the internal nodes range from 1.09 ns to 1.19 ns (Fig. 4, Fig. 5). In terms of overhead, the RFWF16T maintains a normalized area of 1.00× (4.3 μm × 1.9 μm) (Table 3, Fig. 2) and an average power consumption of 23.45 nW (Table 4). Although the power consumption is slightly higher, this increase is a reasonable trade-off for the substantial speed advantage. In the EQM evaluation, the RFWF16T obtains the highest score, which confirms its overall advantage in balancing reliability, speed, and stability (Fig. 9). Conclusions A radiation-hardened SRAM cell, RFWF16T, is proposed for aerospace-grade high-speed read/write applications. The cell contains only two sensitive nodes and achieves 100% self-recovery for SNUs and an 83.3% recovery rate for DNUs, which demonstrates strong radiation tolerance. Compared with eight other SRAM cells, the RFWF16T significantly reduces read and write delay with only a slight increase in area and power consumption, while maintaining good noise immunity and the best electrical quality metric. PVT and Monte Carlo simulations further confirm the stability and robustness of the proposed cell under different operating conditions. Future work will focus on array-level integration and tape-out verification, and on its application in satellite-borne high-speed data processing.
- Static Random Access Memory (SRAM) /
- Radiation hardening /
- Single Node Upset (SNU) /
- Double Node Upset (DNU) /
- High-speed read/write access

HTML全文

图 1 RFWF16T电路原理图

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图 2 RFWF16T版图布局

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图 3 RFWF16T的读、写与保持波形图

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图 4 RFWF16T 受SNU影响后自恢复图

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图 5 RFWF16T单元SNU自恢复2 000次蒙特卡罗模拟

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图 6 读、写访问时间测试的PVT实验

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图 7 功耗测试的PVT实验

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图 8 不同SRAM的各类噪声容限比较

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图 9 不同SRAM的各电气质量度量(EQM)比较

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表 1 可靠性对比

SRAM单元	敏感节点数量	SNUR(%)	DNUR(%)	$ {\mathit{Q}}_{\mathrm{c}} $(fC)
S8P8N^[8]	2	100	83.3	90
QUCCE12T^[9]	4	100	0.0	21
SARP12T^[10]	3	100	58.3	75
SAW16T^[11]	2	100	83.3	90
HRLP16T^[12]	3	100	66.7	90
RH20T^[13]	2	100	83.3	90
S6P8N(18T)^[14]	3	100	66.7	90
S8P6N(18T)^[14]	3	100	66.7	90
RFWF16T	2	100	83.3	90

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表 2 标准测试下WAT与RAT对比

SRAM单元	RAT(ps)	WAT(ps)	PRCs(%)
SRAM单元	RAT(ps)	WAT(ps)	RAT	WAT
S8P8N^[⁸^]	25.36	2.88	–17.31	–5.42
QUCCE12T^[⁹^]	37.31	3.86	–43.80	–29.46
SARP12T^[¹⁰^]	83.06	2.88	–74.75	–5.46
SAW16T^[¹¹^]	48.85	3.05	–57.07	–10.73
HRLP16T^[¹²^]	31.65	3.45	–33.74	–21.25
RH20T^[¹³^]	31.73	2.96	–33.91	–8.08
S6P8N(18T)^[¹⁴^]	46.89	3.34	–55.28	–18.59
S8P6N(18T)^[¹⁴^]	49.15	3.37	–57.33	–19.19
RFWF16T	20.97	2.72	–46.65(平均)	–14.77(平均)

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表 3 SRAM单元的归一化面积对比

SRAM单元	相对面积
S8P8N^[8]	1.01X
QUCCE12T^[9]	0.76X
SARP12T^[10]	0.75X
SAW16T^[11]	1.31X
HRLP16T^[12]	0.99X
RH20T^[13]	1.25X
S6P8N(18T)^[14]	1.12X
S8P6N(18T)^[14]	1.13X
RFWF16T	1.00X

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表 4 标准测试下SRAM平均功耗对比

SRAM单元	平均功耗(nW)
S8P8N^[8]	58.83
QUCCE12T^[9]	31.44
SARP12T^[10]	20.53
SAW16T^[11]	18.84
HRLP16T^[12]	28.56
RH20T^[13]	20.87
S6P8N(18T)^[14]	19.15
S8P6N(18T)^[14]	26.31
RFWF16T	23.45

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