一种基于扇出重汇聚的可测性评估方法

吴文俊; 梁华国; 游畅; 窦贤锐; 肖家辉; 鲁迎春

doi:10.11999/JEIT251286

一种基于扇出重汇聚的可测性评估方法

doi: 10.11999/JEIT251286 cstr: 32379.14.JEIT251286

合肥工业大学微电子学院合肥 230601

基金项目: 国家重大科研仪器研制项目(62027815)，国家自然科学基金资助项目(62174048, 62274052)

详细信息

作者简介:
吴文俊：男，硕士，研究方向为集成电路测试

梁华国：男，教授，研究方向为容错计算与硬件安全

游畅：男，硕士，研究方向为集成电路硬件安全技术

窦贤锐：男，博士生，研究方向为集成电路测试

肖家辉：男，硕士，研究方向为集成电路测试

鲁迎春：男，副教授，研究方向为集成电路硬件安全技术

通讯作者:
梁华国　huagulg@hfut.edu.cn

中图分类号: TN407
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出版历程
- 收稿日期: 2025-12-03
- 修回日期: 2026-03-09
- 录用日期: 2026-03-09
- 网络出版日期: 2026-03-22

A Testability Evaluation Method Based on Reconvergent Fan-out

School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: The National Major Research Instrument Development Project (62027815), The National Natural Science Foundation of China Key Project (62174048, 62274052)

摘要

摘要: 随着电路规模和复杂度的不断提升，可测性分析已成为电路设计与测试阶段中评估电路质量与优化测试点配置的关键环节。然而，现有方法在处理信号相关性与扇出重汇聚结构时，普遍存在精度不足与计算开销较大的问题，难以兼顾效率与准确性。为此，该文提出一种基于扇出重汇聚的可测性评估方法。该方法通过解析电路拓扑识别扇出重汇聚区域，构建结构相关的加权可测性计算模型，并实现了高效的可测性分析算法框架，以在保证精度的同时提升计算效率。实验结果表明，本文方法在可控性预测中均方根误差平均降低约25%，确保精度的同时，计算时间平均加速7倍，在故障覆盖率预测以及排序一致性检测中亦表现优异。
- 可测性测度 /
- 扇出重汇聚 /
- 故障覆盖率 /
- Controllability/Observability Procedure (COP)
Abstract: Objective As the scale and structural complexity of integrated circuits continue to increase, accurate testability evaluation has become essential for Trojan detection, fault diagnosis, and test-point optimization in modern Design-For-Testability (DFT) flows. Metrics such as controllability, observability, and fault coverage rely heavily on reliable probabilistic modeling of signal propagation. However, existing analytical and learning-based approaches often exhibit degraded accuracy in circuits containing dense Reconvergent Fan-Out (RFO) structures, where strong signal correlation invalidates classical independence assumptions and introduces significant estimation bias. Although several enhanced techniques attempt to incorporate structural information, many suffer from high computational cost or limited scalability when applied to deeper or more reconvergent logic networks. This work aims to address these limitations by proposing a testability evaluation method that incorporates RFO structural characteristics to improve modeling accuracy while maintaining practical computational efficiency. Methods The proposed approach begins with a structural-analysis algorithm that identifies RFO regions through a topological traversal of the circuit. A dedicated RFO-recognition mechanism maps each root fan-out node to its corresponding reconvergent fan-out nodes, capturing the structural dependencies that govern correlated signal behavior and providing the foundation needed for accurate probabilistic modeling. Building on this structural extraction, a weighted conditional-probability model is formulated to correct testability distortion within reconvergent regions. Unlike prior optimization schemes, the weighting strategy assigns influence-based weights derived from the contribution of each root node to the target node, yielding probability estimates that better reflect real testability behavior. Furthermore, an efficient computational framework is developed, integrating conditional probability propagation and weight selection within a single topological-traversal process, thereby maintaining low algorithmic complexity while enhancing accuracy. Results and Discussions The proposed method is evaluated on representative benchmark circuits from the ISCAS-85, ISCAS-89, ITC’99 , and EPFL suites. Performance is assessed in terms of controllability accuracy, ordering consistency, fault-coverage estimation, and runtime efficiency. For controllability prediction, the method achieves an average RMSE of 0.0568, corresponding to an average reduction of 25% compared with existing techniques, as reported in Table 2. Ordering consistency also improves, with the average Spearman correlation coefficient reaching 0.935, outperforming existing techniques. Fault-coverage estimation demonstrates similarly strong performance, with an average relative error of 3.64%, which is lower than previously reported methods, as shown in Table 1. Runtime analysis further indicates that the proposed framework maintains practical computational efficiency. Across all benchmark circuits, the method achieves an average speedup of 7× while preserving high accuracy, as illustrated in Figure 5. Conclusions This work addresses the degra dation of testability-evaluation accuracy caused by reconvergent fan-out structures in integrated circuits by proposing a reconvergent-fan-out-aware testability analysis method. The presented RFO-structure identification algorithm extracts reconvergent information at the topology level and establishes explicit mappings between root nodes and reconvergent fan-out nodes. Based on this structural foundation, a weighted conditional-probability model is constructed to mitigate probability distortion induced by signal correlation in RFO regions. An efficient computational framework is further developed to integrate the entire computation within a streamlined traversal-based process. Experimental results demonstrate that the proposed technique achieves accurate fitting of controllability RMSE and ordering consistency with respect to simulation-based ground truth. In testability estimation, the predicted fault-coverage values also match simulation results closely. While maintaining high accuracy, it also exhibits low computational overhead.
- Testability Measurement /
- Reconvergent Fan-out /
- Fault Coverage /
- Controllability/Observability Procedure (COP)

HTML全文

图 1 COP算法计算规则

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图 2 扇出重汇聚结构示意图

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图 3 基于扇出重汇聚的可测性评估方案流程图

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图 4 双扇出重汇聚情况分析

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图 5 CPU运行时间对比图

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Algorithm 1: Find_RFO_structure
INPUT：sorted_list - circuit nodes in topological order
OUTPUT：RFO_info - identified RFO information
for each node v in sorted_list do
if fan-out >1 then 　　　/* find candidate root node*/
create struct_info(v) 　/set S_i/
else if struct_info(v) repeat then 　　/candidate RFON/
create candidate root set RS_v 　　/set RS_i/
for each root r in RS_v do
if struct_info(r) ∩ RS_v is not empty then
delete r from RS_v 　　　/* follow rule 1*/
for each RFON r in node v RFO structure do
if RS_r ∩ struct_info(v) is not empty then
add r into RS_v 　　　　/* follow rule 2*/
propagate_struct_info(v)
return RFO_info

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Algorithm 2: RFO_based_testability_computation
INPUT：sorted_list - circuit nodes in topological order 　　　　　RFO_info - identified RFO information
OUTPUT：controllability C(v) and observability O(v)
for each node v in sorted_list do /calculate controllability/
if v is a primary input then
C(v) ← 0.5 /initialize primary input/
else if v is RFON then
C(v) ← RFON_based_ctrl_cal(v) /follow formula 6/
else
C(v) ← cop_ctrl_calculate(v) /follow rules of Fig. 1/
create/propagate conditional_probability_info(v)
for each node v in invert_sorted_list do /calculate 　observability/
if v is a primary output then
O(v) ← 1 /initialize primary output/
else if v is in RFO structure then
O(v) ← RFON_based_obsv_cal(v) /follow formula 6/
create/propagate conditional_probability_info(v)
else
O(v) ← cop_obsv_calculate(v) /follow rules of Fig. 1/
return {C(v), O(v)} for all v

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表 1 电路基本信息及故障覆盖率相对误差对比表

Circuit	Gate_numb	Max_numb	Fault_coverage(%)	FC_RE(%)
Circuit	Gate_numb	Max_numb	Fault_coverage(%)	[5]	[7]	[12]	RFO
s1238	631	16	94.29	0.79	0.87	1.62	0.85
s3384	1868	3	92.71	1.19	1.22	0.9	1.52
s9234	6173	20	82.16	1.75	2.75	11.12	0.5
s13207	9262	35	91	2	0.87	0.18	0.64
s35932	17793	2	89.25	1.95	2.19	3.14	2.23
s38584	22764	17	93.01	1.13	1.58	1.63	0.01
c1355	1038	33	96.88	2.86	2.81	3.1	2.43
c6288	4544	3	99.37	0.63	0.63	0.63	0.08
b14	10926	67	87.08	18.42	1.37	4.55	0.36
b17	36897	37	69.78	13.98	13.76	15.93	13.12
b18	85724	101	75.95	1.09	2.16	21.04	2.17
b21	22545	69	87.39	18.71	0.52	2.67	0.31
adder	1279	3	89.18	12.13	12.13	12.1	12.13
arbiter	6743	8	35.15	11.93	12.13	19.23	10.63
dec	309	0	98.32	1.71	1.71	1.71	1.71
max	3350	6	47.72	4.84	4.83	3.6	7.37
voter	13698	8	94.49	5.81	5.81	5.8	5.82
Average				5.94	3.96	6.41	3.64

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表 2 可控性值RMSE与斯皮尔曼系数对比表 (%)

circuit	RMSE−30%−only				ρ
circuit	[5]	[7]	[12]	RFO	[5]_ρ	[7]_ρ	[12]_ρ	RFO_ρ
s1238	0.0127	0.0073	0.0570	0.0086	0.9956	0.9962	0.9578	0.9968
s3384	0.0303	0.0192	0.0354	0.0187	0.8832	0.8990	0.7877	0.9144
s9234	0.0311	0.0183	0.1894	0.0200	0.8480	0.8758	0.4102	0.8732
s13207	0.0408	0.0250	0.2164	0.0245	0.8481	0.8692	0.2600	0.8858
s35932	0.0595	0.0437	0.0651	0.0378	0.8223	0.8615	0.7983	0.8663
s38584	0.0278	0.0160	0.1141	0.0169	0.9396	0.9601	0.7741	0.9680
c1355	0.0644	0.0439	0.1196	0.0218	0.9179	0.9424	0.8795	0.9474
c6288	0.0984	0.0719	0.1958	0.0470	0.8511	0.8969	0.5078	0.9630
b14	0.0433	0.0410	0.0624	0.0409	0.9444	0.9447	0.9272	0.9452
b17	0.0193	0.0189	0.0737	0.0189	0.9754	0.9763	0.9034	0.9773
b18	0.0434	0.0278	0.079	0.0414	0.9663	0.9806	0.9201	0.9712
b21	0.0491	0.0425	0.0599	0.0442	0.9340	0.9407	0.9227	0.9400
adder	0.0337	0.0204	0.0532	0.0015	0.8967	0.9013	0.8647	0.9265
arbiter	0.0053	0.0045	0.0185	0.0034	0.9902	0.9894	0.9782	0.9889
dec	0.5216	0.5216	0.5194	0.5216	1.0000	1.0000	0.8688	1.0000
max	0.0294	0.0206	0.0371	0.0184	0.9059	0.9170	0.8925	0.9178
voter	0.0935	0.0824	0.0744	0.0796	0.7811	0.8033	0.8609	0.8132
Average	0.0708	0.0603	0.1159	0.0568	0.9118	0.9267	0.7949	0.935

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