基于反向编程策略的高并行高精度RRAM存算一体芯片

谢力凡; 卫松涛; 姚鹏; 伍冬; 唐建石; 钱鹤; 高滨; 吴华强

doi:10.11999/JEIT251174

基于反向编程策略的高并行高精度RRAM存算一体芯片

doi: 10.11999/JEIT251174 cstr: 32379.14.JEIT251174

谢力凡¹,
卫松涛¹,
姚鹏^1, ,,
伍冬¹,
唐建石¹,
钱鹤¹,
高滨¹,
吴华强¹

清华大学集成电路学院，北京信息科学与技术国家研究中心北京 100084

基金项目: 国家自然科学基金(项目编号：92064001, 62025111)

详细信息

作者简介:
谢力凡：男，硕士，研究方向为存算一体电路设计

卫松涛：男，博士，研究方向为存算一体电路设计

姚鹏：男，副研究员，研究方向为存算一体芯片与系统

伍冬：男，副研究员，研究方向为图像传感器和非挥发性存储器等阵列式电路系统设计技

唐建石：男，副教授，研究方向为新型存储器件与集成工艺

钱鹤：男，教授，研究方向为新型存储与计算技术

高滨：男，教授，研究方向为新型存储与计算系统

吴华强：男，教授，研究方向为新型存储与计算技术

通讯作者:
姚鹏　pyao@mail.tsinghua.edu.cn

中图分类号: TP333.5
计量
- 文章访问数: 21
- HTML全文浏览量: 9
- PDF下载量: 2
- 被引次数: 0
出版历程
- 修回日期: 2026-02-06
- 录用日期: 2026-02-06
- 网络出版日期: 2026-02-28

A fast and accurate programming strategy for analog in-memory computing validated with a transposable RRAM macro and 0.64% fully-parallel RMS error

School of Integrated circuits, BNRist, Tsinghua University, Beijing 100084, China

Funds: NSFC (92064001, 62025111)

摘要

摘要: 推理大模型等人工智能的发展需要高能效、高算力芯片RRAM(阻变随机存取存储器)存算一体技术可以克服传统架构的“存储墙”瓶颈，大幅降低数据搬移的开销，实现高速、低功耗智能计算。当前，RRAM存算一体技术缺乏适配计算的高速、高精度编程方法，传统编程策略面临单器件校验耗时长以及电路非理想因素带来的精度损失挑战。为了提升RRAM高并行度模拟存算一体(CIM)的编程速度并提高权重编程精度，本文提出一种新型系统化编程策略：利用双向矩阵向量乘法(MVM)检测映射故障，并引入基于权重冗余行的原位偏移补偿方案，以高效校准不同通道的偏移。基于上述策略，制备了包含640×256子阵列与双通道ADC的RRAM存算一体芯片。在4位输入、4位权重、8位输出的配置下，该宏单元实现了编程延迟降低4倍，且在全并行MVM计算中取得0.64%的最低均方根(RMS)误差，提出的编程方法在图像识别任务中将识别准确率分别提升了4.7%和4.8%。
- RRAM /
- 存算一体编程策略 /
- 反向计算
Abstract: Objective Non-volatile-memory (NVM) based compute-in-memory (CIM) is a promising candidate for next-generation AI accelerators owing to its high energy efficiency and instant wake-up capability[1–3]. However, the conventional write-and-verify (W&V) scheme cannot satisfy the speed or precision requirements of highly parallel CIM macros. The bottleneck stems from the inefficient verification step: cell-by-cell reading is repeated for the entire array, and the switching from the “verify” state (only one row active) to the “compute” state (all rows active) introduces systematic errors such as reference drift and IR-drop-induced weight inaccuracy. Moreover, analogue CIM macros with on-chip programming must tolerate large and non-uniform offsets under massive parallelism.In this work we propose:1. A back-propagation-assisted programming (BPAP) scheme that rapidly and accurately locates failing cells without full-array verification.2. An analogue-domain offset-cancelling structure (AOSC) that in-situ compensates channel-wise offsets.3. A transposable RRAM macro equipped with parallel two-channel current-domain ADCs (TC-ADC) that doubles the effective sampling rate with only 15 % ADC-area overhead. Methods As shown in Fig. 2, the transposable RRAM macro consists of two processing elements (PE) and a shared backward-processing ADC (BP-ADC). Each PE includes one set of input loader (IL), a DAC array, BL buffer & switch array, and 32 TC-ADCs, supporting a fully parallel forward calculation. Additionally, an error loader (EL) and SL buffer are included to feed in an error input vector for transposed MVM. Figure 3 presents the flow diagram of the BPAP scheme. The forward calculation is firstly performed after AOSC. Subsequently, differences between the expected outputs (yexp) and experimental outputs (yreal) are computed on chip and used as inputs for following backpropagation phase. Then the derivatives of RRAM weight are calculated after feeding a few validation patterns. This training-like scheme could adapt to real RRAM states and detect the failures in high-parallelism computing state. The weights whose derivatives exceed the error threshold are selected to be remapped. This scheme enables accurate programming while avoiding the cell-by-cell verification over the entire array. In the forward phase (Fig. 4a), the 2T2R cell is configured as a signed weight, with SLs clamped at VCM by TC-ADCs. For each PE, a fully-parallel (active 320 rows of 2T2R) 4b-IN/4b-W MVM is completed with 32 ADCs converting simultaneously. In the backward phase (Fig. 4b), only the upper half part of the reference voltages is selected to drive SL buffers and the weight is configured as 1T1R mode. The differential calculation regarding the positive 1T1R and negative 1T1R is conducted by external processer. Fig.5 shows that in AOSC scheme, the redundancy rows in a RRAM array can be programmed to directly compensate the offset of the analog computing in an in-situ manner. The offset currents are obtained by applying an all-zero pattern to the regular weights. The redundancy RRAM weights are programmed to minimize the offset currents under a constant input voltage. Afterwards, these well-written redundancy weights are fed with the same input voltage under computing mode. The macro supports this AOSC mode with only extra 1% overhead of array area. Fig. 6 presents the structure the TC-ADC. Adding one class AB output stage and associated switches and capacitors enables this two-channel conversion to halve the computing latency. Meanwhile, this only consumes extra 15% ADC area to achieve 2× sampling rate. Conclusions We demonstrate that replacing traditional W&V with BPAP, augmented by AOSC and TC-ADC, enables reliable, high-precision programming of analogue RRAM-CIM macros under massive parallelism. The measured 96.5 % MNIST accuracy and 4.8 % ImageNet improvement validate the approach. The proposed techniques are compatible with standard 2T2R/1T1R RRAM bit-cells and are readily extendable to larger arrays and deeper neural networks.
- RRAM /
- Programming strategy /
- Inverse computation

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图 2 单器件校验忆阻器存算一体编程方案流程

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图 1 RRAM-CIM 结构

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图 3 BPAP流程图

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图 4 (a)正向计算和 (b) 反向计算下示意图

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图 5 AOSC阵列

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图 6 TC-ADC的结构和工作原理

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图 7 (a)芯片照片 (b)区域占比

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图 8 (a)MVM结果 (b)有无BPAP的标准差均方根差(c)编程延迟对比(d)有无AOSC偏移(e)网络精度

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图 9 芯片整体概述和性能

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表 1 与同类项目的对比

方法	本项目	VLSI[15]	ISSCC 2022[16]	ISSCC 2023[17]
工艺	110nm	14nm	22nm	22nm
年份	2024	2021	2022	2023
计算域	电流	电流	电荷	电流
支持反向传播	是	否	否	否
存算器件	模拟RRAM	模拟PCM	SLC-PCM	SLC/MLC RRAM
输入	4位电压	串行脉冲	位串行	位串行
并行度	640	256	8	16-128
输入 / 权重精度	4/8	8	8	4/8
电源电压	1.5	0.8	0.8	0.7-0.8
阵列吞吐量(TOPS)	1.365 \| 0.341	1.008	0.004	0.843 \| 0.257
阵列容量(K)	160(640×256)	252(256×1024)	256(1024×256)	1024(1024×1024)
能效(TOPS / W)	10.410 \| 2.603	2.480	21.600	241.800 \| 67.200
标准偏差	标准偏差：1.16%σ	标准偏差：1.94%σ
均方根误差	均方根误差：0.59%	均方根误差：1～2%

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