面向云网融合环境的网络模态报文处理柔性流水线构建机制

朱俊; 徐琪; 张富军; 王永杰; 邹涛; 隆克平

doi:10.11999/JEIT250806

面向云网融合环境的网络模态报文处理柔性流水线构建机制

doi: 10.11999/JEIT250806 cstr: 32379.14.JEIT250806

之江实验室高效能计算设施研究中心，浙江，杭州 311121

基金项目: 国家自然科学基金项目(U22A2005)，浙江省重点研发计划项目(2024SSYS0001)

详细信息

作者简介:
朱俊：男，高级工程师，研究方向为新型网络体系结构、软件定义网络、高性能集群网络、网络资源管理等

徐琪：男，副研究员，研究方向为多模态网络、软件定义网络、时间敏感网络等

张富军：男，工程师，研究方向为网络可编程、多模态网络编译技术等

王永杰：男，工程师，研究方向为网元操作系统、网络编译技术等

邹涛：男，研究员，研究方向为多模态网络技术和新型网络体系架构等

隆克平：男，教授，研究方向为新一代网络技术、光互联网关键技术、无线通信技术、人工智能与大数据等

通讯作者:
隆克平　longkeping@ustb.edu.cn

中图分类号: TP393
计量
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- HTML全文浏览量: 10
- PDF下载量: 2
- 被引次数: 0
出版历程
- 收稿日期: 2025-08-27
- 修回日期: 2025-11-03
- 录用日期: 2025-11-03
- 网络出版日期: 2025-11-11

Flexible Network Modal Packet Processing Pipeline Construction Mechanism for Cloud-Network Convergence Environment

Research Center for High Efficiency Computing Facilities, Zhejiang Lab, Hangzhou 311121, China

Funds: National Natural Science Foundation of China (U22A2005), Key R&D Program of Zhejiang (2024SSYS0001)

摘要

摘要: 随着云网融合技术的发展，多样化的网络业务需求催生了对多模态网络报文柔性化处理的需求。本文提出了一种基于多模态网元抽象模型与前-中-后端三段式编译架构的协议报文柔性化处理编译机制，通过中间表示切片算法将多种网络模态混合的处理逻辑拆解并映射至ASIC、FPGA、CPU等异构硬件资源上，构建支持自定义配置的柔性流水线以适应不同的网络业务传输要求。本文详细介绍该架构的设计理念、中间表示结构及中间表示切片算法，并验证所提出的柔性流水线在构造效果和功能满足方面的优越性。实验表明，该机制能构建从1段到5段等多种流水线样式，在原型系统上实现的多模态处理流水线平均延迟最低可达15.48us。因此，该机制能够有效提升网络服务的灵活性和效率，为超融合云网环境下的网络报文处理提供了新的思路。
- 多模态网络 /
- 协议报文处理 /
- 网络可编程 /
- 网络资源分配和编排
Abstract: Objective With the deep integration of information network technologies and vertical application fields, the demand for cloud-network convergence infrastructure has become increasingly prominent, and the boundaries between cloud computing and network technologies are becoming more blurred. The development of cloud-network convergence technologies has given rise to diverse network service requirements, further posing new challenges for the flexible processing of multi-modal network packets. The device-level network modal packet processing flexible pipeline construction mechanism is key to realizing an integrated environment that supports a variety of network technologies. This mechanism constructs a protocol packet processing flexible pipeline architecture that, based on different network modals and service demands, customizes a series of protocol packet processing operations, including packet parsing, packet editing, and packet forwarding, thus improving the adaptability of networks in cloud-network convergence environments. This flexible design allows the pipeline processing flow to be adjusted according to actual service demands, meeting the functional and performance requirements of different network transmission scenarios. Methods The construction of a device-level flexible pipeline faces two major challenges: (1) how to flexibly process diverse network modal packet protocols based on polymorphic network element devices, requiring coordination of various heterogeneous resources to quickly identify, parse, and correctly handle network modal packets in various formats; (2) how to ensure that the pipeline construction is flexible, providing a mechanism to dynamically generate and configure pipeline structures. This mechanism should not only adjust the number of stages in the pipeline but also allow customization of the specific functions of each stage. To address these challenges, this paper proposes a polymorphic network element abstraction model that integrates heterogeneous resources. It employs a hyper-converged approach using high-performance switching ASIC chips paired with more programmable but slightly weaker FPGA and CPU devices at the device-level hardware architecture layer. Through the synergy of hardware and software, it meets the flexibility demands for unified support of custom network protocols. On the basis of the network element abstraction model, a protocol packet flexible processing compilation mechanism is further designed, constructing a flexible pipeline architecture that supports customizable configurations to accommodate different network service transmission requirements. It is a front-end, mid-end, back-end three-stage compilation architecture. At the same time, in response to the adaptive issues between differentiated network modal demands and heterogeneous resources, a flexible pipeline technology based on IR slicing is proposed. This approach precisely decomposes and reconstructs the integrated IR of multiple network modals into several IR subsets according to specific optimization methods, ensuring the original functionality and semantics, thus enabling flexible customization of the network modal processing pipeline through collaborative handling of heterogeneous resources. By utilizing an intermediate representation slicing algorithm, this mechanism decomposes and maps hybrid processing logic of multiple network modalities onto heterogeneous hardware resources such as ASICs, FPGAs, and CPUs, thereby constructing a custom-configurable flexible pipeline that adapts to various network service transmission requirements. Results and Discussions To demonstrate the construction effect of the flexible pipeline, this paper introduces a prototype verification system for polymorphic network elements. As shown in Fig. 6, the system is equipped with Centec CTC8180 switch chips, multiple domestic FPGA chips, and domestic multi-core CPU chips. On this polymorphic network element prototype verification system, protocol processing pipelines for IPv4, GEO, and MF network modals were constructed, compiled, and deployed. As shown in Fig. 7, actual packet capture tests have verified that different network modals use different packet processing pipelines. To validate the core mechanism of network modal flexible pipeline construction, we compared the IR code size before and after slicing under the three network modals and network modal allocation strategies in Section 6.2. The integrated P4 code for the three network modals, after front-end compilation, produced an unsliced intermediate code of 32,717 lines. According to the modal allocation scheme, slicing was performed during the middle-end compilation stage, resulting in IR slices for ASIC, CPU, and FPGA with code sizes of 23,164, 23,282, and 22,772 lines, respectively. Finally, the performance of multi-modal protocol packet processing was evaluated, focusing on the impact of different traffic allocation schemes on the network modal protocol packet processing performance. According to the experimental results in Fig. 9, it can be observed that the average packet processing delay for Scheme 1 is significantly higher than the other schemes, reaching 4.237 milliseconds. In contrast, the average forwarding processing delay for Schemes 2, 3, and 4 decreased to 54.16 microseconds, 32.63 microseconds, and 15.48 microseconds, respectively. This shows that with changes in the traffic allocation strategy, especially the adjustment of CPU resources for GEO and MF modals, network packet processing bottlenecks can be effectively reduced, thereby significantly improving multi-modal network communication efficiency. Conclusions Experimental evaluations confirm the superiority of the proposed flexible pipeline in terms of construction effects and functional fulfillment. The results show that the proposed method can effectively address complex network environments and diverse service demands, demonstrating strong performance. Future work will further optimize this architecture and expand its applicability, aiming to provide more powerful and flexible technical support for network packet processing in hyper-converged cloud-network environments.
- Polymorphic networks /
- Protocol packet processing /
- Network programmability /
- Network resource allocation and orchestration

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图 1 多模态网元抽象模型

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图 2 网络模态报文处理柔性流水线构建架构

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图 3 报文处理流水线构建与中间表示IR切片机制

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图 4 中间表示IR的数据结构

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图 5 网络资源可编程能力描述模型

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图 6 多模态网元原型验证系统

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图 7 多种网络模态协议报文处理流水线运行效果

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图 8 切片前后IR代码量对比图

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图 9 不同流量分配方案下的多模态协议报文处理性能评估

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图 10 在同一个流量分配方案下不同报文长度的多模态协议报文处理性能评估

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表 1 多段式网络模态报文处理柔性流水线设计

序号	流水线段数	流水线通路	优缺点分析
1	1	ASIC	速度快，报文解析转发功能相对固定
2	3	ASIC→FPGA_m→ASIC	速度较快，具备一定灵活性
3	3	ASIC→CPU_n→ASIC	速度较慢，灵活性高
4	4	ASIC→FPGA_m→CPU_n→ASIC	速度较慢，灵活性高
5	4	ASIC→CPU_n→FPGA_m→ASIC	速度较慢，灵活性高
6	5	ASIC→FPGA_m→CPU_n→FPGA_m→ASIC	速度慢，灵活性较高
7	5	ASIC→FPGA_m→CPU_n→FPGA_m’→ASIC	速度慢，灵活性较高，可利用资源更多
8	5	ASIC→CPU_n→FPGA_m→CPU_n→ASIC	速度慢，灵活性较高
9	5	ASIC→CPU_n→FPGA_m→CPU_n’→ASIC	速度慢，灵活性较高，可利用资源更多
10	1+2i或1+3i(i≥1)	ASIC→i·(CPU_n\|FPGA_m\|(CPU_n→FPGA_m)\|(FPGA_m→ CPU_n) → ASIC →)	更一般化的流水线阶段表示

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表 2 模态中间表示IR中的control单元切片处理模块算法

1 control单元切片处理模块()
2 {
3 　for (auto i : 模态条件判断模块集合){
4 　　　···.
5 　　　auto cond = new 　　　　　IR::IndexedVector<IR::StatOrDecl>；
6 　　　element = element_extract(); //模态条件判断模块，　　　　　模态标识要素提取
7 　　　if (true == check_element(element)) //模态标识要素　　　　　校验
8 　　　　ans = element_match(element) //模态标识要素匹配
9 　　　　if (true == ans)
10 　　　　　cond = push_back(i); //保留此模态条件判断模块
11 　　else
12 　　　　　切片删除此模态条件判断模块
13 　else
14 　continue; //要素不合法，跳出循环
15 　 ···.
16 }
17 refresh_node(cond); //模态条件判断模块集更新
18 return;
19 }

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表 3 IR切片测试和代码量情况

网络模态	模态分配策略	切片前网络模态 IR代码量 (multimodal_mix.ir)	切片后各个芯片IR 切片代码量
网络模态	模态分配策略	切片前网络模态 IR代码量 (multimodal_mix.ir)	ASIC 切片 (asic.ir)	FPGA 切片 (fpga.ir)	CPU 切片 (cpu.ir)
IPv4	ASIC	32717	23164	22772	23282
GEO	CPU
MF	FPGA

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表 4 多模态协议报文处理性能评估(128B报文长度)

模态组合	切片策略	流量分配方案
模态组合	切片策略	方案1	方案2	方案3	方案4
IPv4	ASIC	100 Mbps	200 Mbps	300 Mbps	400 Mbps
GEO	CPU	200 Mbps	150 Mbps	100 Mbps	50 Mbps
MF	CPU	200 Mbps	150 Mbps	100 Mbps	50 Mbps
平均报文处理延迟时间		4237 μs	54.16 μs	32.63 μs	15.48 μs

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