面向芯粒互连的单端64 Gb/s全双工收发机设计

王知非; 黄之闻; 叶天辰; 叶秉奕; 李芳竹; 王玮; 于敦山; 盖伟新

doi:10.11999/JEIT250506

面向芯粒互连的单端64 Gb/s全双工收发机设计

doi: 10.11999/JEIT250506 cstr: 32379.14.JEIT250506

王知非¹,
黄之闻¹,
叶天辰¹,
叶秉奕²,
李芳竹¹,
王玮^{1, 3},
于敦山¹,
盖伟新^{1, 3, ,}

1.
北京大学集成电路学院北京 100871
2.
华东师范大学通信与电子工程学院上海 200241
3.
北京集成电路高精尖创新中心北京 100871

基金项目: 北京市科技计划(Z221100007722019)

详细信息

作者简介:
王知非：男，博士生，研究方向为超高速收发机电路设计等

黄之闻：男，博士生，研究方向为超高速收发机电路设计等

叶天辰：男，博士生，研究方向为超高速收发机电路设计等

叶秉奕：男，青年研究员，研究方向为超高速收发机电路设计等

李芳竹：女，硕士生，研究方向为超高速收发机电路设计等

王玮：男，教授，研究方向为微系统集成与热管理技术等

于敦山：男，教授，研究方向为数字信号处理电路设计等

盖伟新：男，教授，研究方向为超高速收发机电路设计等

通讯作者:
盖伟新　wgai@pku.edu.cn

中图分类号: TN432
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- 被引次数: 0
出版历程
- 收稿日期: 2025-06-03
- 修回日期: 2025-07-24
- 网络出版日期: 2025-08-06

A 64 Gb/s Single-Ended Simultaneous Bi-Directional Transceiver for Die-to-Die Interfaces

1.
School of Integrated Circuits, Peking University, Beijing 100871, China
2.
School of Communication and Electronic Engineering, East China Normal University, Shanghai 200241, China
3.
Beijing Advanced Innovation Center for Integrated Circuits, Beijing 100871, China

Funds: Beijing Major Science and Technology Project (Z221100007722019)

摘要

摘要: 芯粒集成将多颗不同功能、工艺的芯粒封装在一起，为高性能芯片发展开辟了新的思路。芯粒间互连接口电路作为数据传输的纽带，其带宽密度、误码率和功耗对芯片算力、数据吞吐量等关键性能至关重要。针对带宽密度提升带来的信号反射、串扰等问题，该文提出了一种具备回波、近端串扰、远端串扰消除功能的全双工收发机电路，并基于28 nm工艺进行了流片验证。其利用全双工技术提升了单通道数据速率，利用动态阈值判决技术实现了双向收发信号分离、回波与近端串扰消除，利用信道间容性与感性耦合的平衡实现了远端串扰消除。此外，延时匹配的源同步时钟结构降低了时钟相对数据抖动、提升了噪声容限，驻波与重置信号传输电路实现了发送信号的同步，提高了近端串扰消除精度。测试结果表明，在3 mm长的无屏蔽互连信道上，此收发机可以64 Gb/s的单通道速率、10.5 Tb/s/mm的带宽密度，实现低于10^–16的误码率，能效为1.21 pJ/b。
- 芯粒互连 /
- 收发机 /
- 全双工 /
- 串扰消除
Abstract: Objective Chiplet technology, which packages multiple dies with different functions and processes together, offers a cost-effective way for fabricating high-performance chips. For die-to-die data transmission, the edge density, Bit Error Rate (BER), and power consumption of the interface are crucial to the chip’s key performance metrics, such as computing power and throughput. Simultaneous Bi-Directional (SBD) signaling is an effective way to double the edge density by transmitting and receiving data on the same channel. However, with higher data rate and smaller channel pitch, channel reflection and crosstalk bring severe challenges to the design of interface circuits. This paper presents a single-ended SBD transceiver with echo and crosstalk cancellation to achieve a larger edge density and a lower BER. Methods The transceiver improves the per-wire data rate by utilizing the SBD signaling and denser shield-less channels. However, as both ends of the channel transmit data simultaneously, bi-directional signal coupling arises. Signal coupling, echo from impedance mismatch, and crosstalk from adjacent channels degrade the received data’s Signal-to-Noise Ratio (SNR). To decouple the bi-directional signal and cancel the echo and Near-End Crosstalk (NEXT), this paper proposes a Dynamic Voltage ThresHold generator (D-VTH). It generates the slicer’s threshold voltage according to the interfering signals needing to be subtracted. To cancel the Far-End Crosstalk (FEXT), a channel with the same capacitive and inductive coupling is designed by adjusting its width and space. FEXT is the subtraction of these two kinds of coupling, so it is canceled as expected. The source-synchronize architecture enhances the clock-data tracking performance, thereby reducing the clock-to-data jitter to improve the link’s noise margin. The synchronous clock distribution circuit includes a standing wave-based half-rate clock (CK2) distribution and a delay-controlled reset chain. The end of the CK2’s Transmission Line (TL) is terminated by a dedicated inductor, making the reflected wave have a proper amplitude and phase relative to the incident wave; thus, a standing wave can be formed, and CK2 synchronization is realized. To ensure the divided clocks (up to 1/32-rate) are synchronous, the dividers’ reset signals must be released at the same time or skewed with an integer multiple of 32 Unit Interval (UI). A reset chain is proposed to release the reset signals with controlled delay. The delay increases by 2 UI at each lane and is compensated by different stages of DFFs. After the CK2 and the divided clocks’ synchronization, the transmitter’s output and NEXT cancellation synchronization are achieved. Results and Discussions The test chip, including the proposed transceiver and the 3 mm on-chip channel, is fabricated in 28 nm CMOS. The shield-less data channels are routed in the M9 layer, with a channel pitch of 6.1 um. An electromagnetic field solver calculates the channel’s frequency response and the equivalent lumped model. The equivalent $ {C}_{\mathrm{m}}/{C}_{\mathrm{s}} $ is 0.28, and the $ {L}_{\mathrm{m}}/{L}_{\mathrm{s}} $ is 0.26, making FEXT 24 dB smaller than the Insertion Loss (IL) at the Nyquist frequency. In contrast, NEXT and Return Loss (RL) are much larger; they are just 7.3 dB and 8.3 dB smaller than the IL at the Nyquist frequency, respectively (Fig.12). The D-VTH filter’s coefficients are obtained from the Sign-Sign Least Mean Square (SS-LMS) adaptation algorithm, and the data is received correctly using the adapted coefficients. The bi-directional decoupling coefficient is the largest because the local transmitter’s output is the strongest compared to the echo and crosstalk. The echo cancellation coefficient is the smallest because it has to undergo additional insertion loss in the channel (Fig.13). The simulated clock-to-data tracking performance shows the transceiver’s robustness against power supply noise (Fig.15). The standing wave distribution’s simulation results show its amplitude is double that of the conventional traveling wave because of the superposition of incident and reflected waves. A slight skew of 0.6 ps is observed, caused by the residual traveling wave due to the TL’s loss (Fig.18). The measured internal eye diagrams and bathtub curves at 64 Gb/s shows the eye-opening is 0.68 UI/80 mV at 10^-9 BER and 0.64 UI/77 mV at 10^-12 BER, with both crosstalk cancellation and echo cancellation enabled (Fig.21). In addition, the measured BER at the optimal sampling point is less than 10^-16 with all the lanes counting bit errors. The Crosstalk-Induced Jitter (CIJ) is reduced from 0.58 UI to 0.06 UI after crosstalk cancellation is enabled, representing a reduction ratio of 89.6% (Table 1). The measured power efficiency is 1.21 pJ/b, and the simulated power breakdown shows that the transmitter, receiver, D-VTH, and clock distribution account for 40%, 23%, 34%, and 3%, respectively (Fig.22). This work achieves the best per-wire data rate and per-layer edge density compared with previous works (Table 2). Conclusions This paper utilizes SBD signaling and denser shield-less channels to achieve a per-wire data rate of 64 Gb/s and a per-layer edge density of 10.5 Tb/s/mm. The proposed echo and crosstalk cancellation circuit ensures an extremely low BER of less than 10^-16. It provides new insights for increasing the edge density of die-to-die interfaces.
- Chiplet interconnect /
- Transceiver /
- Simultaneous Bi-Directional (SBD) /
- Crosstalk cancellation

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图 1 源同步全双工互连系统结构

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图 2 动态阈值判决技术原理示意图

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图 3 相邻信道间串扰示意图

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图 4 延时匹配的源同步时钟结构

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图 5 单通道收发机电路结构

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图 6 DAC电路结构

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图 7 DAC输出线性度仿真

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图 8 不同线性度DAC仿真得到的眼图

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图 9 驱动器电路结构

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图 10 判决器电路结构

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图 11 判决器灵敏度随输入共模电压变化的曲线

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图 12 片上信道结构与频率响应

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图 13 FIR滤波器系数自适应仿真及系数稳定后的数据波形

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图 14 源同步时钟电路结构

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图 15 时钟-数据延时匹配与PSIJ仿真

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图 16 传统的时钟与分频重置信号传输电路

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图 17 通道间同步时钟传输电路结构

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图 18 驻波时钟传输电路的幅度与相位仿真

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图 19 D-VTH输出与NEXT对齐

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图 20 芯片显微照片与测试环境

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图 21 测得的片上误码率眼图、浴盆曲线

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图 22 仿真得到的功耗分解

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表 1 CIJ消除率计算

	w/o NEXT	w/ NEXT		CIJ		CIJ消除率
	w/o NEXTC	w/o NEXTC	w/ NEXTC	w/o NEXTC	w/ NEXTC	CIJ消除率
抖动峰峰值 (UI_pp)	0.30	0.88	0.36	0.58	0.06	89.6%

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表 2 芯粒互连收发机性能总结与对比

	ISSCC’20^[10]	JSSC’23^[14]	JSSC’23^[5]	JSSC’25^[6]	ISSCC’25^[22]	ISSCC’25^[23]	本文
工艺(nm)	65	28	5	3	3	3	28
数据速率 (Gb/s)	4	10	50.4	32	32	16	64
信号调制方式	NRZ	NRZ	NRZ / Bi-dir	NRZ	NRZ	NRZ	NRZ / Bi-dir
信道长度 (mm)	6	50.8	1.2	2	1.7	1.4	3
信道中心距 (μm)	1	236	–	–	–	–	6.1
信道间屏蔽需求	无	无	接地屏蔽	接地屏蔽	接地屏蔽	接地屏蔽	无
能效 (pJ/b)	1.5	1.29	0.297	0.36	0.6	0.29	1.21
带宽密度 (Tb/(s·mm))	8	0.035	2.14	7.68	10.5	5.27	10.5
数据走线层数	2	1	1	–	4	–	1
测试误码率	<1e-12	<1e-12	<1e-12	<1e-12	–	<1e-11	<1e-16^(a)
串扰消除方式 CIJ消除率	FIR 78%	Coding 45%	无	无	无	无	FIR 89.6%
回波消除方式	无	无	无	无	无	无	FIR
(a) 在最优采样点测得

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