处理器数据预取器安全研究综述

刘畅; 黄祺霖; 刘煜川; 林世鸿; 秦中元; 陈立全; 吕勇强

doi:10.11999/JEIT250412

处理器数据预取器安全研究综述

doi: 10.11999/JEIT250412 cstr: 32379.14.JEIT250412

1.
清华大学计算机科学与技术系北京 100084
2.
东南大学网络空间安全学院南京 211189
3.
清华大学北京信息科学与技术国家研究中心北京 100084

详细信息

作者简介:
刘畅：男，博士生，研究方向为处理器漏洞挖掘、处理器微架构侧信道攻击和处理器漏洞防御

黄祺霖：男，硕士生，研究方向为处理器安全

刘煜川：男，硕士生，研究方向为处理器安全

林世鸿：男，硕士生，研究方向为处理器安全

秦中元：男，副教授，主要研究方向为漏洞挖掘和无线网络安全

陈立全：男，教授，研究方向为网络安全、物联网安全等

吕勇强：男，副研究员，研究方向为处理器漏洞挖掘、处理器安全验证与设计和硬件安全

通讯作者:
吕勇强　luyq@tsinghua.edu.cn

中图分类号: TP309; TN402
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出版历程
- 收稿日期: 2025-05-13
- 修回日期: 2025-08-28
- 网络出版日期: 2025-09-02

A Survey of Data Prefetcher Security on Modern Processors

1.
Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
2.
School Of Cyber Science and Engineering, Southeast University, Nanjing 211189, China
3.
Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China

摘要

摘要: 数据预取器是现代处理器用于提高性能的重要微架构组件。然而，由于在设计之初缺乏系统性的安全评估与考量，主流商用处理器中的预取器近年来被揭示出存在严重安全隐患，已被用于针对浏览器、操作系统和可信执行环境的侧信道攻击。面对这类新型微架构攻击，处理器安全研究亟需解决以下关键问题：如何系统性地分析攻击方法，全面认识预取器潜在风险，量化评估预取器安全程度，从而设计更加安全的数据预取器。为解决这些问题，该文系统调研了商用处理器中已知预取器设计及相关侧信道攻击，通过提取内存访问模式，为7种预取器建立行为模型，并基于此为20种侧信道攻击建立攻击模型，系统整理了各类攻击的触发条件和泄露信息，并分析可能存在的其他攻击方法。在此基础上，该文提出1套包含3个维度和24个指标的安全性评估体系，为数据预取器的安全性提供全面量化评估。最后，该文深入探讨了防御策略、安全预取器设计思路及未来研究方向。作为首篇聚焦于商用处理器数据预取器安全问题的综述性文章，该文有助于深入了解数据预取器面临的安全挑战，推动预取器的安全性量化评估体系构建，从而为设计更加安全的数据预取器提供指导。
- 计算机体系结构 /
- 处理器 /
- 数据预取器 /
- 微架构安全 /
- 侧信道攻击
Abstract: Significance The data prefetcher is a key microarchitectural component in modern processors, designed to enhance memory access performance by speculatively preloading data into the cache based on predictions of future access patterns. While effective at reducing cache misses, prefetcher design has historically neglected security considerations, resulting in various forms of information leakage. Recent studies have shown that data prefetchers can be exploited in side-channel attacks targeting cryptographic libraries, operating systems, hypervisors, and trusted execution environments. However, most existing attacks focus on specific implementations (eg., "one-spot" attacks) fail to comprehensively capture the broader attack surface exposed by diverse prefetcher designs. Two fundamental research questions remain open: (1) Do current attacks fully characterize all exploitable vectors in modern prefetchers, or are additional vectors yet to be explored? (2) How can the security of different prefetcher designs be systematically and quantitatively assessed to support comparative analysis and guide secure design? This paper addresses both questions through a systematic survey of data prefetcher attacks and a model-driven analysis. By generalizing known attack mechanisms, this work proposes a formalized framework for understanding and evaluating the security of data prefetchers. Methods To capture the behavior of data prefetchers, this study first presents a memory access model that specifies the instruction address, data address, and access attributes for each memory operation, which can be extended to represent access sequences. Building on this, a prefetcher model is proposed in which a prefetcher is trained by a sequence of memory accesses and triggered by a single access to generate a set of prefetches. Each prefetcher is characterized by design parameters. Attacker and victim profiles are then incorporated to construct attack models based on reduced memory access representations, enabling formalization of 20 known prefetcher-based attacks. Finally, a security evaluation framework is proposed, comprising 24 metrics across three dimensions—design parameters, isolation, and attack feasibility. This framework supports quantitative scoring and comparison of prefetcher designs. Results and Prospects In terms of attack modeling, the analysis shows that the 20 known attacks cover only a limited portion of the overall attack space. This study proposes several previously unexplored attack vectors, including those that exploit cache hit effects and speculative execution, attacks that leverage indexing collisions using instruction and data addresses, and additional side channels resulting from prefetcher-induced effects on other microarchitectural components, such as Translation Lookaside Buffer (TLB) state and cache coherence state. In terms of evaluation, this paper examines five commercial processors featuring different prefetchers: Intel’s Stride prefetcher and eXtended Page Table (XPT), AMD’s Stride prefetcher, Arm’s Spatial Memory Streaming (SMS) prefetcher, and Apple’s Data Memory Prefetcher (DMP). The findings reveal that all five prefetchers exhibit varying degrees of vulnerability to side-channel leakage, depending on their design parameters, isolation strategies, and the feasibility of exploitation. The paper further assesses three mitigation strategies and shows that while some measures substantially enhance security, residual risks remain, highlighting the need for improved countermeasures. Discussion Beyond characterizing existing attack vectors and evaluating the security of current prefetcher implementations, this study also outlines emerging directions for secure prefetcher design. Existing work primarily focuses on the Stride prefetcher, with preliminary defenses based on control registers that allow software to constrain the address range eligible for prefetching. This reduces the likelihood that secret-dependent memory accesses affect prefetcher state or trigger the prefetching of sensitive cache lines. Nevertheless, these approaches remain at an early stage, and a comprehensive framework for the systematic design of secure prefetchers has yet to be developed. Conclusions This paper presents a systematic study of data prefetcher security. It proposes a model-driven framework for analyzing potential attack vectors and introduces a quantitative method for evaluating prefetcher security. These contributions lay a theoretical foundation for identifying new attack mechanisms, guiding the development of effective countermeasures, and informing the secure design of data prefetchers in future processor architectures.
- Computer Architecture /
- Processor /
- Data Prefetcher /
- Microarchitectural Security /
- Side Channel Attack

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图 1 数据预取器在现代处理器微架构中的位置和基本原理

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图 2

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图 3 基于内容和基于驱逐的数据预取器侧信道攻击示意图

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图 4 XX

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表 1 商用处理器中已发现数据预取器的关键设计参数，以及求解这些参数的相关工作

预取器	参数声明	参数定义
Next-line	$ {k}_{1} $: 跨页预取^[49]	$ {k}_{1}\in \left(\mathrm{0,1}\right) $, {$ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}\left(\left\langle a \right\rangle ,\left\langle a \right\rangle +1\right) $}: $ 0 $, $ a\to {k}_{1}(\left\langle a \right\rangle +1) $
Adjacent	$ {k}_{1} $: 预取策略^[36]	$ {k}_{1}\in \left(-\mathrm{1,1}\right) $, {$ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{c}\mathrm{h}\mathrm{u}\mathrm{n}\mathrm{k}(\left\langle a \right\rangle ,\left\langle a \right\rangle +1) $}: $ 0 $, $ a\to \left\langle a \right\rangle +{k}_{1} $
Stride	$ {k}_{1} $: 激活信心值^[32,36]	$ \left\lfloor{k}_{1}\right\rfloor $, {$ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}(a,s) $}: $ {\left[a\right]}_{{k}_{1},s},a+{k}_{1}s\to \left\langle a+({k}_{1}+1)s \right\rangle $
	$ {k}_{2} $: 步长范围^[30,32]	$ \left\\|{k}_{2}\right\\| $, {$ n\ge {k}_{1} $}: $ {\left[a\right]}_{n,s} $, $ a+n{k}_{2}\to \left\langle a+(n+1){k}_{2} \right\rangle $
	$ {k}_{3} $: 预取深度^[36]	$ \left\lceil{k}_{3}\right\rceil $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $}: $ {\left[a\right]}_{n,s} $, $ a+ns\to \left\langle a+(n+1){k}_{3} \right\rangle $
	$ {k}_{4} $: 非等步长预取行为^[30]	$ {k}_{4}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{c}\mathrm{l}(a+ns $, $ b) $}: $ {\left[a\right]}_{n,s} $, $ b\to {k}_{4}\left\langle b+s \right\rangle $
	$ {k}_{5} $: 单次预取数量^[36]	$ \left\\|{k}_{5}\right\\| $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $}: $ {\left[a\right]}_{n,s} $, $ a+ns\to \left\langle {[a+\left(n+1\right)s]}_{{k}_{5},s} \right\rangle $
	$ {k}_{6} $: 小步长预取数量^[38]	$ \left\\|{k}_{6}\right\\| $, {$ \mathrm{s}\mathrm{a}\mathrm{m}\mathrm{e}\_\mathrm{c}\mathrm{l}\left({\left[a\right]}_{n,s}\right) $, $ c > 0 $}: $ {\left[{a}^{1,c}\right]}_{n,s} $, $ {a}^{1,c}+ns\to {\left\langle{\left\langle a \right\rangle +1}\right\rangle}_{{k}_{6},1} $
	$ {k}_{7} $: PC 碰撞^[30,32,36]	$ {k}_{7}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}({i}_{1},{i}_{2}) $}: $ {\left[{a}^{{i}_{2}}\right]}_{n,s} $, $ {(a+ns)}^{{i}_{1}}\to {k}_{7}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{8} $: 数据地址碰撞^[30]	$ {k}_{8}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $,$ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}(a,b) $}: $ {\left[\left(a,b\right)?\right]}_{n,s} $, $ a+ns\to {k}_{8}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{9} $: 随机块内偏移^[36]	$ {k}_{9}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $, $ \mathrm{s}\mathrm{a}\mathrm{m}\mathrm{e}\_\mathrm{c}\mathrm{l}(a,b) $}: $ {[\left(a,b\right)?]}_{n,s} $, $ a+ns\to {k}_{9}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{10} $: 表项大小^[32]	$ \left\lceil{k}_{10}\right\rceil $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{10}\right)} \right\rangle $ }: $ {[{\left[{a}^{i}\right]}_{n,s}{\text{～}}]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{10}\right),i:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{10}\right)} $, $ ({{a}_{1}+ns)}^{1}\to \left\langle {a}_{1}+\left(n+1\right)s \right\rangle $
	$ {k}_{11} $: 跨页预取^{[30,32,36,37]}	$ {k}_{11}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle a+ns \right\rangle ,\left\langle a+\left(n+1\right)s \right\rangle ) $}: $ {\left[a\right]}_{n,s} $, $ a+ns\to {k}_{11}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{12} $: 跨页训练^[30,32]	$ {k}_{12}\in \left(\mathrm{0,1}\right) $, {$ n={k}_{1} $, $ s\in \left\\|{k}_{2}\right\\|, $ $ \mathrm{s}\mathrm{a}\mathrm{m}\mathrm{e}\_\mathrm{p}\mathrm{p}\mathrm{g}\left(\left\langle {\left[a\right]}_{n-1,s} \right\rangle \right) $, $ \mathrm{s}\mathrm{a}\mathrm{m}\mathrm{e}\_\mathrm{p}\mathrm{p}\mathrm{g}\left(\left\langle {\left[a+(n-1)s\right]}_{3,s} \right\rangle \right) $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle a+(n-2)s \right\rangle ,\left\langle a+(n-1)s \right\rangle ) $}: $ {\left[a\right]}_{n,s} $, $ (a+ns)\to {k}_{12}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{13} $: 瞬态训练^[30]	$ {k}_{13}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $}: $ {\left[\bar{a}\right]}_{n,s} $, $ a+ns\to {k}_{13}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{14} $: 瞬态预取^[30]	$ {k}_{14}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in \left\\|{k}_{2}\right\\| $}: $ {\left[a\right]}_{n,s} $, $ \bar{a}+ns\to {k}_{14}\left\langle a+\left(n+1\right)s \right\rangle $
	$ {k}_{15} $: 交叉训练^[37]	$ {k}_{15}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ s\in\left\\|{k}_{2}\right\\| $, $ 2\le y\le {k}_{10} $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}\left(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y\right)} \right\rangle \right) $}: $ \left({{[\left[a\right]}_{n,s}～]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y\right)}\right)! $, $ {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y\right)}+ns\to {k}_{15}\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y\right)}+(n+1)s \right\rangle $
	$ {k}_{16} $: Cache 命中影响^[37]	$ {k}_{16}\in \left(\mathrm{0,1}\right) $, {$ n={k}_{1}+2 $, $ s\in \left\\|{k}_{2}\right\\| $, $ c > \text{0} $}: $ {\left[{a}^{1}\right]}_{n-2,s}{\left(a+\left(n-2\right)s\right)}^{1,c}{\left(a+\left(n-1\right)s\right)}^{1} $,$ {\left(a+ns\right)}^{1}\to {k}_{16}\left\langle a+\left(n+1\right)s \right\rangle $
Stream	$ {k}_{1} $: 流表初始化^[49]	$ \left\\|{k}_{1}\right\\|$, {$ d\in (-\mathrm{1,1}) $}: $ 0 $, $ a\to {\left\langle \left\langle a \right\rangle +d \right\rangle }_{{k}_{1},d} $
	$ {k}_{2} $: 流向初始化^[49,50]	$ {k}_{2}\in (-\mathrm{1,1}) $, {}: $ {a}_{1} $, $ {a}_{2}\to {\left\langle \left\langle {a}_{2} \right\rangle +{k}_{2} \right\rangle }_{2,{k}_{2}} $
	$ {k}_{3} $: 流向更新^[49,50]	$ {k}_{3}\in (-\mathrm{1,1}) $, $\left\\|{k}_{4}\right\\| $, {}: $ {a}_{1}{a}_{2} $, $ {a}_{3}\to {\left\langle \left\langle {a}_{3} \right\rangle +{k}_{3} \right\rangle }_{{k}_{4},{k}_{3}} $
	$ {k}_{4} $: 预取数量^[49,50]
	$ {k}_{5} $: 表项大小^[50]	$\left\lceil{k}_{5}\right\rceil $, {$ y={k}_{2} $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}\left(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{5}\right)} \right\rangle \right) $}: $ {[{\left[{a}^{i}\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(2\right)}{\text{～}}]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{5}\right),i:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{5}\right)} $, $ {a}_{\mathrm{1,3}}\to {\left\langle \left\langle {a}_{\mathrm{1,3}} \right\rangle +y \right\rangle }_{2,y} $
	$ {k}_{6} $: 跨页预取^[50]	$ {k}_{6}\in \left(\mathrm{0,1}\right) $, {$ y={k}_{2} $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle {a}_{1} \right\rangle ,\left\langle {a}_{2} \right\rangle ) $}: $ {a}_{1} $, $ {a}_{2}\to {k}_{6}{\left\langle \left\langle {a}_{2} \right\rangle +y \right\rangle }_{2,y} $
	$ {k}_{7} $: Cache命中影响^[49]	$ {k}_{7}\in \left(\mathrm{0,1}\right) $, {$ y={k}_{3} $, $ x={k}_{4} $, $ c > 0 $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{c}\mathrm{l}\left({a}_{1},{a}_{2},{a}_{3}\right) $}: $ {a}_{1}^{1}{a}_{2}^{1,c} $, $ {a}_{3}^{1}\to {k}_{7}{\left\langle \left\langle {a}_{3} \right\rangle +y \right\rangle }_{x,y} $
XPT	$ {k}_{1} $: 激活信心值^[33]	$ \left\lfloor{k}_{1}\right\rfloor $: $ {\left[a\right]}_{{k}_{1}} $, $ a\to \left\langle a \right\rangle $
	$ {k}_{2} $: 数据地址碰撞^[33]	$ {k}_{2}\in \left(\mathrm{0,1}\right) $, {$ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}(a,b) $, $ n\ge {k}_{1} $}: $ {[\left(a,b\right)?]}_{n} $, $ a\to {k}_{2}\left\langle a \right\rangle $
	$ {k}_{3} $: PC碰撞^[33]	$ {k}_{3}\in \left(\mathrm{0,1}\right) $, {$ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}({i}_{1},{i}_{2}) $, $ \mathrm{s}\mathrm{a}\mathrm{m}\mathrm{e}\_\mathrm{c}\mathrm{l}({a}_{1},{a}_{2}) $, $ n\ge {k}_{1} $}: $ {\left[{a}_{1}^{{i}_{1}}\right]}_{n} $, $ {a}_{2}^{{i}_{2}}\to {k}_{3}\left\langle {a}_{1} \right\rangle $
	$ {k}_{4} $: 是否跨页^[33]	$ {k}_{4}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}(a,b) $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle a \right\rangle ,\left\langle b \right\rangle ) $}: $ {\left[a\right]}_{n} $, $ b\to {k}_{4}\left\langle b \right\rangle $
	$ {k}_{5} $: 表项大小^[33]	$ \left\lceil {k}_{5}\right\rceil $, {$ n\ge {k}_{1} $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}\left(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{5}\right)} \right\rangle \right) $}: $ {[{\left[{a}^{i}\right]}_{n}{\text{～}}]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{5}\right),i:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{5}\right)} $, $ {a}_{1}^{1}\to \left\langle a \right\rangle $
	$ {k}_{6} $: 相联度^[33]	$ \left\lfloor{k}_{6}\right\rfloor $, {$ \text{n}\ge {k}_{1} $, $ \text{same\_lsb}({\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{6}+1\right)},{\mathrm{log}}_{2}\frac{4096{k}_{5}}{{k}_{6}}) $, $ \text{diff\_ppg}(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{6}+1\right)} \right\rangle $}: $ {[{\left[{a}^{i}\right]}_{n}{\text{～}}]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{6}+1\right),i:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}({k}_{6}+1)} $, $ {a}_{1}^{1}\to 0 $
	$ {k}_{7} $: 替换策略 (LRU)^[33]	$ {k}_{7}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ y={k}_{6} $, $ \mathrm{s}\mathrm{a}\mathrm{m}\mathrm{e}\_\mathrm{l}\mathrm{s}\mathrm{b}({\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{6}+1\right)},{\mathrm{log}}_{2}\frac{4096{k}_{5}}{{k}_{6}}) $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y+1\right)} \right\rangle $}: $ {[{\left[{a}^{i}\right]}_{n}～]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y\right),i:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(y\right)}{a}_{1}^{1}{a}_{y+1}^{y+1} $, $ {a}_{1}^{1}\to {k}_{7}\left\langle {a}_{1}^{1} \right\rangle $
SMS	$ {k}_{1} $: 激活次数^[36]	$ \left\lfloor {k}_{1}\right\rfloor $, {$ {k}_{1}\ge 2 $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}\left(b\right) $}: $ {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{1}\right)} $, $ b\to \left\langle b+{\left[\right(a-{a}_{1}\left)\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}(2,{k}_{1})} \right\rangle $
	$ {k}_{2} $: 低地址预取数量^[36]	$ \left\lceil{k}_{2}\right\rceil $, {$ {k}_{2}\ge {k}_{1} $, $ \mathrm{i}\mathrm{s}\_\mathrm{m}\mathrm{a}\mathrm{x}\mathrm{i}\mathrm{m}\mathrm{u}\mathrm{m}({\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{2}\right)},{a}_{1}) $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}\left(b\right) $}: $ {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{2}\right)} $, $ b\to \left\langle b+{\left[\right(a-{a}_{1}\left)\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}(2,{k}_{2})} \right\rangle $
	$ {k}_{3} $: 高地址预取数量^[36]	$ \left\lceil{k}_{3}\right\rceil $, {$ \mathrm{i}\mathrm{s}\_\mathrm{m}\mathrm{i}\mathrm{n}\mathrm{i}\mathrm{n}\mathrm{u}\mathrm{m}({\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{3}\right)},{a}_{1}) $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}\left(b\right) $}: $ {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{3}\right)} $, $ b\to \left\langle b+{\left[\right(a-{a}_{1}\left)\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}(2,{k}_{3})} \right\rangle $
	$ {k}_{4} $: 预取边界^[36]	$ \left\\|{k}_{4}\right\\| $, {$ n={k}_{1} $, $ {a}_{n}=a+{k}_{4} $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}\left(b\right) $}: $ {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(n\right)} $, $ b\to \left\langle b+{\left[\right(a-{a}_{1}\left)\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}(2,n)} \right\rangle $
	$ {k}_{5} $: 数据地址碰撞^[36]	$ {k}_{5}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}\left(b\right) $, $ \mathrm{d}\mathrm{i}\mathrm{f}\mathrm{f}\_\mathrm{p}\mathrm{p}\mathrm{g}(\left\langle {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(n\right)} \right\rangle ,\left\langle b \right\rangle ) $}: $ {\left[\left(a,b\right)!\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(n\right)} $, $ b\to {k}_{5}\left\langle b+{\left[\right(a-{a}_{1}\left)\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}(2,n)} \right\rangle $
	$ {k}_{6} $: PC碰撞^[36]	$ {k}_{6}\in \left(\mathrm{0,1}\right) $, {$ n\ge {k}_{1} $, $ \mathrm{e}\mathrm{x}\mathrm{i}\mathrm{s}\mathrm{t}({i}_{1},{i}_{2},b) $}: $ {\left[{a}^{{i}_{1}}\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left(n\right)} $, $ {b}^{{i}_{2}}\to {k}_{6}\left\langle b+{\left[\right(a-{a}_{1}\left)\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}(2,n)} \right\rangle $
DMP	$ {k}_{1} $: 预取数量和位置^[31]	$ \left\\|{k}_{1}\right\\| $: $ 0 $, $ a\to \left\langle {\left[{}_{8}{}^{\mathrm{*}}a\right]}_{8,{k}_{1}} \right\rangle $
	$ {k}_{2} $: 历史过滤^[31]	$ {k}_{2}\in \left(\mathrm{0,1}\right) $, {$ \text{n}\in \left\\|{k}_{1}\right\\| $}: $ \text{a} $, $ a\to {k}_{2}\left\langle {\left[{}_{8}{}^{*}a\right]}_{8,n} \right\rangle $
	$ {k}_{3} $: 历史过滤器大小^[31]	$ \left\lfloor{k}_{3}\right\rfloor $, {$ \text{n}\in \left\\|{k}_{1}\right\\| $}: $ {\left[a\right]}_{a:\mathrm{r}\mathrm{a}\mathrm{n}\mathrm{g}\mathrm{e}\left({k}_{3}\right)} $, $ {a}_{1}\to \left\langle {\left[{}_{8}{}^{*}a\right]}_{8,n} \right\rangle $
	$ {k}_{4} $: 预取范围^[31]	$ \left\\|{k}_{4}\right\\| $, {$ {}_{8}{}^{}a\in {k}_{4} $, $ n\in \left\\|{k}_{1}\right\\| $}: $ \text{0} $, $ a\to \left\langle {\left[{}_{8}{}^{}a\right]}_{8,n} \right\rangle $
	$ {k}_{5} $: 瞬态预取^[35]	$ {k}_{5}\in \left(\mathrm{0,1}\right) $, {$ n\in \left\\|{k}_{1}\right\\| $}: $ 0 $, $ \stackrel{-}{a}\to {k}_{5}\left\langle {\left[{}_{8}{}^{*}a\right]}_{8,n} \right\rangle $
	$ {k}_{6} $: L2 Cache命中影响^[31]	$ {k}_{6}\in \left(\mathrm{0,1}\right) $, {$ c=2 $, $ n\in \left\\|{k}_{1}\right\\| $}: 0, $ {a}^{1,c}\to {k}_{6}\left\langle {\left[{}_{8}{}^{*}a\right]}_{8,n} \right\rangle $
	$ {k}_{7} $: L1 Cache命中影响^[31]	$ {k}_{7}\in \left(\mathrm{0,1}\right) $, {$ c=3 $, $ n\in \left\\|{k}_{1}\right\\| $}: 0, $ {a}^{1,c}\to {k}_{7}\left\langle {\left[{}_{8}{}^{*}a\right]}_{8,n} \right\rangle $
	$ {k}_{8} $: TLB miss^[35]	$ {k}_{8}\in \left(\mathrm{0,1}\right) $, {$ c=0 $, $ t=0 $, $ n\in \left\\|{k}_{1}\right\\| $}: 0, $ {a}^{1,c,t}\to {k}_{8}\left\langle {\left[{}_{8}{}^{*}a\right]}_{8,n} \right\rangle $

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表 2 预取器设计参数简化

预取器	参数简化
Next-line	$ {k}_{1}=0 $
Adjacent	$ {k}_{1}=1 $
Stream	$ {k}_{1}=0 $, $ {k}_{2}=1 $, $ {k}_{3}={a}_{1} > {a}_{2}?1:-1 $, $ {k}_{4}=\left[\mathrm{1,1}\right] $, $ {k}_{5}=1 $, $ {k}_{6}=0 $, $ {k}_{7}=1 $
Stride	$ {k}_{1}=3 $, $ {k}_{2}=\left[\mathrm{1,1024}\right] $, $ {k}_{3}=1 $, $ {k}_{4}=1 $, $ {k}_{5}=\left[\mathrm{1,1}\right] $, $ {k}_{6}=\left[\mathrm{1,2}\right] $, $ {k}_{7}=1 $, $ {k}_{8}=1 $, $ {k}_{9}=1 $, $ {k}_{10}=1 $, $ {k}_{11}=1 $, $ {k}_{12}=1 $, $ {k}_{13}=1 $, $ {k}_{14}=1 $, $ {k}_{15}=0 $, $ {k}_{16}=0 $
XPT	$ {k}_{1}=1 $, $ {k}_{2}=0 $, $ {k}_{3}=0 $, $ {k}_{4}=0 $, $ {k}_{5}=1 $, $ {k}_{6}=1 $, $ {k}_{7}=1 $
SMS	$ {k}_{1}=1 $, $ {k}_{2}=1 $, $ {k}_{3}=1 $, $ {k}_{4}=1024 $, $ {k}_{5}=0 $, $ {k}_{6}=1 $
DMP	$ {k}_{1}=1 $, $ {k}_{2}=1 $, $ {k}_{3}=1 $, $ {k}_{4}=[64,{2}^{32}] $, $ {k}_{5}=1 $, $ {k}_{6}=0 $, $ {k}_{7}=0 $, $ {k}_{8}=1 $
注：表2所列参数的取值不表示实际情况，而仅用于描述一个简化后的模型。

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表 3 预取器侧信道攻击模型

攻击原语	预取器	攻击模型	类型	秘密值	利用场景
Next-line-SCA^[48]	Next-line	$ V\left(a\right)\to \left\langle a \right\rangle +1 $	Content	数据流	CLEFIA
Stream-CC^[50]	Stream	$ V{(a}_{1}) $, $ V\left({a}_{2}\right),V\left({a}_{3}\right)\to \left\langle {a}_{3} \right\rangle +1 $	Content	数据流	隐蔽信道
Stride-CC^[52]	Stride	$ A\left(b\right) $, $ A(b+s) $, $ A\left(b+2s\right) $,$ V\left(a\right) $, $ V(a+s) $, $ V(a+2s)\to \left\langle b+3s \right\rangle $	Eviction	数据流	隐蔽信道
Stride-SCA^[38,39]	Stride	$ V\left(a\right) $, $ V(a+s) $, $ V(a+2s)\to \left\langle a+3s \right\rangle $	Content	数据流	AES, ECDH
PRFCF^[37]	Stride	$ V\left(c\right) $, $ V(c+s) $, $ V\left(\mathrm{A}\mathrm{L}\mathrm{U}\left(a\right)\right) $, $ V(c+2s)\to \left\langle c+3s \right\rangle $	Content	控制流	隐蔽信道
PRFIS^[37]	Stride	$ V\left({c}^{1}\right) $, $ V\left({(c+s)}^{1}\right) $, $ V\left({a}^{\mathrm{1,3}}\right) $, $ V\left({(c+2s)}^{1}\right)\to \left\langle c+6s \right\rangle $	Content	数据流	隐蔽信道
PRFOS^[37]	Stride	$ V\left(c\right) $, $ V(c+s) $, $ V\left(a\right) $, $ V(c+2s)\to \left\langle c+3s \right\rangle $	Content	数据流	隐蔽信道
AfterImage-V1^[32]	Stride	$ A\left({b}^{{i}_{1}}\right) $, $ A\left({(b+s)}^{{i}_{1}}\right) $, $ A\left({(b+2s)}^{{i}_{1}}\right) $, $ V\left({a}^{{i}_{2}}\right)\to \left\langle a+s \right\rangle $	Content	控制流	隐蔽信道
AfterImage-V2^[32]	Stride	$ A\left({b}^{{i}_{1}}\right) $, $ A\left({(b+s)}^{{i}_{1}}\right) $, $ A\left({(b+2s)}^{{i}_{1}}\right) $, $ V\left({a}^{{i}_{2}}\right)\to \left\langle b+3s \right\rangle $	Content	控制流	RSA，中断检测
ShadowLoad-V1^[30]	Stride	$ A\left({d}^{{i}_{1}}\right) $, $ A\left({(d+s)}^{{i}_{1}}\right) $, $ A\left({(d+2s)}^{{i}_{1}}\right) $, $ V\left({a}^{{i}_{2}}\right)\to \left\langle a+s \right\rangle $	Content	数据流	KASLR
ShadowLoad-V2^[30]	Stride	$ A\left({d}^{{i}_{1}}\right) $, $ A\left({(d+s)}^{{i}_{1}}\right) $, $ A\left({(d+2s)}^{{i}_{1}}\right) $, $ V\left({\stackrel{-}{a}}^{{i}_{2}}\right)\to \left\langle a+s \right\rangle $	Content	数据流	瞬态执行
FetchProbe-V1^[30]	Stride	$ V\left({a}^{{i}_{1}}\right) $, $ A\left({d}^{{i}_{2}}\right) $, $ A\left({(d+s)}^{{i}_{2}}\right) $, $ A\left({(d+2s)}^{{i}_{2}}\right)\to \left\langle d+3s \right\rangle $	Content	数据流	Base64
FetchProbe-V2^[30]	Stride	$ V\left({\stackrel{-}{a}}^{{i}_{1}}\right) $, $ A\left({d}^{{i}_{2}}\right) $, $ A\left({(d+s)}^{{i}_{2}}\right) $, $ A\left({(d+2s)}^{{i}_{2}}\right)\to \left\langle d+3s \right\rangle $	Content	数据流	瞬态执行
Prime-Reset^[34]	Stride	$ A\left(b\right) $, $ A(b+s) $, $ A\left(b+2s\right),V\left(\mathrm{I}\mathrm{N}\mathrm{V}\right(a\left)\right)\to \left\langle b+3s \right\rangle $	Eviction	控制流	隐蔽信道
PrefetchX-V1^[33]	XPT	$ A\left(b\right) $, $ V\left(a\right)\to \left\langle b \right\rangle $	Eviction	控制流	隐蔽信道，中断检测，RSA
PrefetchX-V2^[33]	XPT	$ V\left(c\right)\text{,}V\left(a\right)\to \left\langle a \right\rangle $	Content	数据流	隐蔽信道
SMS-SCA^[36]	SMS	$ V\left({a}^{{i}_{1}}\right) $, $ V\left({(a+s)}^{{i}_{1}}\right) $, $ A\left({b}^{{i}_{2}}\right)\to \left\langle b+s \right\rangle $	Content	数据流	AES，隐蔽信道
Augury-V1^[35]	DMP	$ V\left({}_{8}{}^{\mathrm{}}(a-24)\right) $,$ V\left({}_{8}{}^{\mathrm{}}(a-16)\right)\text{,} $ $ V({}_{8}{}^{\mathrm{}}a-8)\to \left\langle {}_{8}{}^{\mathrm{}}a \right\rangle $	Content	数据流	绕过“幽灵”防御
Augury-V2^[35]	DMP	$ V\left(\stackrel{-}{{}_{8}{}^{\mathrm{}}(a-24)}\right) $, $ V\left(\stackrel{-}{{}_{8}{}^{\mathrm{}}(a-16)}\right) $, $ V\left(\stackrel{-}{{}_{8}{}^{\mathrm{}}a-8}\right)\to \left\langle {}_{8}{}^{\mathrm{}}a \right\rangle $	Content	数据流	ASLR
GoFetch^[31]	DMP	$ V\left(a\right)\to \left\langle {}_{8}{}^{\mathrm{*}}a \right\rangle $	Content	数据流	DH, RSA， Kyber, Dilithium

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表 4 预取器安全性评估指标

评估项	子项	评估指标	评估项	子项	评估指标
设计参数$ {p}_{1}～{p}_{12} $	激活长度	0或1 (4); 2(3); 3(2); 4+(1)	隔离性 $ {i}_{1}～{i}_{6} $	同进程沙盒逃逸	可碰撞(0.2); 争用 (0.1); 隔离 (0)
	预取数量	1 (1); 2+ (2)		跨核	可碰撞(0.2); 争用 (0.1); 隔离 (0)
	预取深度(Byte)	63- (1); 64+,4095- (2); 4096+ (4)		跨进程	可碰撞(0.2); 争用 (0.1); 隔离 (0)
	表项大小	7- (2); 8+ (1)		跨域-内核	可碰撞(0.2); 争用 (0.1); 隔离 (0)
	是否可跨页训练	是 (4); 否 (0)		跨域-虚拟机	可碰撞(0.2); 争用 (0.1); 隔离 (0)
	是否可跨页预取	是 (5); 否 (0)		跨域-可信执行环境	可碰撞(1); 争用 (0.5); 隔离 (0)
	是否可推测训练	是 (4); 否 (0)		泄露粒度(Byte)	63-(1); 64+,4095- (0.9); 4096+ (0.8)
	是否可推测预取	是 (5); 否 (0)	可利用性 $ {e}_{1}～{e}_{6} $	是否跨页泄露	是 (1); 否 (0.9)
	cache命中是否影响	是 (4); 否 (0)		是否需预训练	是 (0.9); 否 (1)
	cache line内是否训练	是 (4); 否 (0)		是否需特权	是 (0.5); 否 (1)
	是否PC碰撞	是 (6); 否 (0)		是否受指令流影响	是 (0.95); 否 (1)
	是否数据地址碰撞	是 (6); 否 (0)		是否受数据流影响	是 (0.95); 否 (1)

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表 5 数据预取器安全性评估案例分析

预取器	参数简化			评估结果
预取器	设计参数	隔离性	利用难度	UH	H1	H2	H3
Intel Coffee Lake Stride 预取器^[30,32,36]	(2,2,2,0,0,4,5,4,4,6,6,1)	(0.2,0,0.2,0.2,0.2,1)	(1,0.9,0.9,1,1,0.95)	49.9	5.5	18.5	33.2
AMD Zen2 Stride 预取器^[30,36]	(2,2,4,4,5,4,5,4*,0,6,6,1)	(0.2,0,0.2,0.2,0.2,1*)	(0.9,0.9,0.9,1,1,0.95)	53.6	6.0	21.5	37.7
Intel Ice Lake XPT^[33]	(1,1,1,0,0,4,5,0,0,0,0,1)	(0.2,0.1,0.1,0.1,0.1,0.5)	(0.8,1,0.9,1,1,0.95)	9.8	1.8	9.8	2.5
Arm Cortex-A72 SMS预取器^[36]	(3,2,2,4,0,4,5,0,0,6,0,2)	(0.2,0,0.2,0.2,0.2*,1)	(0.9,1,0.9,1,1,0.95)	38.8	4.3	17.0	23.4
Apple M3 DMP^[31,35,36]	(4,2,4,4,5,4,5,0,4,0,0,2)	(0.2,0.2,0.2,0.2,0.2,1)	(1,1,1,1,1,1)	68.0	68.0	68.0	45.0
注：*表示目前仍未知的评估参数，并根据参考文献和处理器厂商开源文档的信息给出估计值。对于文献已经给出的评估参数，在满足表1定义的前提下，以最新论文的数据为准。

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表 6 预取器组合侧信道的潜在攻击模型示例

可能的攻击原语	预取器	可能的攻击模型	可能的利用场景
Combination-V1	Stride, Stream	$ V\left(a\right),V\left(a+s\right),V\left(a+2s\right),A\left(a+3s+1\right)\to \left\langle{a+3s}\right\rangle+2 $	攻击者地址受限时的跨页数据泄露
Combination-V2	Stride, DMP	$ A\left(b\right),A\left(b+s\right),A\left(b+2s\right),V\left(a\right)\to \left\langle{{}_{8}{}^{*}(a+s)}\right\rangle $	受害者访问地址有限时的数据泄露
Combination-V3	Stride, DMP	$ V\left(a\right),V\left(a+s\right),V\left(a+2s\right)\to \left\langle {\left[{}_{8}{}^{*}a\right]}_{\mathrm{8,24}s} \right\rangle $	降低Stride预取器侧信道的噪声
Combination-V4	Stream, XPT	$ A{(a}_{1}) $, $ A\left({a}_{2}\right),A\left({a}_{3}\right)\to \left\langle {a}_{3} \right\rangle $	优化XPT驱逐集构建过程
Combination-V5	Stride, SMS	$ V\left(a\right),V\left(a+s\right),V\left(a+2s\right),V\left(c\right),V\left(c+s\right),V\left(c+2s\right), $ $ A\left(b\right)\to \left\langle{b+a-c}\right\rangle $	优化Stride预取器探测并行度

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参考文献(63)

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