基于自检测修复的比特配置物理不可克隆函数电路设计

徐梦凡; 张跃军; 刘天翔; 潘钰

doi:10.11999/JEIT250359

基于自检测修复的比特配置物理不可克隆函数电路设计

doi: 10.11999/JEIT250359 cstr: 32379.14.JEIT250359

1.
宁波大学信息科学与工程学院宁波 315211
2.
杭州旗捷科技股份有限公司杭州 310052

基金项目: 浙江省“尖兵领雁+X”科技计划(2025C01063)，国家自然科学基金(62474100, 62174121, 62134002)，宁波市科创甬江2035重点研发计划(2024Z139)，慈溪市重点研发专项(CZ2025006)

详细信息

作者简介:
徐梦凡：女，博士生，研究方向为高可靠物理不可克隆电路设计及实现

张跃军：男，教授，研究方向为低功耗、高信息密度集成电路理论和设计

刘天翔：男，硕士，研究方向为集成电路设计、智能装备系统开发与优化

潘钰：女，硕士生，研究方向为面向FPGA的定制化可编程逻辑电路设计

通讯作者:
张跃军　zhangyuejun@nbu.edu.cn

中图分类号: TN43
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出版历程
- 收稿日期: 2025-05-06
- 修回日期: 2025-07-28
- 网络出版日期: 2025-08-04

Bit-configurable Physical Unclonable Function Circuit Based on Self-detection and Repair Method

1.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China
2.
Hangzhou Qijie Technology Co., Ltd., Hangzhou 310052, China

Funds: “Vanguard Geese Leading and X” Science and Technology Program of Zhejiang Province (2025C01063), The National Natural Science Foundation of China (62474100, 62174121, 62134002), The Key R&D Program of Ningbo Science and Technology Yongjiang 2035 (2024Z139), The Key R&D Program of Cixi(CZ2025006)

摘要

摘要: 物理不可克隆函数(PUF)作为硬件安全原语，为资源受限的物联网设备提供低成本的密钥生成与设备身份认证。然而，PUF电路的可靠性问题已经成为大规模部署的瓶颈。为此，该文提出一种基于自检测修复的比特配置高可靠PUF电路方案。该方案首先研究电桥失衡效应和亚阈值电流特性，利用亚阈值指数级电流特性放大随机工艺偏差，提升输出熵源随机性。其次，构建可配置位单元拓扑结构，结合比特配置策略，在不增加额外硬件开销的情况下，可灵活切换电桥PUF与分压PUF模式。最后，提出一种自检测与修复机制以提升PUF电路的可靠性，并结合掩蔽操作进一步降低误码率(BER)。在TSMC 28 nm工艺下实现64×64位PUF电路设计，全定制版图面积为3283.3 μm²。实验结果表明，电桥PUF和分压PUF唯一性和自相关性分别为50.03%/50.08%和0.027 7/0.027 3，且通过NIST800-22随机性测试。此外，在0 °C～80 °C的温度范围和0.81～0.99 V的电压范围内，对29%的不稳定位进行修复或掩蔽处理，最终误码率为1.62E–9。
- 硬件安全 /
- 物理不可克隆函数 /
- 可靠性 /
- 自检测修复 /
- 比特配置
Abstract: Objective The proliferation of Internet of Things (IoT) devices has intensified the need for robust, hardware-level security. Among hardware-based security primitives, Physical Unclonable Functions (PUFs) serve a critical role in lightweight authentication and dynamic key generation by leveraging inherent process variations to produce unique, unclonable responses. Achieving reliable PUF performance under environmental fluctuations—such as temperature and supply voltage variation, requires balancing sensitivity to process variations with environmental robustness. Conventional approaches, including circuit-level stabilization and architecture-level error correction, can improve reliability but often increase area, power, and test complexity. To overcome these drawbacks, recent work has explored voltage or bias perturbation for unstable response correction. However, entropy degradation during mode transitions in dual-mode PUFs remains a major concern, compromising both reliability and energy efficiency. This study proposes a bit-configurable bistable electric bridge-divider PUF that addresses these challenges by maintaining entropy independence between operational modes, reducing error correlation, and limiting repair and masking overhead. The proposed solution improves randomness, reliability, and energy efficiency, making it suitable for secure, cost-effective authentication in IoT edge devices operating under dynamic conditions. Methods Hardware overhead and testing complexity associated with conventional PUF stabilization techniques are reduced by introducing a bit-configurable bistable electric bridge-divider PUF architecture. Entropy generation is enhanced by amplifying process-induced variations through electric bridge imbalance and the exponential behavior of subthreshold current. A reconfigurable bit-cell is employed to enable seamless switching between electric bridge mode and voltage divider mode without additional layout cost; dual-mode operation is thus supported while preserving area efficiency. A voltage-skew-based self-detection and repair mechanism is integrated to dynamically identify and mitigate unstable responses, thereby improving reliability under varying environmental conditions. The PUF circuit is fully custom-designed and fabricated in the TSMC 28 nm CMOS process. Post-layout simulations confirm the robustness of the architecture, demonstrating effective self-repair capabilities and consistent performance under temperature and voltage fluctuations. Results and Discussions The proposed design is fabricated using the TSMC 28 nm CMOS process. The total layout area measures 3 283.3 μm², and each PUF cell occupies 0.7888 μm² (Fig. 11). Simulation waveforms of the self-detection, repair, and masking operations are presented in (Fig. 12). Inter-chip Hamming distance histograms and fitted curves for both electric bridge mode and voltage divider mode are shown in (Fig. 13a, Fig. 14a). Autocorrelation results of the 40,960-bit output are illustrated in (Fig. 13b, Fig. 14b). The randomness of the responses is evaluated using the NIST test suite provided by the U.S. National Institute of Standards and Technology, with the results summarized in (Table 1). The native Bit Error Rate (BER), measured before repair or masking, is analyzed under various temperature and supply voltage conditions (Fig. 15). By dynamically adjusting the voltage skew, precise control of the error correction rate is achieved, leading to a substantial reduction in BER across different environments (Fig. 16). A performance comparison with previously reported designs is provided in (Table 2). After applying the entropy source repair and masking mechanism, the BER converges to below 1.62 × 10^–9, approaching the ideal “zero” BER. Conclusions A bit-configurable PUF architecture is proposed to address environmental variability and hardware constraints in IoT edge devices. A reconfigurable bit-cell is employed to support dynamic switching between electric bridge mode and voltage divider mode without incurring additional layout cost. Process-induced variations are amplified through bridge imbalance and the exponential behavior of subthreshold current, which enhances the randomness and uniqueness of the PUF responses. A voltage-skew-based self-detection and repair mechanism is integrated to identify and correct unstable responses, effectively reducing the BER under varying environmental conditions. The proposed design, fabricated using the TSMC 28 nm CMOS process, demonstrates high entropy, robustness, and low overhead in terms of area and power consumption. These characteristics make it suitable for secure and lightweight authentication and key generation in resource-constrained IoT systems.
- Hardware security /
- Physical Unclonable Function (PUF) /
- Reliability /
- Self-detection and repair /
- Bit-configurable

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图 1 惠斯通电桥结构

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图 2 NMOS电桥结构及I-V特性分析

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图 3 PMOS电桥结构及I-V特性分析

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图 4 分压PUF电路结构及I-V特性分析

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图 5 电桥模式

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图 6 分压模式

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图 7 自检测电路

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图 8 模式选择电路

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图 9 自检测修复与掩蔽操作流程

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图 10 整体电路顶层架构

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图 11 电路整体版图和PUF单元版图

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图 12 自检测修复与掩蔽操作仿真波形

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图 13 电桥PUF片间汉明距离和自相关测试

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图 14 分压PUF片间汉明距离和自相关测试

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图 15 不同温度和电压下PUF原生误码率

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图 16 不同温度和电压下PUF误码修复比率

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表 1 NIST随机性测试

测试项目	比特流长度	P-Value I	P-Value II	通过/不通过
近似熵	1 024	0.999 83	0.795 61	通过
块内频率	1 024	0.877 29	0.839 12	通过
累加和	1 024	0.741 40	0.834 10	通过
离散傅里叶变换	1 024	0.327 66	0.427 92	通过
频率	1 024	0.592 16	0.521 88	通过
线性复杂度	1 024	0.561 34	0.638 17	通过
块内最长游程	1 024	0.775 82	0.793 70	通过
非重叠模块匹配	1 024	0.718 99	0.460 11	通过
2元矩阵秩	1 024	0.538 69	0.324 15	通过
序列	1 024	0.693 72	0.586 71	通过
游程	1 024	0.530 80	0.443 76	通过

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表 2 与相关文献性能对比

	INV PUF^[15]	SRAM PUF^[17]	NOR PUF^[19]	NAND PUF^[20]	本文
工艺尺寸(nm)	65	65	65	14	28
单位面积(F²/bit)	594	3 001	266	1 065	1 006
温度范围(°C)	–40～125	–10～85	–20～125	25～110	0～80
电压范围(V)	0.7～1.4	0.8～1.2	0.8～1.2	0.55～75	0.8～1
原生不稳定位(%)	4.2	19.6	2.74	2.55	5.4/8.2
稳定前误码率(%)	4.2	2.24	4.64	1.46	-
稳定后误码率(%^e)	<5.99E–7	<1.4E–9	<4.88E–8	-	<1.62E–9
掩蔽率(%)	31/35	59	-	20	29
唯一性(%)	0.499 5	-	0.499/0.5	0.497 8	0.503/0.507
芯片能耗(fJ/bit)	0.057	15.39	0.063	4	0.104

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参考文献(20)

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