面向国产交换芯片的多模态网络后端编译器设计

凃化清; 王元鸿; 徐琪; 朱俊; 邹涛; 隆克平

doi:10.11999/JEIT250132

面向国产交换芯片的多模态网络后端编译器设计

doi: 10.11999/JEIT250132 cstr: 32379.14.JEIT250132

凃化清^{1, 2},
王元鸿^{1, 2},
徐琪^{1, 2},
朱俊^{1, 2},
邹涛^{1, 2, ,},
隆克平^{1, 2}

1.
之江实验室杭州 310000
2.
中国科学院计算技术研究所北京 100000

基金项目: 国家重点研发计划项目(2022YFB2901503)，国家自然科学基金项目(U22A2005)，浙江省重点研发计划项目(2024SSYS0001)，中国博士后科学基金项目(2024M75986)。

详细信息

作者简介:
凃化清：女，博士后，研究方向为软件定义网络、可编程数据平面、多模态网络等

王元鸿：男，硕士，研究方向为多模态网络、可编程网络

徐琪：男，副研究员，研究方向为多模态网络、软件定义网络、时间敏感网络

朱俊：男，高级工程师，研究方向为新型网络体系结构、软件定义网络、网络资源管理、网络协议设计优化等

邹涛：男，研究员，研究方向为多模态网络技术和新型网络体系结构

隆克平：男，教授，研究方向为新一代网络技术、光互联网关键技术、无线通信技术、人工智能与大数据

通讯作者:
邹涛，　zout@zhejianglab.org

中图分类号: TN393
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出版历程
- 收稿日期: 2025-03-05
- 修回日期: 2025-11-03
- 录用日期: 2025-11-03
- 网络出版日期: 2025-11-08

A Polymorphic Network Backend Compiler for Domestic Switching Chips

TU Huaqing^{1, 2},
WANG Yuanhong^{1, 2},
XU Qi^{1, 2},
ZHU Jun^{1, 2},
ZOU Tao^{1, 2
, ,},
LONG Keping^{1, 2}

1.
Zhejiang Laboratory, Hangzhou 310000, China
2.
Institute of Computing Technology Chinese Academy of Sciences, Beijing 100000, China

Funds: National Key Research and Development Project of China (No. 2022YFB2901503), National Natural Science Foundation of China (No. U22A2005), Key R&D Program of Zhejiang (2024SSYS0001), China Postdoctoral Science Foundation (No. 2024M75986).

摘要

摘要: 当前，后端编译器相关工作主要针对软件可编程交换机(BMv2)、现场可编程门阵列(FPGA)、Intel Tofino系列芯片等可编程设备进行设计和优化，不适用于国产盛科TsingMa.MX交换芯片上多模态网络程序的编译。为此，本文提出面向TsingMa.MX交换芯片的多模态网络后端编译器p4c-TsingMa，实现了高级网络编程语言到TsingMa.MX交换芯片的编译，使TsingMa.MX交换芯片同时支持多种网络模态报文的解析与转发。p4c-TsingMa首先使用先序遍历方法从中间表示中提取出协议类型、协议字段、动作等关键信息，然后根据所提取的信息进行指令转译，最终生成TsingMa.MX芯片控制命令。同时，p4c-TsingMa采用用户自定义字段(UDF)合并方法，将不同网络模态的匹配指令合并在一个查找表中，从而一次提取多个模态的匹配项，提高芯片资源利用率。实验结果表明，p4c-TsingMa可实现对多种网络模态程序的正确编译，相较于未启用 UDF 表项合并算法、单端口独立配置各模态UDF规则的场景，其可将寄存器资源利用率提升37.5%～75%。
- 多模态网络 /
- 可编程数据平面 /
- 国产交换芯片 /
- 后端编译器
Abstract: Objective The P4 language and programmable switching chips provide a feasible solution for the deployment of polymorphic networks. However, polymorphic network packets written in P4 cannot be directly executed on the domestically produced TsingMa.MX programmable switching chip from Centec, necessitating the design of a specialized compiler to translate and deploy P4 language onto this chip. Existing backend compilers are primarily designed and optimized for software-programmable switches such as BMv2, FPGAs, and Intel Tofino series chips, making them unsuitable for compiling polymorphic network programs on the TsingMa.MX chip. To address this issue, this paper proposes p4c-TsingMa, a backend compiler tailored for the TsingMa.MX switching chip. This compiler enables the translation of high-level network programming languages into executable formats for the TsingMa.MX chip, allowing it to simultaneously support the parsing and forwarding of multiple types of network modal packets. Methods p4c-TsingMa first employs a preorder traversal method to extract key information such as protocol types, protocol fields, and actions from the Intermediate Representation (IR). Then performs instruction translation, ultimately generating control commands for the TsingMa.MX chip. Additionally, p4c-TsingMa adopts a UDF entry merging method to consolidate matching instructions from different network modalities into a single lookup table, enabling the extraction of multiple modal matching entries in one operation and significantly improving the utilization of chip resources. Results and Discussions This paper implements the p4c-TsingMa compiler using C++, which maps network modal programs written in P4 language into chip configurations for the TsingMa.MX switching chip. A polymorphic network packet testing environment (Fig. 7) is established, where multiple types of network data packets are simultaneously sent to the same port of the switch. The chip, following the flow table configuration, successfully identifies polymorphic network data packets and forwards them to their corresponding ports (Fig. 9). Additionally, the table entry merging algorithm improves register resource utilization by 37.5% to 75%, enabling the chip to process more than two types of modal data packets in parallel. Conclusions This paper designs a polymorphic network backend compiler, p4c-TsingMa, specifically for domestic switching chip. By leveraging the FlexParser and FlexEdit capabilities of the TsingMa chip, the compiler translates polymorphic network programs into TsingMa.MX chip commands, enabling the chip to parse and edit polymorphic data packets. Experimental results demonstrate that p4c-TsingMa achieves high compilation efficiency and improves register resource utilization by 37.5% to 75%.
- Polymorphic Network /
- Programmable Data Plane /
- Domestic Switching Chips /
- Backend Compiler

HTML全文

图 1 后端编译器p4c-TsingMa.MX的整体架构

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图 2 P4源程序及IR比较

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图 3 UDF指令转译过程

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图 4 关键字具体位分布图

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图 5 FlexEdit指令转译过程

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图 6 测试环境拓扑

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图 7 流表文件

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图 8 端口流量分析图

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表 1 不同编译方法对比

目标平台	编译方法	IR解析策略	硬件映射逻辑	核心优化方向
BMv2	P4LLVM^[16]	利用底层虚拟机框架解析P4代码，提取可通过底层虚拟机优化通道处理的网络程序逻辑	生成JSON格式输出，借助底层虚拟机的通用优化能力提升网络程序效率	为软件交换机bmv2提供专用后端编译支持
FPGA	P4FPGA^[18]	解析P4代码并提取适合FPGA硬件实现的并行、高性能逻辑	生成Verilog代码，简化FPGA开发，融合 P4 的灵活性与 FPGA 的高性能	借助底层虚拟机优化通道提升网络程序执行效率
Tofino	Chipmunk^[17]	解析P4代码并进行多层级编译处理，抽象掉Tofino硬件特定细节	生成Tofino专用文件，提供高层级编程抽象，适配 Tofino 的匹配 - 动作流水线架构	简化FPGA开发，实现P4与FPGA的高效融合
TsingMa	p4c-TsingMa (本文方法)	通过先序遍历解析DAG结构的中间表示，精准提取协议类型等关键信息	自定义P4 语义-国产芯片 FlexParser / FlexEdit硬件参数”映射规则，生成适配的芯片指令，解决非原生P4支持的硬件适配问题	提供高层级编程抽象，屏蔽Tofino硬件细节

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1 协议头字段偏移量计算算法

输入：$hdr$-P4协议头类型定义(Type_Header对象)
输出：更新全局映射$ structOffsets $，存储协议头字段的元数据
(1) 初始化 $structInfo$← $\varnothing $
(2) $ headerName $←$ hdr $的名字
(3) 创建空的 $ headerOffset $ 字典
(4) $ offset $← 0
(5) for each 字段 $ ele $ in $ hdr $ 的字段列表 do ：
(6) 　$ structInfo.eleName $←$ ele.name $
(7) 　if $ ele $的类型是 $ Type\_Bits $ then
(8) 　　$ structInfo.eleType,length $← "Type_Bits",ele的位宽
(9) 　　$ offset $←$ offset $+$ ele $的位宽
(10) end if
(11) 将 ($ ele $的名称,$ structInfo $) 插入 $ headerOffset $ 字典
(12) end for
(13) $ structInfo.eleName,length,eleOffset $← 　"totalOffset",offset,offset
(14) 将 ("totalOffset",$ structInfo $) 插入 $ headerOffset $字典
(15) 将 ($ headerName $, $ headerOffset $) 插入全局 $ structOffsets $字典

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2 UDF表项合并算法

(1) 对$ ruleSet $中的UDF规则根据关键字长度进行降序排序
(2) 设置$mergeNum$个模态分组，每组初始化为$\varnothing $
(3) for each UDF规则in $ruleSet$：
(4) 　找到消耗存储资源最少的模态分组，记为$ G\_min $
(5) 　$ G\_min \leftarrow G\_min \cup ${UDF规则}
(6) end for
(7) for each 模态分组：
(8) 构建合并的UDF规则$ mergeRule $
(9) $ mergeRuleSet \leftarrow mergeRuleSet \cup mergeRule $
(10) end for
(11) return $ mergeRuleSet $

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表 2 IPv4模态CLI指令

ID	CLI	说明
1	config udf_1 L2 96 0X0800 0XFFFF	etherType通过udf_1这条规则匹配，基础偏移类型L2 偏移96位，掩码0XFFFF，匹配0X0800
2	config udf_2 L2 240 0X0A000003 0XFFFFFFFF	dst_addr通过udf_2这条规则匹配，基础偏移类型L2 偏移240位，掩码0XFFFFFFFF，匹配0X0A000003
3	config udf match udf_1 udf_2 action Ethernet2	将匹配到的数据包从Ethernet2端口转发

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表 3 芯片资源占用情况

网络模态	关键字个数	关键字长度(bit)	寄存器资源利用率
AccMF	3	80	62.5%
CoreMF	2	32	25%
IPv4	2	48	37.5%
PwL	2	64	50%
IPv6	2	144	100%
AccMF_CoreMF_IPv4_PwL	6	176	100%

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