The Design and Implementation of a Secure and Efficient Firmware Trusted Platform Module for RISC-V Platforms
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摘要: 可信平台模块(TPM)作为提升系统安全性的核心技术,能够提供基于硬件的密钥管理、可信启动和远程认证等安全功能。然而,当前 RISC-V平台普遍缺乏TPM支持,限制了其在嵌入式和云计算场景中的安全能力。为解决这一问题,该文设计并实现了RfTPM—一种面向RISC-V平台的固件可信平台模块(fTPM)架构,无需额外硬件单元或安全扩展即可提供等效的安全功能。针对执行隔离、可信启动、高效通信和安全时钟等关键挑战,在RfTPM中,该文提出了创新解决方案,包括:基于RISC-V物理内存保护(PMP)机制的内存隔离以及结合DRAM物理不可克隆函数(PUF)与Flash锁定的静态数据保护、基于延迟度量扩展的可信启动机制、基于动态权限交换页的高效通信机制以及基于RISC-V硬件计时器的细粒度安全时钟。该文构建了RfTPM的原型系统,对其进行了安全性分析并在Genesys2 FPGA平台模拟的Rocket Core上进行了性能测试。实验结果表明,RfTPM在保证安全性的同时在大多数TPM命令处理中有比较显著的性能优势。Abstract:
Objective The Trusted Platform Module (TPM) is a critical technology in modern secure computing systems, providing hardware-based key management, trusted boot, and remote attestation to safeguard sensitive operations in embedded and cloud environments. However, current RISC-V platforms lack native TPM support, presenting a security challenge as these systems are increasingly deployed in diverse application scenarios. To address this limitation, RfTPM—a firmware-based TPM (fTPM) architecture—has been developed to deliver the same security functionality as conventional hardware TPMs without requiring additional hardware components or specialized security extensions. This solution provides an immediate, cost-effective means to secure RISC-V systems while contributing to the advancement of trusted computing on emerging processor architectures. Methods The development of RfTPM incorporates several innovative techniques to overcome the challenges of implementing TPM functionalities in firmware. The design utilizes the RISC-V Physical Memory Protection (PMP) mechanism to enforce strict memory isolation, ensuring that fTPM code and data are inaccessible to unauthorized processes. A novel static data protection strategy is introduced, combining a DRAM-based Physically Unclonable Function (PUF) with Flash locking to secure the generation and storage of cryptographic root keys, preventing rollback attacks on persistent fTPM data. To secure the boot process, RfTPM employs a delay measurement extension mechanism, which divides the boot sequence into two phases: a verification phase where each boot stage is measured and authenticated before control is transferred, and a subsequent measurement phase that continuously validates system integrity according to TPM standards. The architecture also features a dynamic permission exchange page, enabling zero-copy communication across different privilege levels by dynamically configuring PMP permissions, reducing data transfer overhead. Additionally, a fine-grained secure clock is established using the native RISC-V hardware timer to counter timing-based attacks. The solution is prototyped as a secure extension module within OpenSBI, integrated with a dedicated kernel driver and an adapted TPM Software Stack (TSS), and evaluated on a Genesys2 FPGA board simulating a Rocket Core running Linux. Results and Discussions Comprehensive experimental evaluations demonstrate that RfTPM meets stringent security requirements while offering significant performance benefits over both traditional hardware TPMs and conventional software TPM implementations. In a benchmark involving 2048-bit RSA key generation ( Fig. 4 ), the hardware TPM required approximately 17.28 seconds to complete the operation, whereas the RfTPM implementation achieved the same task in just 2.18 seconds, representing a 7 times improvement. Further tests evaluating sealing, unsealing, signing, and verification commands (Fig. 5 ) reveal performance enhancements ranging from 3.7% to 8.2%, primarily due to the efficiency of the zero-copy communication mechanism. Additional evaluations of cryptographic operations show that RfTPM improved RSA encryption and decryption by 8.2% and 8.0%, respectively, and AES encryption and decryption by 9.1% and 9.2% (Fig. 6 ). Although the NVRAM startup process in RfTPM incurs minor overhead—measured at 5.28 milliseconds compared to 0.9 milliseconds for conventional software TPMs—this delay is negligible, as NVRAM initialization occurs only once during system boot and does not impact overall runtime performance. Memory footprint analysis further reveals that while conventional software TPMs may consume approximately 1 536 kB of physical memory, the combined footprint of the fTPM and OpenSBI firmware in RfTPM is only 956 kB, which can be reduced to 808 kB through compiler optimizations. These results collectively confirm that RfTPM not only provides robust defense against various security threats, including TOCTOU and rollback attacks, but also enhances operational efficiency, making it an optimal solution for secure computing on RISC-V platforms.Conclusions In summary, RfTPM represents the first comprehensive firmware-based TPM architecture specifically tailored for RISC-V platforms, effectively addressing critical challenges such as secure execution, trusted boot integrity, efficient inter-layer communication, and precise timekeeping without incurring additional hardware costs. By integrating advanced techniques—including PMP-based memory isolation, DRAM PUF-enhanced static data protection, a dual-phase boot process with delay measurement extension, dynamic permission exchange for zero-copy communication, and a hardware-based secure clock—RfTPM delivers robust security functionality that matches or exceeds that of traditional hardware TPMs. Experimental results confirm that RfTPM upholds rigorous security standards while offering substantial performance and resource utilization advantages over both hardware TPMs and existing software TPMs. The open-sourcing of core components further fosters community collaboration and provides a platform for future research focused on refining trusted computing solutions for emerging architectures like RISC-V. Future work may explore additional hardware optimizations, such as native AES instruction support, and further enhancements to file system performance to increase the efficiency and robustness of fTPM implementations. -
1 基于受保护 DRAM PUF 的密钥生成算法
输入:受保护的 DRAM 区域;重读次数repeat_count;位稳定
性的阈值threshold输出:生成的稳定密钥Key 1 Key ← $\varnothing $ 2 response_set ← $\varnothing $ 3 for i in range(0, repeat_count): 4 response ← $\varnothing $ 5 初始化受保护 DRAM 为全“0”或全“1” 6 读取受保护 DRAM 状态并记录为 response 7 response_set.add(response) 8 end for 9 bit_statistics ← 统计每个位在 response_set 中为“1”的频率 10 for idx in bit_statistics: 11 if bit_statistics[idx] ≥ threshold: 12 Key.add(1) 13 else: 14 Key.add(0) 15 end if 16 end for 17 return Key -
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