一种新型的高性能CPU时钟树自适应优化策略

樊凌雁; 张哲; 黄灿坤; 骆建平; 刘海銮

doi:10.11999/JEIT240811

一种新型的高性能CPU时钟树自适应优化策略

doi: 10.11999/JEIT240811

1.
杭州电子科技大学微电子研究院杭州 310018
2.
上海奕斯伟计算技术有限公司上海 200131

基金项目: 国家自然科学基金(U22A2071)，科技部重大攻关项目(GG20210104)

详细信息

作者简介:
樊凌雁：女，研究员，研究方向为数据存储，高速接口集成电路设计

张哲：男，硕士生，研究方向为高性能CPU的物理设计

黄灿坤：男，硕士生，研究方向为高性能CPU的物理设计

骆建平：男，高工，研究方向为高性能数字芯片设计

刘海銮：男，正高级高工，研究方向为数据存储，高速接口集成电路设计

通讯作者:
刘海銮　lloyd.liu@sage-micro.com.cn

中图分类号: TN4; TN431.2
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- 文章访问数: 89
- HTML全文浏览量: 29
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- 被引次数: 0
出版历程
- 收稿日期: 2024-09-23
- 修回日期: 2025-03-10
- 网络出版日期: 2025-03-19

A Novel Adaptive Optimization Strategy for High-Performance CPU Clock Trees

1.
Microelectronics Research Institute, Hangzhou Dianzi University, Hangzhou 310018, China
2.
Shanghai ESWIN Computing Technology Co., Ltd. Shanghai 200131, China

Funds: The National Natural Science Foundation of China (U22A2071), The National Key Research and Development Program (GG20210104)

摘要

摘要: 该文基于精简指令集系统(RISC-V)架构提出了一种新型的自适应全流程(ADFF)时钟树优化方法，高效利用有用偏差(useful skew)来优化高性能CPU时钟树，以满足市场对芯片高性能和低功耗的双重需求。针对时钟树，通过选择关键路径并结合理论延迟和缓冲器制造有用偏差，采用循环迭代的方式，在不同流程自适应修复常规流程无法解决的建立时间违例(setup violation)和保持时间违例(hold violation)。为了在提升性能的同时，最大限度降低功耗，该文对加入的延迟单元进行合并(merge)处理，实现功耗与时序的联合优化。最后采用RISC_V CPU核进行验证，研究结果表明，在确保合理功耗的基础上，所提方法显著改善了时序情况，总时序裕量违例几乎完全消除。
- 时钟树 /
- 有用偏差 /
- 自适应 /
- 时间违例 /
- 联合优化
Abstract: Objective With continuous advancements in Integrated Circuit (IC) process technology, chip integration levels have steadily increased, driving higher market demands for performance. In the era of intelligence and digitalization, an inherent challenge arises: as the number of logic gates increases, both main frequency and power consumption rise, imposing stricter requirements on digital IC designers. Although existing Electronic Design Automation (EDA) tools optimize timing using useful skew in clock trees, this technique has notable limitations. To address this issue, a novel adaptive full-flow clock tree timing violation correction method is proposed. This method corrects timing violations unresolved by conventional flows while reducing power consumption and improving performance, meeting the market’s dual demands for high-performance and low-power chips. Methods The ADaptive Full Flow (ADFF) clock tree optimization method is based on the RISC-V CPU architecture. As an open-source architecture, RISC-V offers openness and flexibility, making it widely used in high-performance, low-power processor design. The method exploits imbalances in key path logic depth to enhance optimization. Useful skew is introduced to adjust logic delay distribution, improving overall performance. Timing feedback is incorporated at multiple stages, ultimately forming a joint optimization strategy for power consumption and timing, which enhances clock tree quality and reduces chip load. The method integrates feedback optimization during both the Clock Tree Synthesis (CTS) and routing stages. In the CTS stage, timing paths are traversed to gather feedback, which is then returned to the pre-CTS stage for early intervention. Adaptive iteration accurately identifies critical paths and resolves setup time violations. In the routing stage, targeted strategies address hold time violations, and the merging method reduces power consumption while optimizing timing correction. This enables full-flow correction of clock tree timing violations while improving power efficiency. Results and Discussions The ADFF clock tree optimization strategy is implemented using Synopsys IC Compiler II for layout and routing, establishing an adaptive full-flow framework for correcting clock tree timing violations (Fig. 5). For setup time violations in the reg2reg group, a loop iteration algorithm dynamically adjusts path delays, updating CTS guidance files to iteratively optimize critical path timing (Fig. 6). Using the ADFF method, total timing violations are nearly eliminated, achieving a 55.6% efficiency improvement over the built-in auto useful skew function (Table 2). For hold time violations in the reg2mem group (Figs. 9 and 10), 125 buffers are inserted. Across 50 critical paths, the total timing margin improves significantly, reducing the worst slack from –362.2 ns to near zero (Table 3). To further optimize timing, when a clock signal is transmitted to two physically close registers, and buffers in the final clock path stage are used for timing correction, a merging plan consolidates multiple register buffers into a single delay unit (Fig. 11). Through a rigorous filtering mechanism in the script language, nearly 700 clock delay units are reduced while maintaining timing integrity. Additionally, clock network nets are reduced (Table 4), improving clock tree quality, achieving timing convergence, and enhancing overall design efficiency. Conclusions This paper proposes a novel ADFF clock tree optimization strategy that integrates loop iteration adjustment with IC Compiler II, leveraging useful skew for adaptive full-flow automatic correction of setup and hold time violations. The method extends the traditional concept and has demonstrated significant results on a high-performance RISC-V-based CPU, achieving a main clock frequency of 800 MHz. Compared to conventional timing optimization methods, this strategy resolves timing violations that standard layout and routing processes cannot address, significantly improving timing convergence. Through joint optimization of power consumption and timing, the method reduces the cost and power overhead associated with useful skew optimization and is applicable to CPU pipelines, providing a valuable reference for chip design. Future research may refine filtering conditions, optimize script traversal statements, and incorporate mainstream tool techniques to improve path selection efficiency while minimizing runtime overhead in large designs. Additionally, further refinement of the mathematical model could help identify more suitable targets for power optimization, improving overall performance.
- Clock tree /
- Useful skew /
- Adaptation /
- Timing violation /
- Joint optimization

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图 1 不同架构的关键路径(critical path)逻辑深度分布图

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图 2 时钟树基本层级结构

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图 3 同步时序电路基本模型

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图 4 建立时间和保持时间

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图 5 新型ADFF时钟树优化方法流程图

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图 6 useful skew修复setup violation循环流程图

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图 7 该路径的具体时序情况

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图 8 人工insert_buffer实例模型

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图 9 useful skew修复hold violation模型

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图 10 修复reg2mem的hold violation模型

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图 11 merge delay cell的物理实现

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图 12 net分支到reg_63的insert_buffer情况

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图 13 net分支到reg_10的insert_buffer情况

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图 14 merge操作前后版图变化情况

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表 1 工具设置不同postpone值的时钟树质量和时序情况

	Clock QoR			Timing QoR
工具auto useful skew的postpone值(ps)	Clock Cell(个)	Nets(个)	Latency(ns)	WNS(ns)	TNS(ns)
0	2547	264888	0.386	–0.260	–855.5
100	2920	265203	0.411	–0.228	–782.5
250	3251	265526	0.504	–0.193	–690.3

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1 基于时钟树综合的关键路径列表自适应时序优化算法

For i=1 to n
If (S_i>S_th and H_i>H_th) Then
If (P_i $\notin$ DelayList) Then
△=D₀
Else
D_i= D₀+△
△=D_i
DelayList ← DelayList∪{(P_i, D_i)}
WriteToGuidanceFile(P_i, D_i)
Run CTS

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2 基于后缀名筛选适合联合优化的时序路径算法

get_net -of [get_cells indelaybuffer -hier]
For i=1 to n get_pins -of nets
Size of_collection pins number=2

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表 2 不同优化方法reg2reg组测试时序情况(ns)

优化策略	时序路径组别	WNS	TNS	WNS (hold)	TNS (hold)
balance case	reg2reg(func_N40CSSG0P81_cworst_postcts)	–0.252	–876.3	–0.187	–45.8
auto useful skew	reg2reg(func_N40CSSG0P81_cworst_postcts)	–0.219	–597.2	–0.192	–54.1
ADFF(本文)	reg2reg(func_N40CSSG0P81_cworst_postcts)	–0.079	–9.100	–0.212	–72.7

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表 3 不同优化方法reg2mem组测试时序情况(ns)

优化策略	时序路径组别	WNS(hold)	TNS(hold)
balance case	reg2mem(func_125CFFG0P99_rcbest_postcts)	–0.199	–362.2
auto useful skew	reg2mem(func_125CFFG0P99_rcbest_postcts)	–0.162	–237.4
ADFF(本文)	reg2mem(func_125CFFG0P99_rcbest_postcts)	–0.024	–0.2

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表 4 不同情况下的时钟树质量和时序结果

	Clock QoR			Timing QoR
优化策略	Clock Cell(个)	Nets(个)	Latency(ns)	WNS(ns)	TNS(ns)	WNS(hold) (ns)	TNS(hold) (ns)
balance case	2962	272003	0.386	–0.252	–876.3	–0.238	–45.8
ADFF(不含merge)	3754	280599	0.411	–0.044	–9.100	–0.020	–0.201
ADFF(＋merge)	3095	274423	0.399	–0.040	–8.112	–0.014	–0.122

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