SMCA: A Framework for Scaling Chiplet-Based Computing-in-Memory Accelerators
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摘要: 基于可变电阻式随机存取存储器(ReRAM)的存算一体芯片已经成为加速深度学习应用的一种高效解决方案。随着智能化应用的不断发展,规模越来越大的深度学习模型对处理平台的计算和存储资源提出了更高的要求。然而,由于ReRAM器件的非理想性,基于ReRAM的大规模计算芯片面临着低良率与低可靠性的严峻挑战。多芯粒集成的芯片架构通过将多个小芯粒封装到单个芯片中,提高了芯片良率、降低了芯片制造成本,已经成为芯片设计的主要发展趋势。然而,相比于单片式芯片数据的片上传输,芯粒间的昂贵通信成为多芯粒集成芯片的性能瓶颈,限制了集成芯片的算力扩展。因此,该文提出一种基于芯粒集成的存算一体加速器扩展框架—SMCA。该框架通过对深度学习计算任务的自适应划分和基于可满足性模理论(SMT)的自动化任务部署,在芯粒集成的深度学习加速器上生成高能效、低传输开销的工作负载调度方案,实现系统性能与能效的有效提升。实验结果表明,与现有策略相比,SMCA为深度学习任务在集成芯片上自动生成的调度优化方案可以降低35%的芯粒间通信能耗。Abstract: Computing-in-Memory (CiM) architectures based on Resistive Random Access Memory (ReRAM) have been recognized as a promising solution to accelerate deep learning applications. As intelligent applications continue to evolve, deep learning models become larger and larger, which imposes higher demands on the computational and storage resources on processing platforms. However, due to the non-idealism of ReRAM, large-scale ReRAM-based computing systems face severe challenges of low yield and reliability. Chiplet-based architectures assemble multiple small chiplets into a single package, providing higher fabrication yield and lower manufacturing costs, which has become a primary trend in chip design. However, compared to on-chip wiring, the expensive inter-chiplet communication becomes a performance bottleneck for chiplet-based systems which limits the chip’s scalability. As the countermeasure, a novel scaling framework for chiplet-based CiM accelerators, SMCA (SMT-based CiM chiplet Acceleration) is proposed in this paper. This framework comprises an adaptive deep learning task partition strategy and an automated SMT-based workload deployment to generate the most energy-efficient DNN workload scheduling strategy with the minimum data transmission on chiplet-based deep learning accelerators, achieving effective improvement in system performance and efficiency. Experimental results show that compared to existing strategies, the SMCA-generated automatically schedule strategy can reduce the energy costs of inter-chiplet communication by 35%.
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Key words:
- Chiplet /
- Deep learning processor /
- Computing-in-Memory (CiM) /
- Task dispatching
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1 自适应层级网络划分策略
1: 输入:单个芯粒的固定算力M;网络$l({l_0},{l_1}, \cdots,{l_{L - 1}}) $的算力
需求$w({w_0},{w_1}, \cdots ,{w_{L - 1}}) $。2: 输出:网络划分策略bestP。 3: ${C_{{\text{idle}}}}{\text{ = M}} $; /*初始化${C_{{\text{idle}}}} $*/ 4: for $i = 0,1, \cdots ,L - 1 $ 5: if ${C_{{\text{idle}}}} \ge {w_i} $ then 6: ${\text{bestP}} \leftarrow {\text{NoPartition}}(i{\text{,}}{w_i}) $; 7: else if $\left\lceil {\dfrac{{{w_i}}}{{\text{M}}} = = \dfrac{{{w_i} - {C_{{\text{idle}}}}}}{{\text{M}}}} \right\rceil $ then 8: ${\text{bestP}} \leftarrow {\text{CMP}}(i{\text{,}}{w_i}) $; 9: else 10: ${\text{bestP}} \leftarrow {\text{CAP}}(i{\text{,}}{w_i}) $; 11: Update(${C_{{\text{idle}}}} $) 表 1 SMT约束中的符号表示
符号 含义 $ \boldsymbol{T},\boldsymbol{E},\boldsymbol{C} $ 计算任务集合,计算图中边的集合以及
芯片封装的芯粒集合$ t,c $ 计算任务$ t $,芯粒$ c $ $ {e}_{i,j} $ 计算图中,任务$ i $到到任务$ j $的有向边 $ {x}^{c},\;{y}^{c} $ 芯粒$ c $在芯片上的$ \left(x,y\right) $坐标 $ {w}^{t} $ 任务$ t $的计算需求 $ {o}^{t} $ 任务$ t $计算产生的中间数据量 $ {s}^{t} $ 任务$ t $的开始执行时间 $ {d}^{t} $ 完成任务t所有前置任务所需的芯粒间最小数据传输开销 $ {\tau }^{t} $ 任务$ t $的执行时间 $ \mathrm{s}{\mathrm{w}}^{c} $ 芯粒$ c $所在的波前编号 $ \mathrm{d}\mathrm{i}\mathrm{s}({c}_{i},{c}_{j}) $ 芯粒$ i $到芯粒$ j $的距离 表 2 系统配置
架构层次 属性 参数 封装 频率 1.8 GHz 芯粒间互联网络带宽 100 GB/s/Chiplet 芯粒间通信能耗 1.75 pj/bit 芯粒 工艺制程 16 nm 单个芯粒包含的计算核个数 16 单个计算核包含的ReRAM交叉
阵列个数16 计算核 ReRAM交叉阵列大小 128$ \times $128 ADC 1 bit DAC 8 bits 一个ReRAM单元存储的位数 2 权重精度 8 bits 数据流 权重固定型 -
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