两种面向宇航应用的高可靠性抗辐射加固技术静态随机存储器单元

闫爱斌; 李坤; 黄正峰; 倪天明; 徐辉

doi:10.11999/JEIT240082

两种面向宇航应用的高可靠性抗辐射加固技术静态随机存储器单元

doi: 10.11999/JEIT240082

1.
合肥工业大学微电子学院合肥 230601
2.
安徽工程大学集成电路学院芜湖 241000
3.
安徽理工大学计算机科学与工程学院淮南 232001

基金项目: 国家自然科学基金(61974001)

详细信息

作者简介:
闫爱斌：男，博士，教授，研究方向为数字电路可靠性技术等

李坤：男，硕士生，研究方向为SRAM单元容错技术

黄正峰：男，博士，教授，研究方向为数字集成电路容错设计等

倪天明：男，博士，教授，研究方向为数字集成电路可测性设计等

徐辉：男，博士，教授，研究方向为可信计算与人工智能等

通讯作者:
徐辉　austxuhui@163.com

中图分类号: TN43
计量
- 文章访问数: 72
- HTML全文浏览量: 34
- PDF下载量: 5
- 被引次数: 0
出版历程
- 收稿日期: 2024-02-04
- 修回日期: 2024-09-11
- 网络出版日期: 2024-09-16

Two Highly Reliable Radiation Hardened By Design Static Random Access Memory Cells for Aerospace Applications

1.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China
2.
School of Integrated Circuit, Anhui University of Engineering, Wuhu 241000, China
3.
School of Computer Science and Engineering, Anhui University of Science and Technology, Huainan 232001, China

Funds: The National Natural Science Foundation of China (61974001)

摘要

摘要: CMOS尺寸的大幅缩小引发电路可靠性问题。该文介绍了两种高可靠的基于设计的抗辐射加固(RHBD)10T和12T抗辐射加固技术(SRAM)单元，它们可以防护单节点翻转(SNU)和双节点翻转(DNU)。10T单元主要由两个交叉耦合的输入分离反相器组成，该单元可以通过其内部节点之间的反馈机制稳定地保持存储的值。由于仅使用少量晶体管，因此其在面积和功耗方面开销也较低。基于10T单元，提出了使用4个并行存取访问管的12T单元。与10T单元相比，12T单元的读/写访问时间更短，且具有相同的容错能力。仿真结果表明，所提单元可以从任意SNU和部分DNU中恢复。此外，与先进的加固SRAM单元相比，所提10T单元平均可以节省28.59%的写访问时间、55.83%的读访问时间和4.46%的功耗，而平均牺牲了4.04%的硅面积。
- CMOS /
- 静态随机存储器单元 /
- 抗辐射加固 /
- 单节点翻转 /
- 双节点翻转
Abstract: Aggressive scaling of CMOS technologies can cause the reliability issues of circuits. Two highly reliable Radiation Hardened By Design (RHBD) 10T and 12T Static Random-Access Memory (SRAM) cells are presented in this paper, which can protect against Single Node Upsets (SNUs) and Double Node Upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed 10T cell can save 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.
- CMOS /
- Static Random Access Memory (SRAM) cell /
- Radiation hardening /
- Single node upset /
- Double node upset

HTML全文

图 1 所提RHBD10T单元电路图

下载: 全尺寸图片幻灯片

图 2 所提RHBD10T单元版图

下载: 全尺寸图片幻灯片

图 3 所提RHBD10T单元正常操作的仿真结果

下载: 全尺寸图片幻灯片

图 4 所提 RHBD10T单元的SNU自恢复仿真结果

下载: 全尺寸图片幻灯片

图 5 所提 RHBD10T 单元的 DNU 的仿真结果

下载: 全尺寸图片幻灯片

图 6 所提RHBD12T单元电路图

下载: 全尺寸图片幻灯片

图 7 所提 RHBD12T单元的版图

下载: 全尺寸图片幻灯片

图 8 温度与电压变化对 SRAM 设计的 RAT,WAT 和功耗影响的仿真结果

下载: 全尺寸图片幻灯片

图 9 阙值电压和沟道长度变化对SCRM的RAT, WAT和功耗的影响的仿真结果

下载: 全尺寸图片幻灯片

图 10 电压0.8 V下的SNM比较

下载: 全尺寸图片幻灯片

表 1 未加固/加固 SRAM 单元之间的可靠性和开销比较结果

SRAM	6T	NASA 13T	RHD 12T	QCCM 12T	QUCCE 12T	DNU SRM	We-Quatro	Zhang 14T	QCCM 10T	RHSC 12T	SAR 14T	RHBD 10T	RHBD 12T
文献	–	[18]	[19]	[20]	[21]	[22]	[23]	[24]	[20]	[26]	[27]	本文	本文
SNUR	×	×	√	×	×	√	×	×	×	√	√	√	√
#DHP	0	0	2	1	0	16	2	0	1	0	0	4	4
RAT (ps)	26.55	128.67	25.72	12.99	13.02	6.63	12.99	51.2	18.20	36.89	32.92	25.88	11.21
WAT (ps)	4.11	18.2	5.06	4.22	4.31	4.71	4.38	4.09	23.21	3.83	4.84	7.11	4.21
功耗(nW)	5.24	18.92	10.38	10.43	10.43	20.86	10.43	7.78	11.45	8.93	10.6	9.02	9.32
10^–3×面积(nm²)	4.35	9.07	8.27	8.71	8.71	17.42	8.71	10.25	7.79	8.71	12.44	7.30	8.71

下载: 导出CSV

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