Cost-Effective TMR Soft Error Tolerance Technique for Commercial Aerospace: Utilization of Approximate Computing
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摘要: 三模冗余(TMR)作为如今集成电路可靠性领域中最为常用且有效的软错误加固技术，在满足高容错要求之时，不可避免地牺牲了庞大的硬件损耗。为实现面积、功耗等硬件性能和容错电路加固能力的折中考虑，适应低成本高可靠性加固的时代需求，针对基于近似计算的三模冗余加固技术(ATMR)进行研究，该文提出一种基于近似门单元(ApxLib)的动态调整多目标优化框架(ApxLib+DAMOO)。首先，其基本优化框架采用非支配排序遗传算法(NSGA-II)实现， 通过极性分析与预创建的近似库对电路实现快速近似。随后，该框架提出动态概率调整和极性扩张两种创新机制，根据可测性分析对遗传算法中门单元的突变概率进行动态更新，对双向门单元进行定向识别和重构，以实现寻优效率和寻优效果的双重优化。实验结果表明，该文提出的优化框架与传统NSGA-II相比，在相同硬件损耗下可实现最大10%～20%的额外软错误率(SER)降低，且其执行时间平均降低18.7%。Abstract: Triple Modular Redundancy (TMR), as the most prevalent and effective technique for soft error mitigation technique, inevitably incurs substantial hardware overhead while meeting high fault-tolerance requirements. To achieve the trade-off between area, power and fault coverage and meet the requirement of low-cost and high-reliability circuit design, Approximate Triple Modular Redundancy (ATMR) is investigated and a Dynamic Adjustment Multi-Objective Optimization Framework based on Approximate Gate Library (ApxLib+DAMOO) is investigated. The basic optimization framework employs Non-dominated Sorting Genetic Algorithm II (NSGA-II), achieving rapidly approximation through parity analysis and the pre-established ApxLib. Subsequently, the framework introduces two novel mechanisms: dynamic probability adjustment and parity expansion. The first mechanism dynamically updates the mutation probability of gates in the genetic algorithm based on testability analysis, while the second mechanism performs recognition and reconstruction for binate gates to achieve dual optimization of efficiency and effectiveness in optimization. Experimental results indicate that the proposed optimization framework achieves an additional Soft Error Rate (SER) reduction of up to 10%～20% compared to traditional NSGA-II with the same hardware overhead, while reducing 18.7% of execution time reduction averagely.
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表 1 可测性分析与突变概率转换表
近似选项 可控性 可观察性 可测性 突变概率 g1_under_apx 0.2500 0.25 0.0625 0.461 g2_under_apx 0.3750 0.50 0.1875 0.155 g1_over_apx 0.7500 0.25 0.1875 0.155 g2_over_apx 0.6250 0.50 0.3125 0.093 g3_under_apx 0.3125 1.00 0.3125 0.093 g3_over_apx 0.6875 1.00 0.6875 0.043 
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表 3 基准电路信息
基准电路 #输入数量 #输出数量 #门单元数量 c432 36 7 160 c499 41 32 202 c880 60 26 383 c1355 41 32 546
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表 4 基准电路加固结果比较(%)
电路 DA-MOO NSGA-II TMR 面积(+) 功耗(+) 软错误率(–) 面积(+) 功耗(+) 软错误率(–) 面积(+) 功耗(+) 软错误率(–) c432 128.2 138.0 71.9 130.4 138.4 73.7 220.8 237.5 100 c499 158.3 159.3 78.3 153.8 164.2 75.7 231.7 221.1 100 c880 141.8 153.7 70.3 163.4 169.8 71.8 226.0 243.0 100 c1355 131.8 114.4 73.6 133.6 117.1 72.3 231.7 220.0 100 均值 140.0 141.4 73.5 145.3 147.4 73.4 227.6 230.4 100
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表 5 c880应用DA-MOO的最终加固方案(%)
ATMR电路 额外面积
损耗额外功耗
损耗软错误率 非保护
输出占比未加固电路 0 0 100.0 100.0 ATMR1 46.9 37.4 53.6 52.1 ATMR2 83.3 90.6 36.9 34.6 ATMR3 125.9 125.6 32.6 15.8 ATMR4 152.4 167.6 26.2 13.9 ATMR5 179.5 179.1 17.1 11.8 ATMR6 190.0 195.7 10.5 7.3 ATMR7 201.9 214.1 6.4 4.9 ATMR8 211.5 229.6 2.5 2.3 TMR 226.0 243.0 0 0
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