一种用于常开型智能视觉感算系统的极速高精度模拟减法器

刘博; 王想军; 麦麦提·那扎买提; 郑辞晏; 向菲; 魏琦; 杨兴华; 乔飞

doi:10.11999/JEIT231099

一种用于常开型智能视觉感算系统的极速高精度模拟减法器

doi: 10.11999/JEIT231099

1.
河南科技大学信息工程学院洛阳 471023
2.
清华大学北京 100084
3.
广东技术师范大学广州 510665
4.
北京林业大学理学院北京 100091

基金项目: 国家自然科学基金(92164203, 62334006, 61704049)，新疆维吾尔自治区重点研发计划(2022B01008)，河南省科技攻关计划(232102211066, 242102211101)，河南省高校青年骨干教师计划(2020GGJS077)

详细信息

作者简介:
刘博：男，副教授，研究方向为生物感算一体及通信芯片设计及其应用系统

王想军：男，硕士生，研究方向为智能视觉感知集成电路

麦麦提·那扎买提：男，博士研究生，研究方向为超低功耗智能视觉感知芯片设计，面向视觉感知的能量采集和能量管理架构和电路设计

郑辞晏：女，副教授，研究方向为基于忆阻器的信号感知与处理电路设计

向菲：女，副教授，研究方向为信息安全和保密通信技术

魏琦：男，副研究员，研究方向为集成电路设计

杨兴华：男，讲师，研究方向为近似计算电路系统设计

乔飞：男，副研究员，研究方向为智能感知集成电路与系统

通讯作者:
乔飞　qiaofei@tsinghua.edu.cn

中图分类号: TN911.73; TN492
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- 被引次数: 0
出版历程
- 收稿日期: 2023-10-10
- 修回日期: 2024-08-24
- 网络出版日期: 2024-08-30
- 刊出日期: 2024-09-26

Ultra High-speed High-precision Analog Subtractor Applied to Always-on Intelligent Visual Sense-computing System

1.
College of Information Engineering, Henan University of Science and Technology, Luoyang 471023, China
2.
Tsinghua University, Beijing 100084, China
3.
Guangdong Polytechnic Normal University, Guangzhou 510665, China
4.
College of Science, Beijing Forestry University, Beijing 100091, China

Funds: The National Natural Science Foundation of China (92164203, 62334006, 61704049), The Key Research and Development Program of Xinjiang Uygur Autonomous Region (2022B01008), The Key Science and Technology Program of Henan Province (232102211066, 242102211101) , The Young Teacher Talent Program of Henan Province (2020GGJS077)

摘要

摘要: 常开型智能视觉感算系统对图像边缘特征提取的精度和实时性要求更高，其硬件能耗也随之暴增。采用模拟减法器代替传统数字处理在模拟域同步实现感知和边缘特征提取，可有效降低感存算一体系统的整体能耗，但与此同时，突破10^–7 s数量级的长计算时间也成为了模拟减法器设计的瓶颈。该文提出一种新型的模拟减法运算电路结构，由模拟域的信号采样和减法运算两个功能电路组成。信号采样电路进一步由经改进的自举采样开关和采样电容组成；减法运算则由所提出的一种新型开关电容式模拟减法电路执行，可在2次采样时间内实现3次减法运算的高速并行处理。基于TSMC 180 nm/1.8 V CMOS工艺，完成整体模拟减法运算电路的设计。仿真实验结果表明，该减法器能够实现在模拟域中信号采样与计算的同步并行处理，一次并行处理的周期仅为20 ns，具备高速计算能力；减法器的计算取值范围宽至–900～900 mV，相对误差小于1.65%，最低仅为0.1%左右，处理精度高；电路能耗为25～27.8 pJ，处于中等可接受水平。综上，所提模拟减法器具备良好的速度、精度和能耗的性能平衡，可有效适用于高性能常开型智能视觉感知系统。
- 模拟减法器 /
- 自举采样开关 /
- 电荷守恒定律 /
- 极速 /
- 高精度
Abstract: Always-on intelligent visual sense-computing (Senputing) system has higher requirement on the accuracy and real-time of edge feature extraction on target image, and thus the accompanying hardware energy consumption increases accordingly. Since an analog subtracter can realize visual sensing and edge feature extraction synchronously in analogue domain instead of the traditional digital processing, the overall energy consumption of sensing-storage-computing integrated system can be effectively reduced. But meanwhile, the long calculation time beyond the order of 10^–7 s has also become the bottleneck of design of analog subtracter circuits. A novel analogue subtraction circuit structure is proposed in this paper, which consists of two functional circuits in analogue domain: signal sampling and subtraction module. The signal sampling circuit is further composed of an improved bootstrapped sampling switch and a pair of sampling capacitors; The subtraction operation is performed by a novel switched capacitor analog subtraction circuit, which can realize high-speed parallel processing of three subtraction operations in two sampling times. Based on TSMC 180 nm/1.8 V CMOS technology, the design of the whole analog subtraction circuit is implemented. The simulation results show that, The proposed analog subtracter can realize synchronous parallel processing of signal sampling and computation in analogue domain, and the cycle of one parallel processing is only 20 ns, which has high-speed computing capability. The calculated value range of the subtracter is sufficiently wide from –900～900 mV, the relative error is less than 1.65%, the lowest one is only about 0.1%, which proves that the computing accuracy is high; The energy consumption is 25～27.8 pJ, which is in the acceptable medium level. Therefore, the proposed analog subtracter has a significant performance trade-off on speed, precision and energy consumption, and can be effectively applied to high-performance always-on intelligent visual senputing system.
- Analog subtractor /
- Bootstrap sample switch /
- Charge conservation law /
- Ultra high-speed /
- High-precision

HTML全文

图 1 视觉感知系统最前端 CIS信号接收过程抽象图

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图 2 两种常用减法运算电路架构

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图 3 2次采样完成3次减法运算的电阻式模拟减法器

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图 4 电阻式模拟减法器的运算时序图

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图 5 结合采样保持功能的基于单运放实现3次减法运算的开关电容式模拟减法运算电路

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图 6 减法器3次减法运算功能示意图

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图 7 常规的栅压自举采样开关

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图 8 所提自举采样开关

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图 9 自举采样开关的瞬态仿真结果

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图 10 自举采样开关基于DFT的频谱及动态性能

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图 11 理想的减法计算差值与减法电路的仿真输出结果对比

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图 12 不同的减法器差值输出对应的误差采样曲线

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图 13 整体模拟域减法运算电路的计算值与仿真值的对比

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图 14 不同的减法器差值输出对应的误差采样曲线

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图 15 模拟减法器计算值与能耗的曲线

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表 1 本文设计与他参考文献各指标对比

指标参数	2023年^[22]	2022年^[23]	2021年^[24]	2020年^[25]	本文
工艺(nm)	180	180	180	180	180
电源电压(V)	1.8	1.8	1.2	1.8	1.8
采样率(MS/s)	50	50	50	1	100
ENOB(bit)	16.5	16.5	13.6	14	16.79
SNDR(dB)	101.1	101.11	83.7	86.94	102.85
SFDR(dBc)	101.8	101.83	83.9	87.32	103.09
THD(dB)	N/A	–101.2	–83.7	–87.3	–103.08

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表 2 本文提出的模拟减法运算电路与其他设计案例的对比

文献	工作类型	工艺尺寸(nm)	电源电压(V)	总计算时间(μs )	能耗(nJ )	计算误差(%)
本文	开关电容式模拟减法器	180	1.8	0.02	0.0278^b	<1.65
[14]	KCL电流模式减法器	350	–	0.45^a	50000^b	<3^c
[15]	开关电容式模拟减法器	180	0.56 /0.8	1220^a	0.0125^b	–
[19]	忆阻器式模拟减法器	180	4	0.2^a	0.019^b	–
[20]	开关电容式模拟减法器	180	1.8	2	8.67^b	<12.73
注：a: 每一帧的处理时间；b: 每一帧能耗；c: 像素不匹配误差

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